DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I (Claims 1-15 and 21-25) in the reply filed on 07/08/2026is acknowledged.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the
“in forming the base epitaxy layers, an upper surface of each of the base epitaxy layers is at a level higher than a level of a bottom surface of each of two corresponding adjacent ones of the stack portions.” of claim 8.
must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
Claims 6 and 12 recite “first films and second films that alternate with the first films” and “recessing the second films” This terminology was substituted, by amendment, for “nanosheets” (“first nanosheets and second nanosheets” of Claim 1)
The Specification and drawings consistently and exclusively use “nanosheet material layers” (210, 220) “nanosheet layers” (21’, 22’) and “nanosheets” (21. 22, 21A, 21B).
The term “first films” and “second films” do not appear anywhere in the written description or in figures of the specification as filed. Further, specification never establishes “film” as synonymous with “nanosheet”.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1-15, 21-25 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 10 and 21 recite a series of active method steps (“forming…; forming…; forming trenches…, after forming the trenches, the stack being formed into stack portions which are respectively beneath the gate structures; forming base epitaxy layers…”) The clause “the stack being formed into stack portions” breaks the structure used for every other step and is not set up as its own claimed step. It is unclear whether this clause recites a distinct, required manufacturing step (“forming the stack into stack portion”) or merely describes and outcome of the immediately preceding “forming trenches” step (“thereby forming the stack into stack portions”). As presently drafted, the metes and bounds of the steps actually required by the clause are unclear.
For the purposes of examination, the Examiner will treat “the stack being formed into stack portions” as being an outcome of the “forming trenches” step.
Claims 2-9 are being rejected as being dependent on Claim 1.
Claims 11-15 are being rejected as being dependent on Claim 10.
Claims 22-25 are being rejected as being dependent on Claim 21.
Claim 9 recites “has a blocking feature which includes the dopants, which is configured as a continuous structure and which has a width that is not smaller than a width of a respective one of the source/drain portions.”
The repeated use of “which “ in series creates a chain of relative whose antecedent (“a blocking feature”, the doped epitaxy layers” , “the dopants”) is not clearly signaled by the grammar.
For the purposes of examination, the Examiner will treat the claim--- has a blocking feature which includes the dopants, is configured as a continuous structure and has a width that is not smaller than a width of a respective one of the source/drain portions.—
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 24 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 24 recites “the doped middle portion interconnects two portions of the base structure.”.
The Examiner notes that originally filed specification does not reasonably convey that a doped middle portion that “interconnects two portions of” whatever “base structure” refers to. Further, the Applicant did not explicitly point out where in originally filed specification support of the limitation can be found.
Therefore, “the doped middle portion interconnects two portions of the base structure.” is new matter.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 10, 14 and 15 is/are rejected under 35 U.S.C. 102(A2) as being anticipated by Kim et al. (US 2013/0411529 A1).
Regarding Claim 10, Kim (Fig. 18-19, 45-49) discloses a method for manufacturing a semiconductor structure, comprising:
forming a stack (U_AP) on a substrate (BP1);
forming gate structures (130P, 120P, 140P) on the stack, the gate structures (130P, 120P, 140P) being spaced apart from each other such that portions of the stack are exposed from the gate structures; (See Fig. 46)
forming trenches (115R) respectively in the portions of the stack and respectively extending into upper portions of the substrate (BP1), after forming the trenches (115R), the stack being formed into stack portions (U_AP under 130P, 120P, 140P) which are respectively beneath the gate structures (130P, 120P, 140P);
forming treated base epitaxy layers (115) respectively at bottoms of the trenches (150R), at least one of each of the treated base epitaxy layers including an undoped upper portion (upper 117), an undoped lower portion (lower 117), and a doped middle portion (“the point blocking film 116 may be an oxygen-doped crystalline silicon film”) interposed between the undoped lower portion (upper 117) and the undoped upper portion (lower 117); and
forming source/drain portions (150) respectively in the trenches (150R) on the treated base epitaxy layers (115) such that at least one of the source/drain portions (150) is isolated from the substrate (BP1) through the doped middle portion (116) of the at least one of the treated base epitaxy layers (115). [0188, 0192]
Regarding Claim 14, Kim discloses the method according to claim 10, wherein for the at least one of each of-the treated base epitaxy layers (150), the doped middle portion (116) is covered by the undoped upper portion (upper 117).
Regarding Claim 15, Kim discloses the method according to claim 14, wherein for the at least one of the treated base epitaxy layers (115), the undoped upper portion (upper 117) fully covers the doped middle portion (116) . (Fig. Fig. 18-19)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 9, 11, 12, 21-23 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2013/0411529 A1) in view of Chang et al. (US 2022/0359696 A1).
Regarding Claim 1, Kim (Fig. 45-49) discloses a method for manufacturing a semiconductor structure, comprising:
forming a stack (U_AP) on a substrate (BP1);
forming gate structures (130P, 120P, 140P) on the stack (U_AP), the gate structures being spaced apart from each other such that portions of the stack are exposed from the gate structures (See Fig. 46);
forming trenches (115R) respectively in the portions of the stack and respectively extending into upper portions of the substrate (BP1), after forming the trenches (115R), the stack being formed into stack portions (U_AP under 130P, 120P, 140P) which are respectively beneath the gate structures (130P, 120P, 140P);
forming base epitaxy layers (115) respectively at bottoms of the trenches (150R);
“The point blocking structure 115 may include at least one or more point blocking films 116. The point blocking structure 115 may include a point insertion semiconductor film 117” (0188, 0192)
performing a process to dope dopants into the base epitaxy layers so as to obtain doped base epitaxy layers;
(“The point blocking film 116 may be an oxygen-doped crystalline silicon film. The point blocking film 116 is in a state in which the crystalline silicon film is doped with oxygen”) [0192, 0198]
forming source/drain portions (150) respectively in the trenches on the doped base epitaxy layers (115) such that the source/drain portions are isolated from the substrate (BP1) respectively through the doped base epitaxy layers (115).
Kim does not explicitly disclose performing an ion implantation process to dope dopants into the base epitaxy layers so as to obtain doped base epitaxy layers.
Chang (Fig. 11) discloses performing an ion implantation process to dope dopants into a base so as to obtain doped base. [0044, 0050]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a method for manufacturing a semiconductor structure in Kim in view of Chang such that performing an ion implantation process to dope dopants into the base epitaxy layers so as to obtain doped base epitaxy layers in order to block current leakage in the substrate flowing from source region to drain region when the gate is in an “off” state [0049, 0053-0055].
Regarding Claim 2, Kim in view of Chang discloses the method for manufacturing a method according to claim 1,
Kim in view of Chang does not explicitly disclose the dopants include one of oxygen and nitrogen.
However, Chag discloses the dopants include one of oxygen and nitrogen omong limited number of dopants. [0045-0050]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a method for manufacturing a semiconductor structure in Kim in view of Chang such that the dopants include one of oxygen and nitrogen in order to block current leakage in the substrate flowing from source region to drain region when the gate is in an “off” state [0049, 0053-0055] and since the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) (See MPEP 2144.07).
Regarding Claim 3, Kim in view of Chang discloses the method according to claim 2, wherein, in the ion implantation process, a dosage level of the dopants is in a range from 1×10.sup.16 cm.sup.−2 to 1×10.sup.18 cm.sup.−2.
Kim in view of Chang does not explicitly disclose the ion implantation process, a dosage level of the dopants is in a range from 1×10.sup.16 cm.sup.−2 to 1×10.sup.18 cm.sup.−2.
However, Chang discloses an ion implantation process, a dosage level of the dopants is in a range from 1E10.sup.12 atoms/cm.sup.2 to about 3E10.sup.22 atoms/cm.sup.2, such as about 1E10.sup.16 atoms/cm.sup.2 to about 6E10.sup.15 atoms/cm.sup.2, which may vary depending on the mass and intended purpose of the ions. [0049]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a method for manufacturing a semiconductor structure in Kim in view of Chang such that the ion implantation process, a dosage level of the dopants is in a range from 1×10.sup.16 cm.sup.−2 to 1×10.sup.18 cm.sup.−2 to block current leakage in the substrate flowing from source region to drain region when the gate is in an “off” state [0049, 0053-0055] and since it has been held that the general conditions of a claim are disclosed in a prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding Claim 4, Kim in view of Chang discloses the method according to claim 1, wherein the ion implantation process is performed at a temperature (“ion implantation process 139 is a high-temperature implantation process performed at a temperature greater than about 250 degrees Celsius, such as about 350 degrees Celsius to about 550 degrees Celsius”) [0068 Chang].
Kim in view of Chang does not explicitly disclose that a temperature is not less than 500° C.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a method for manufacturing a semiconductor structure in Kim in view of Chang such a temperature is not less than 500° C since it has been held that the general conditions of a claim are disclosed in a prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding Claim 5, Kim in view of Chang discloses the method according to claim 1, further comprising,
after the ion implantation process and prior to forming the source/drain portions (167), performing an annealing process [0064, 0072-007; Chang]
Regarding Claim 6, Kim in view of Chang discloses the method according to claim 1, wherein
each of the stack portions includes first films (CS_L) and second films (ACT_L) that alternate with the first films, and the method further comprises,
after forming the trenches (115r) and prior to forming the base epitaxy layers (115),
Kim in view of Chang as previously combined does not explicitly disclose recessing the second films of each two adjacent ones of the stack portions through a respective one of the trenches, so as to form multiple pairs of lateral recesses; and forming multiple pairs of inner spacers respectively in the multiple pairs of lateral recesses.
However, Chang (Fig. 10) discloses recessing a second films nanosheets (108) of each two adjacent ones of the stack portions through a respective one of the trenches (trenches between 104), so as to form multiple pairs of lateral recesses (“The removal of the edge portions of the second semiconductor layers 108 forms cavities”); [0042] and
forming multiple pairs of inner spacers (144) respectively in the multiple pairs of lateral recesses. (“recesses”) [0043-0044]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a method for manufacturing a semiconductor structure in Kim in view of Chang such that recessing the second films of each two adjacent ones of the stack portions through a respective one of the trenches, so as to form multiple pairs of lateral recesses; and forming multiple pairs of inner spacers respectively in the multiple pairs of lateral recesses in order to pattern GAA structure [0019].
Regarding Claim 9, Kim in view of Chang discloses the method according to claim 1, wherein
each of the doped base epitaxy layers (115R) has a blocking feature which includes the dopants (115R), which
is configured as a continuous structure and which has a width that is not smaller than a width of a respective one of the source/drain portions (150 Kim). (See widths in Chang Fig. 11) (See widths in Kim Fig. 48).
Regarding Claim 11, Kim (Fig. 17-20, 45-49) discloses a method according to claim 10, wherein
each of the treated base epitaxy layers (150) includes the undoped upper portion (upper 117) , the undoped lower portion (lower 117), and the doped middle portion (116), and forming the treated base epitaxy layers includes:
forming base epitaxy layers (117) respectively at the bottoms of the trenches (115R);
Kim does not explicitly discloses performing an ion implantation process to dope dopants into middle portions of the base epitaxy layers; and after performing the ion implantation process, performing an annealing process to anneal the base epitaxy layers, so that the base epitaxy layers are formed into the treated base epitaxy layers.
Chang (Fig. 11) discloses performing an ion implantation process to dope dopants into a base so as to obtain doped base. [0044, 0050] and after performing the ion implantation process, performing an annealing process to anneal the base epitaxy layers, so that the base epitaxy layers are formed into the treated base epitaxy layers. [0064, 0072-007; Chang]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a method for manufacturing a semiconductor structure in Kim in view of Chang such that performing an ion implantation process to dope dopants into middle portions of the base epitaxy layers; and after performing the ion implantation process, performing an annealing process to anneal the base epitaxy layers, so that the base epitaxy layers are formed into the treated base epitaxy layers in order to block current leakage in the substrate flowing from source region to drain region when the gate is in an “off” state [0049, 0053-0055].
Examiner notes: Regarding the language of " so that the base epitaxy layers are formed into the treated base epitaxy layers ", the examiner notes that such language merely recites an intended outcome or result of the positively recited method step of " performing an annealing process ". The examiner notes recitations directed to the intended use/outcome/result of a specific step in a method claim does not narrow scope of the method claim past the specific recited step. See MPEP § 2106 II C and MPEP § 2111.04. As such, the claim as currently written does not actually require " the base epitaxy layers are formed into the treated base epitaxy layers. ", but merely requires " performing an annealing process to anneal the base epitaxy layers ", which is taught by the prior art of Kim in view of Chang.
Regarding Claim 12, Kim in view of Chang discloses method according to claim 11, wherein
each of the stack portions includes first films (SC_L) and second films (ACT_T) that alternate with the first films, and the method further comprises, after forming the trenches (115R) and prior to forming the base epitaxy layers (115R),
Kim in view of Chang as previously does not explicitly disclose recessing the second films of each two adjacent ones of the stack portions through a respective one of the trenches, so as to form multiple pairs of lateral recesses; and forming multiple pairs of inner spacers respectively in the multiple pairs of lateral recesses.
However, Chang (Fig. 10) discloses recessing a second films nanosheets (108) of each two adjacent ones of the stack portions through a respective one of the trenches (trenches between 104), so as to form multiple pairs of lateral recesses (“The removal of the edge portions of the second semiconductor layers 108 forms cavities”); [0042] and
forming multiple pairs of inner spacers (144) respectively in the multiple pairs of lateral recesses. (“recesses”) [0043-0044]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a method for manufacturing a semiconductor structure in Kim in view of Chang such that recessing the second films of each two adjacent ones of the stack portions through a respective one of the trenches, so as to form multiple pairs of lateral recesses; and forming multiple pairs of inner spacers respectively in the multiple pairs of lateral recesses in order to pattern GAA structure [0019].
Regarding Claim 21, Kim (Fig. 18-20, 45-49) discloses the method for manufacturing a semiconductor structure, comprising:
forming a stack (U_AP) on a base structure (BP1);
(130P, 120P, 140P) on the stack (U_AP), the gate structures being spaced apart from each other such that portions of the stack are exposed from the gate structures (See Fig. 46);
forming trenches (115R) respectively in the portions of the stack and respectively extending into upper portions of the substrate (BP1), after forming the trenches (115R), the stack being formed into stack portions (U_AP under 130P, 120P, 140P) which are respectively beneath the gate structures (130P, 120P, 140P);
forming base epitaxy layers (115) respectively at bottoms of the trenches (150R);
Kim does not explicitly disclose forming a spacer layer over the gate structures and the stack portions while exposing the base epitaxy layers; after forming the spacer layer, performing an ion implantation process to dope dopants into the base epitaxy layers so as to obtain doped base epitaxy layers; and removing the spacer layer after the ion implantation process.
Chang (Fig. 11-13) discloses forming a spacer layer (141) over a gate structures (132, 134, 136) and a stack portions (104) while exposing a base (bottom 141);
after forming the spacer layer (141), performing an ion implantation process (139) (139) to dope dopants into the base so as to obtain doped base (147); [0044, 0050] and
removing the spacer layer (141) after the ion implantation process (139).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a method for manufacturing a semiconductor structure in Kim in view of Chang such that forming a spacer layer over the gate structures and the stack portions while exposing the base epitaxy layers; after forming the spacer layer, performing an ion implantation process to dope dopants into the base epitaxy layers so as to obtain doped base epitaxy layers; and removing the spacer layer after the ion implantation process in order to block current leakage in the substrate flowing from source region to drain region when the gate is in an “off” state [0049, 0053-0055].
Regarding Claim 22, Kim in view of Chang discloses the method according to claim 21, wherein the spacer layer has a thickness ranging from 1 nm to 4 nm. [0195-0202] (“The thickness of the pair of point blocking films 116 and point insertion semiconductor films 117 may be, for example, 10 Å to 100 Å.”)
Regarding Claim 23, Kim in view of Chang discloses the method according to claim 21, wherein at least one of the doped base epitaxy layers has an undoped upper portion (upper 117), an undoped lower portion (lower 117), and a doped middle portion (116) interposed between the undoped lower portion (lower 117) and the undoped upper portion. (upper 117)
Regarding Claim 25, Kim in view of Chang discloses the method according to claim 23, wherein the undoped upper portion includes silicon with a single crystal structure. (“The point insertion semiconductor film 117 may be a crystalline silicon film.”) [0192]
Claim(s) 7, 8, 13 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2013/0411529 A1) in view of Chang et al. (US 2022/0359696 A1) and further in view of Son et al. (US 2020/0303521 A1).
Regarding Claim 7, Kim in view of Chang discloses the method according to claim 6, wherein
the blocking feature in each of the doped base epitaxy layers has a blocking feature which includes the dopants and which
Kim in view of Chang does not explicitly disclose interfaces is in direct contact with a bottommost pair of the inner spacers in the respective one of the trenches.
Son (Fig. 17-19) discloses doped base epitaxy layers (132) interfaces is in direct contact with a bottommost pair of an inner spacers (120) in the respective one of a trenches ( R1)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a method for manufacturing a semiconductor structure in Kim in view of Chang and Son such that interfaces is in direct contact with a bottommost pair of the inner spacers in the respective one of the trenches in order to have Anti-punch-through semiconductor layer filling the recess and optionally contacting the lowest nanosheet sidewall and helps suppress bottom leakage [0036, 0048-0052].
Regarding Claim 8, Kim in view of Chang discloses the method according to claim 1, wherein
Kim in view of Chang does not explicitly disclose in forming the base epitaxy layers, an upper surface of each of the base epitaxy layers is at a level higher than a level of a bottom surface of each of two corresponding adjacent ones of the stack portions.
Son (Fig. 17-19) discloses in forming a base epitaxy layers (132), an upper surface of each of the base epitaxy layers (132) is at a level higher than a level of a bottom surface of each of two corresponding adjacent ones of a stack portions (104, NSS).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a method for manufacturing a semiconductor structure in Kim in view of Chang and Son such that interfaces is in direct contact with a bottommost pair of the inner spacers in the respective one of the trenches in order to have anti-punch-through semiconductor layer filling the recess and optionally contacting the lowest nanosheet sidewall and helps suppress bottom leakage [0036, 0048-0052]
Regarding Claim 13, Kim in view of Chang discloses the method according to claim 12,
Kim in view of Chang does not explicitly disclose each of the treated base epitaxy layers is formed to at least partially cover a bottommost pair of the multiple pairs of inner spacers in the respective one of the trenches.
Son (Fig. 17-19) discloses each of the treated base epitaxy layers (132) is formed to at least partially cover a bottommost pair of the multiple pairs (120) of inner spacers in the respective one of a trenches. (R1)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a method for manufacturing a semiconductor structure in Kim in view of Chang and Son such that each of the treated base epitaxy layers is formed to at least partially cover a bottommost pair of the multiple pairs of inner spacers in the respective one of the trenches in order to have anti-punch-through semiconductor layer filling the recess and optionally contacting the lowest nanosheet sidewall and helps suppress bottom leakage [0036, 0048-0052].
Regarding Claim 24, Kim in view of Chang discloses the method according to claim 23, wherein
the doped middle portion (116) interconnects two portions of the base structure. (BP!)
Kim in view of Chang does not explicitly disclose the undoped upper portion is at a level higher than a level of an upper surface of the base structure.
Son (Fig. 19) discloses an undoped upper portion (132A) (“ anti-punch-through semiconductor layers 132 may each include an undoped semiconductor layer”) [0036] is at a level higher than a level of an upper surface of a base structure (102).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a method for manufacturing a semiconductor structure in Kim in view of Chang and Son such that the undoped upper portion is at a level higher than a level of an upper surface of the base structure. in order to have anti-punch-through semiconductor layer filling the recess and optionally contacting the lowest nanosheet sidewall and helps suppress bottom leakage [0036, 0048-0052].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRIY YEMELYANOV whose telephone number is (571)270-7920. The examiner can normally be reached M-F 9a.m.-6p.m.
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/DMITRIY YEMELYANOV/ Examiner, Art Unit 2891
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