DETAILED ACTION
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment
Acknowledgment is made of applicant's Amendment, filed 02-27-2026. The changes and remarks disclosed therein have been considered.
Claim(s) 1 and 5 has/have been amended, and claim(s) 1-21 remain(s) pending in the application.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the erase gate lines arranged in a first direction and bit lines arranged in a second direction perpendicular to the first direction, as disclosed in claim 7, source lines, control gate lines, word lines, erase gate lines, and bit lines arranged in a single direction, as disclosed in claim 8, erase gate lines arranged in a first direction and control gate lines and bit lines arranged in a second direction perpendicular to the first direction, as disclosed in claim 9, erase gate lines arranged in a first direction and word lines and bit lines arranged in a second direction perpendicular to the first direction, as disclosed in claim 10 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 7-10 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claims 7-10 attribute a first and second direction to various control lines and spatial relationship between them, but the specification only discloses circuit schematics. Schematics are abstract representation of circuits to aid in reading the circuit, and are not physical layouts of fabricated circuits, thus the directions and spatial relationship between the various control lines of claims 7-10 are not properly disclosed in the original specification, and thus not enabled to one of ordinary skill in the art.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1-4, and 6-13 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim(s) 1 recite(s) the language (emphasis added) “by increasing or decreasing the voltage level”, where “the voltage level” lacks antecedent basis.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 4, and 6-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mehra, US 20180121121 A1, in view of Bayat, US 20170337466 A1.
As to claim 1, Mehra discloses a system (see Fig 11) comprising:
a programmable logic block (see Mehra Fig 19 Refs 1302 and 1304) comprising programmable logic (see Mehra Fig 19 Ref 1304) and a configuration block (see Mehra Fig 19 Ref 1302) to store and provide configuration data to the programmable logic (see Mehra Para [0089]), the configuration block comprising a flash memory array to store the configuration data (see Mehra Para [0089]) and configuration data logic (see Mehra Para [0089]; Receiving configuration data requires logic.) for receiving signals from the flash memory array (see Mehra Para [0089]) and the flash memory array comprising an array of NAND memory cells (see Mehra Para [0060]).
Mehra does not appear to explicitly disclose split-gate flash memory cells; and generating enhanced signals by increasing or decreasing the voltage level of a '1' bit and providing the enhanced signals to the programmable logic.
Bayat discloses split-gate flash memory cells (see Bayat Figs 13 and 20); and generating enhanced signals by increasing or decreasing the voltage level of a '1' bit and providing the enhanced signals to the programmable logic (see Bayat Para [0048]; The voltage/threshold assigned to a ‘1’ bit is arbitrary.).
It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a system, as disclosed by Mehra, may implement a particular non-volatile memory, as disclosed by Bayat. The inventions are well known variants of devices which preform compute operations in memory, and the combination of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is Bayat’s attempt to improve power consumption for memory operations (see Bayat Para [0055]).
As to claim 2, Mehra and Bayat discloses the system of claim 1, wherein
the configuration block comprises configuration data logic to receive signals from the flash memory array based on the configuration data, modify the received signals into modified signals, and provide the modified signals to the programmable logic (see Mehra Para [0089]; Modifications of signals in required for the disclosed operations.).
As to claim 4, Mehra and Bayat discloses the system of claim 1, wherein
a respective bit of configuration data is stored in a plurality of adjacent memory cells (see Bayat Fig 20 Ref 10 and Para [0064]) in the flash memory array sharing a shared bit line (see Bayat Fig 20 Ref 14a).
As to claim 6, Mehra and Bayat discloses the system of claim 1, wherein
the configuration block comprises a column multiplexor (see Bayat Fig 13 Ref 36).
As to claim 7, Mehra and Bayat discloses the system of claim 1, where
the flash memory array comprises source lines (see Bayat Fig 20 Ref 14a), control gate lines (see Bayat Fig 20 Ref 22a), word lines (see Bayat Fig 20 Ref 28a1 and 28a2), and erase gate lines (see Bayat Fig 20 Ref 30a) arranged in a first direction (see annotated image of Bayat Fig 20 below Ref X; A portion of the erase line is in the first direction.) and bit lines arranged in a second direction (see annotated image of Bayat Fig 20 below Ref Y) perpendicular to the first direction (see annotated image of Bayat Fig 20 below Refs X and Y).
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As to claim 8, Mehra and Bayat discloses the system of claim 1, where
the flash memory array comprises source lines, control gate lines, word lines, erase gate lines, and bit lines (see Bayat Fig 20 Refs 14a, 22a, 28a1, 28a2, 30a, 16a1, and 16a2) arranged in a single direction (see annotated image of Bayat Fig 20 above Ref X; A portion of all the line is in the single direction.).
As to claim 9, Mehra and Bayat discloses the system of claim 1, where
the flash memory array comprises source lines, word lines, and erase gate lines (see Bayat Fig 20 Refs 14a, 28a1, 28a2, and 30a, and annotated image of Bayat Fig 20 above Ref X) arranged in a first direction and control gate lines and bit lines (see Bayat Fig 20 Refs 22a, 16a1, and 16a2, and see annotated image of Bayat Fig 20 above Ref Y) arranged in a second direction perpendicular to the first direction (see annotated image of Bayat Fig 20 above Refs X and Y).
As to claim 10, Mehra and Bayat discloses the system of claim 1, where
the flash memory array comprises source lines, control gate lines, and erase gate lines (see Bayat Fig 20 Refs 14a, 22a, and 30a, and annotated image of Bayat Fig 20 above Ref X) arranged in a first direction and word lines and bit lines (see Bayat Fig 20 Refs 28a1, 28a2, 16a1, and 16a2, and see annotated image of Bayat Fig 20 above Ref Y) arranged in a second direction perpendicular to the first direction (see annotated image of Bayat Fig 20 above Refs X and Y).
As to claim 11, Mehra and Bayat discloses the system of claim 1, comprising:
a second programmable logic block comprising second programmable logic and a second configuration block to store and provide second configuration data to the second programmable logic, the second configuration block comprising a second flash memory array to store the second configuration data (see Mehra Fig 19, Fig 11 Ref 222, 252, and Para [0049]).
As to claim 12, Mehra and Bayat discloses the system of claim 1, wherein
the split-gate flash memory cells are programmed using source side injection with hot electrons (see Bayat Paras [0040] and [0041]).
As to claim 13, Mehra and Bayat discloses the system of claim 1, wherein
the split-gate flash memory cells are programmed using a current source (see Bayat Paras [0040] and [0041]).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mehra, US 20180121121 A1 and Bayat, US 20170337466 A1, in view of Khare, US 20240291491 A1.
As to claim 3, Mehra and Bayat discloses the system of claim 2, wherein
the configuration data logic comprises circuitry for transferring data.
Mehra and Bayat do not appear to explicitly disclose a level shifter to generate modified signals with a different voltage level for a “1”.
Khare discloses a level shifter to generate modified signals with a different voltage level for a “1”.
It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a system, as disclosed by Mehra and Bayat, may implement a particular domain interfacing circuit, as disclosed by Khare. The inventions are well known variants of devices which transfer data between different circuit locations, and the combination of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is Khare’s attempt to prevent erroneous level shifts (see Khare Para [0004]).
Response to Arguments
Applicant's arguments filed 02/27/2026 have been fully considered but they are not persuasive.
The amended language does not appear to overcome the rejection of record.
Arguments regards the drawing objections and 112 enablement rejections is not persuasive. Claim 1 recites a system, part of which is depicted as schematics and logic blocks in figure 5. Figures 7A, 7B, 8A, and 8B are wiring schematics of the system, and not physical representation of the system’s circuitry as fabricated. Schematics are abstract representation of circuits to aid in reading the circuit, and are not physical layouts of fabricated circuits, thus the limitations relating to the physical structure of the system are not properly disclosed in the original specification, and not enabled to one of ordinary skill in the art.
Allowable Subject Matter
Claim(s) 5 is allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art does not appear to disclose (as recited in claim 5):
the plurality of adjacent memory cells comprises a first memory cell and a second memory cell and the bit of configuration data is a “1” when the first memory cell is erased and the second memory cell is programmed and the bit of configuration data is a “0” when the first memory cell is programmed and the second memory cell is erased.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEROME LARRY LEBOEUF whose telephone number is (571)272-7612. The examiner can normally be reached M-Th: 8:00AM - 6:00PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, RICHARD ELMS can be reached at (517)272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JEROME LEBOEUF/Primary Examiner, Art Unit 2824 - 04/24/2026
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