DETAILED ACTION
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment
Acknowledgment is made of applicant's Amendment, filed 07-22-2026. The changes and remarks disclosed therein have been considered.
Claim(s) 1, 2, and 11 has/have been amended, and claim(s) 1-21 remain(s) pending in the application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 4, and 6-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mehra, US 20180121121 A1, in view of Bayat, US 20170337466 A1.
As to claim 1, Mehra discloses a system (see Fig 11) comprising:
a programmable logic block (see Mehra Fig 19 Refs 1302 and 1304) comprising programmable logic (see Mehra Fig 19 Ref 1304) and a configuration block (see Mehra Fig 19 Ref 1302) to store and provide configuration data to the programmable logic (see Mehra Para [0089]), the configuration block comprising a flash memory array to store the configuration data (see Mehra Para [0089]) and configuration data logic (see Mehra Para [0089]; Receiving configuration data requires logic.) for receiving signals from the flash memory array (see Mehra Para [0089]) and generating signals to configure the programable logic (see Mehra Para [0089]; FPGAs are configured by programming logic.), and the flash memory array comprising an array of NAND memory cells (see Mehra Para [0060]).
Mehra does not appear to explicitly disclose split-gate flash memory cells; and generating enhanced signals by increasing or decreasing a voltage level of a '1' bit and providing the enhanced signals to the programmable logic.
Bayat discloses split-gate flash memory cells (see Bayat Figs 13 and 20); and generating enhanced signals by increasing or decreasing a voltage level of a '1' bit and providing the enhanced signals to the programmable logic (see Bayat Para [0048]; The voltage/threshold assigned to a ‘1’ bit is arbitrary.).
It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a system, as disclosed by Mehra, may implement a particular non-volatile memory, as disclosed by Bayat. The inventions are well known variants of devices which preform compute operations in memory, and the combination of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is Bayat’s attempt to improve power consumption for memory operations (see Bayat Para [0055]).
As to claim 2, Mehra and Bayat discloses the system of claim 1, wherein
the configuration block comprises configuration data logic to receive signals from the flash memory array based on the configuration data, modify the received signals into modified signals, and provide the modified signals to the programmable logic (see Mehra Para [0089]; Modifications of signals in required for the disclosed operations.) to configure the programable logic (see Mehra Para [0089]).
As to claim 4, Mehra and Bayat discloses the system of claim 1, wherein
a respective bit of configuration data is stored in a plurality of adjacent memory cells (see Bayat Fig 20 Ref 10 and Para [0064]) in the flash memory array sharing a shared bit line (see Bayat Fig 20 Ref 14a).
As to claim 6, Mehra and Bayat discloses the system of claim 1, wherein
the configuration block comprises a column multiplexor (see Bayat Fig 13 Ref 36).
As to claim 7, Mehra and Bayat discloses the system of claim 1, where
the flash memory array comprises source lines (see Bayat Fig 20 Ref 14a), control gate lines (see Bayat Fig 20 Ref 22a), word lines (see Bayat Fig 20 Ref 28a1 and 28a2), and erase gate lines (see Bayat Fig 20 Ref 30a) arranged in a first direction (see annotated image of Bayat Fig 20 below Ref X; A portion of the erase line is in the first direction.) and bit lines arranged in a second direction (see annotated image of Bayat Fig 20 below Ref Y) perpendicular to the first direction (see annotated image of Bayat Fig 20 below Refs X and Y).
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As to claim 8, Mehra and Bayat discloses the system of claim 1, where
the flash memory array comprises source lines, control gate lines, word lines, erase gate lines, and bit lines (see Bayat Fig 20 Refs 14a, 22a, 28a1, 28a2, 30a, 16a1, and 16a2) arranged in a single direction (see annotated image of Bayat Fig 20 above Ref X; A portion of all the line is in the single direction.).
As to claim 9, Mehra and Bayat discloses the system of claim 1, where
the flash memory array comprises source lines, word lines, and erase gate lines (see Bayat Fig 20 Refs 14a, 28a1, 28a2, and 30a, and annotated image of Bayat Fig 20 above Ref X) arranged in a first direction and control gate lines and bit lines (see Bayat Fig 20 Refs 22a, 16a1, and 16a2, and see annotated image of Bayat Fig 20 above Ref Y) arranged in a second direction perpendicular to the first direction (see annotated image of Bayat Fig 20 above Refs X and Y).
As to claim 10, Mehra and Bayat discloses the system of claim 1, where
the flash memory array comprises source lines, control gate lines, and erase gate lines (see Bayat Fig 20 Refs 14a, 22a, and 30a, and annotated image of Bayat Fig 20 above Ref X) arranged in a first direction and word lines and bit lines (see Bayat Fig 20 Refs 28a1, 28a2, 16a1, and 16a2, and see annotated image of Bayat Fig 20 above Ref Y) arranged in a second direction perpendicular to the first direction (see annotated image of Bayat Fig 20 above Refs X and Y).
As to claim 11, Mehra and Bayat discloses the system of claim 1, comprising:
a second programmable logic block comprising second programmable logic and a second configuration block to store and provide second configuration data to the second programmable logic to configure the programable logic (see Mehra Para [0089]), the second configuration block comprising a second flash memory array to store the second configuration data (see Mehra Fig 19, Fig 11 Ref 222, 252, and Para [0049]).
As to claim 12, Mehra and Bayat discloses the system of claim 1, wherein
the split-gate flash memory cells are programmed using source side injection with hot electrons (see Bayat Paras [0040] and [0041]).
As to claim 13, Mehra and Bayat discloses the system of claim 1, wherein
the split-gate flash memory cells are programmed using a current source (see Bayat Paras [0040] and [0041]).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mehra, US 20180121121 A1 and Bayat, US 20170337466 A1, in view of Khare, US 20240291491 A1.
As to claim 3, Mehra and Bayat discloses the system of claim 2, wherein
the configuration data logic comprises circuitry for transferring data.
Mehra and Bayat do not appear to explicitly disclose a level shifter to generate modified signals with a different voltage level for a “1”.
Khare discloses a level shifter to generate modified signals with a different voltage level for a “1”.
It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a system, as disclosed by Mehra and Bayat, may implement a particular domain interfacing circuit, as disclosed by Khare. The inventions are well known variants of devices which transfer data between different circuit locations, and the combination of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is Khare’s attempt to prevent erroneous level shifts (see Khare Para [0004]).
Response to Arguments
Applicant's arguments filed 07/22/2026 have been fully considered but they are not persuasive.
The amend subject matter does not appear to overcome the rejection of record. Mehra explicitly discloses in paragraph [0089]) “That is, configuration data stored in memory array 1302 is used to configure the FPGA's.” The circuitry and signals used to transmit the data stored in memory array is inherent to the configuration of FPGA.
With regards to the drawing objections of the office action filed 04/28/2026, the applicant has amended their schematics drawings with cartesian coordinates. These amended draws do not alleviate the deficiency in the drawings, that is Figures 7A, 7B, 8A, and 8B are wiring schematics of the system, and not physical representation of the system’s circuitry as fabricated. Examiner has taken these amended drawings as attempt to clarify that the limitations “a first direction” and “a second direction”, which are described in the written specification as an arbitrary cartesian coordinate system with the “first direction” having a perpendicular relationship to the “second direction”. With regards to the limited argued scope, examiner has dropped the drawing objections and has given a minimum of patentable weight to the “a first direction” and “a second direction” limitations.
Allowable Subject Matter
Claim(s) 5 is allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art does not appear to disclose (as recited in claim 5):
the plurality of adjacent memory cells comprises a first memory cell and a second memory cell and the bit of configuration data is a “1” when the first memory cell is erased and the second memory cell is programmed and the bit of configuration data is a “0” when the first memory cell is programmed and the second memory cell is erased.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEROME LARRY LEBOEUF whose telephone number is (571)272-7612. The examiner can normally be reached M-Th: 8:00AM - 6:00PM EST.
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/JEROME LEBOEUF/Primary Examiner, Art Unit 2824 - 08/07/2026
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