DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/16/2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 15 and 21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention
Claim 15 recites the limitation “a first encapsulant" (in line 2). However, claim 14 (upon which claim 15 depends) recites “a first encapsulant" (in line 9), and it is unclear whether the second recited “a first encapsulant" of claim 15 is intended to relate back to “a first encapsulant" of claim 14 or to set forth an additional first encapsulant.
Claim 21 recites the limitation “a first encapsulant" (in line 2). However, claim 20 (upon which claim 21 depends) recites “a first encapsulant" (in line 9), and it is unclear whether the second recited “a first encapsulant" of claim 21 is intended to relate back to “a first encapsulant" of claim 20 or to set forth an additional first encapsulant.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0197829 to Stiebler in view of Guzek (US 2021/0134731) and Hsu et al. (US Patent No. 9,627,346, hereinafter Hsu).
With respect to claim 1, Stiebler discloses a semiconductor device (e.g., three-dimensional (3D) integrated circuit (IC) (3DIC) assembly having an antenna substrate and active interposer) (Stiebler, Fig. 2, ¶0005-¶0007, ¶0026-¶0042), comprising:
a semiconductor assembly (e.g., active interposer 34 on the carrier substrate 38 of the 3DIC assembly 32) (Stiebler, Fig. 2, ¶0026-¶0032) including,
an interposer substrate (e.g., 34/44) (Stiebler, Fig. 2, ¶0026),
a conductive via (66) (Stiebler, Fig. 2, ¶0032) formed through the interposer substrate (34/44),
a semiconductor die (e.g., IC chip 68) (Stiebler, Fig. 2, ¶0034);
an antenna substrate (e.g., 36) (Stiebler, Fig. 2, ¶0026-¶0027) formed separate from the semiconductor assembly (34/38) and mounted to the semiconductor assembly (34/38); and
a bonding material (e.g., metallization 54 of the antenna substrate 36 is bonded to the patterned metallization 62 of the active interposer 34 by a solder patch) (Stiebler, Fig. 2, ¶0032-¶0033) disposed between the antenna substrate (38) and semiconductor assembly (56/77), wherein,
a first portion of the bonding material (e.g., metallization 54 with a solder patch) (Stiebler, Fig. 2, ¶0033) is disposed at an edge of the antenna substrate (36),
a second portion (e.g., metallization 54 with a solder patch) (Stiebler, Fig. 2, ¶0033) of the bonding material is disposed directly on a back surface of the semiconductor die (IC chip 68), and
a third portion (e.g., metallization 54 with a solder patch) (Stiebler, Fig. 2, ¶0033) of the bonding material is disposed directly on a back surface of the interposer substrate (34/44).
Regarding limitation “an antenna substrate formed separate from the semiconductor assembly and mounted to the semiconductor assembly”, it is noted that the above language is directed towards the process of making a semiconductor device comprising an antenna substrate and a semiconductor assembly. It is well settled that "product-by-process" limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985), which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language "an antenna substrate formed separate from the semiconductor assembly and mounted to the semiconductor assembly" only requires a structure, a semiconductor device comprising an antenna substrate and a semiconductor assembly, which does not distinguish the invention from Stiebler, who teaches the structure as claimed.
Further, Stiebler does not specifically disclose (1) a semiconductor die disposed in an opening of the interposer substrate, and a first encapsulant deposited into the opening between the interposer substrate and semiconductor die; a second portion of the bonding material is disposed directly on a back surface of the first encapsulant; (2) a first portion of the bonding material extends onto a side surface of the antenna substrate.
Regarding (1), Guzek teaches forming an integrated circuit package having an interposer with an embedded die (Guzek, Fig. 11B, ¶0018-¶0020, ¶0034-¶0044), wherein a semiconductor die (402) (Guzek, Figs. 4, 11B, ¶0035) is disposed in an opening of the interposer substrate (412), and a first encapsulant (mold compound 510) (Guzek, Figs. 5, 11B, ¶0036) deposited into the opening between the interposer substrate (412) and semiconductor die (402). Further, the package substrate (1160/1170) is bonded to the back side of the assembly (900) including the interposer with an embedded die (Guzek, Fig. 11B, ¶0044) with a bonding material (1164/1174), and forming the underfill material (1162) having a second portion disposed between the package substrate (1160) and the first encapsulant (mold compound 510) (Guzek, Figs. 5, 11B, ¶0044) and directly on a back surface of the first encapsulant (510), to provide improved stacked integrated circuit package including an interposer material selected to match the package substrate to minimize the coefficient of thermal expansion mismatch to the die material, and thus to minimize warpage in stacking 3D IC assembly (Guzek, ¶0002, ¶0018-¶0020, ¶0044).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Stiebler by forming an interposer with an embedded die surrounded by the first encapsulant as taught by Guzek and forming a portion of the metallization with a solder patch of Stiebler on the interposer including an embedded die surrounded by the first encapsulant as a second bonding portion to have the semiconductor device, compriing: a semiconductor die disposed in an opening of the interposer substrate, and a first encapsulant deposited into the opening between the interposer substrate and semiconductor die; a second portion of the bonding material is disposed directly on a back surface of the first encapsulant, in order to provide improved stacked integrated circuit package including an interposer material selected to match the package substrate to minimize the coefficient of thermal expansion mismatch to the die material, and thus to minimize warpage in stacking 3D IC assembly (Guzek, ¶0002, ¶0018-¶0020, ¶0044).
Regarding (2), Hsu teaches forming a semiconductor structure (Hsu, Fig. 1, 2A-2B, Col. 1, lines 19-28; lines 55-67; Col. 2, lines 1-17; Col. 3, lines 1-43; Col. 4, lines 5-19) comprising a package (10) having a larger package size attached to the package substrate (20) by using a plurality of electrical connectors (e.g., solder connectors 18) and bonding material (22) disposed at the lateral edges of the package (10) and surrounding the plurality of electrical connectors (18) along the periphery of the package (10), to provide additional bonding and support to the ball/bump connectors, and thus to enhance the reliability of the package (Hsu, Col. 1, lines 23-28; Col. 4, lines 16-19).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Stiebler by forming a bonding material at the lateral edges of the package as a first bonding portion as taught by Hsu, wherein the bonding material surrounds the plurality of electrical connectors between the package and the semiconductor assembly, and wherein the package includes an antenna substrate to have the semiconductor device, wherein a first portion of the bonding material extends onto a side surface of the antenna substrate, in order to provide additional bonding and support to the ball/bump connectors, and thus to enhance the reliability of the package (Hsu, Col. 1, lines 23-28; Col. 4, lines 16-19).
With respect to claim 14, Stiebler discloses a method of making a semiconductor device (e.g., forming three-dimensional (3D) integrated circuit (IC) (3DIC) assembly having an antenna substrate and active interposer) (Stiebler, Fig. 2, ¶0005-¶0007, ¶0026-¶0042), comprising:
providing a semiconductor assembly (e.g., active interposer 34 on the carrier substrate 38 of the 3DIC assembly 32) (Stiebler, Fig. 2, ¶0026-¶0032) including,
an interposer substrate (e.g., 34/44) (Stiebler, Fig. 2, ¶0026),
a conductive via (66) (Stiebler, Fig. 2, ¶0032) formed through the interposer substrate (34/44),
a semiconductor die (e.g., IC chip 68) (Stiebler, Fig. 2, ¶0034);
forming an antenna substrate (e.g., 36) (Stiebler, Fig. 2, ¶0026-¶0027) separate from the semiconductor assembly (34/38);
mounting the antenna substrate (e.g., 36) (Stiebler, Fig. 2, ¶0033) to the semiconductor assembly (34/38); and
disposing a bonding material (e.g., metallization 54 of the antenna substrate 36 is bonded to the patterned metallization 62 of the active interposer 34 by a solder patch) (Stiebler, Fig. 2, ¶0032-¶0033) between the antenna substrate (38) and semiconductor assembly (56/77), wherein,
a first portion of the bonding material (e.g., metallization 54 with a solder patch) (Stiebler, Fig. 2, ¶0033) is disposed at an edge of the antenna substrate (36),
a second portion (e.g., metallization 54 with a solder patch) (Stiebler, Fig. 2, ¶0033) of the bonding material is disposed directly on a back surface of the semiconductor die (IC chip 68), and
a third portion (e.g., metallization 54 with a solder patch) (Stiebler, Fig. 2, ¶0033) of the bonding material is disposed directly on a back surface of the interposer substrate (34/44).
Further, Stiebler does not specifically disclose (1) a semiconductor die disposed in an opening of the interposer substrate, and a first encapsulant deposited into the opening between the interposer substrate and semiconductor die; a second portion of the bonding material is disposed directly on a back surface of the first encapsulant; (2) a first portion of the bonding material extends onto a side surface of the antenna substrate.
Regarding (1), Guzek teaches forming an integrated circuit package having an interposer with an embedded die (Guzek, Fig. 11B, ¶0018-¶0020, ¶0034-¶0044), wherein a semiconductor die (402) (Guzek, Figs. 4, 11B, ¶0035) is disposed in an opening of the interposer substrate (412), and a first encapsulant (mold compound 510) (Guzek, Figs. 5, 11B, ¶0036) deposited into the opening between the interposer substrate (412) and semiconductor die (402). Further, the package substrate (1160/1170) is bonded to the back side of the assembly (900) including the interposer with an embedded die (Guzek, Fig. 11B, ¶0044) with a bonding material (1164/1174), and forming the underfill material (1162) having a second portion disposed between the package substrate (1160) and the first encapsulant (mold compound 510) (Guzek, Figs. 5, 11B, ¶0044) and directly on a back surface of the first encapsulant (510), to provide improved stacked integrated circuit package including an interposer material selected to match the package substrate to minimize the coefficient of thermal expansion mismatch to the die material, and thus to minimize warpage in stacking 3D IC assembly (Guzek, ¶0002, ¶0018-¶0020, ¶0044).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Stiebler by forming an interposer with an embedded die surrounded by the first encapsulant as taught by Guzek and forming a portion of the metallization with a solder patch of Stiebler on the interposer including an embedded die surrounded by the first encapsulant as a second bonding portion to have the method, comprising: a semiconductor die disposed in an opening of the interposer substrate, and a first encapsulant deposited into the opening between the interposer substrate and semiconductor die; a second portion of the bonding material is disposed directly on a back surface of the first encapsulant, in order to provide improved stacked integrated circuit package including an interposer material selected to match the package substrate to minimize the coefficient of thermal expansion mismatch to the die material, and thus to minimize warpage in stacking 3D IC assembly (Guzek, ¶0002, ¶0018-¶0020, ¶0044).
Regarding (2), Hsu teaches forming a semiconductor structure (Hsu, Fig. 1, 2A-2B, Col. 1, lines 19-28; lines 55-67; Col. 2, lines 1-17; Col. 3, lines 1-43; Col. 4, lines 5-19) comprising a package (10) having a larger package size attached to the package substrate (20) by using a plurality of electrical connectors (e.g., solder connectors 18) and bonding material (22) disposed at the lateral edges of the package (10) and surrounding the plurality of electrical connectors (18) along the periphery of the package (10), to provide additional bonding and support to the ball/bump connectors, and thus to enhance the reliability of the package (Hsu, Col. 1, lines 23-28; Col. 4, lines 16-19).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Stiebler by forming a bonding material at the lateral edges of the package as a first bonding portion as taught by Hsu, wherein the bonding material surrounds the plurality of electrical connectors between the package and the semiconductor assembly, and wherein the package includes an antenna substrate to have the method, wherein a first portion of the bonding material extends onto a side surface of the antenna substrate, in order to provide additional bonding and support to the ball/bump connectors, and thus to enhance the reliability of the package (Hsu, Col. 1, lines 23-28; Col. 4, lines 16-19).
Claims 2 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0197829 to Stiebler in view of Guzek (US 2021/0134731) and Hsu (US Patent No. 9,627,346) as applied to claim 1 (claim 14), and further in view of Lee et al. (US 2020/0044306, hereinafter Lee) and Kim (US 2021/0274652).
Regarding claim 2, Stiebler in view of Guzek and Hsu discloses the semiconductor device of claim 1. Further, Stiebler does not specifically disclose the semiconductor device, further including a second encapsulant deposited over the antenna substrate, wherein the second encapsulant includes a high dielectric constant of greater than 4.0 and a low dielectric dissipation factor of less than 0.01, and wherein the second encapsulant includes an encapsulant bump over an antenna of the antenna substrate.
However, Lee teaches forming an encapsulant (220) (Lee, Fig. 1K, ¶0002, ¶0027, ¶0043) over the antenna pattern (APN1), wherein the encapsulant (220) is formed as a plurality of blocks on the core dielectric layer (110B) to cover the antenna pattern (APN1) and expose portions of the first surface of the core dielectric layer (110B), to provide a degree of protection for the underlying structure and prevent oxidation of the antenna patterns, and to obtain a high performance package with integrated antenna.
Further, Kim teaches forming a polymeric composition (Kim, Fig. 11, ¶0003, ¶0022-¶0025) for the antenna substrate having a high dielectric constant of greater than 4.0 (e.g., 5 or more; 6 or more; or between about 8 and 30) and a low dielectric dissipation factor of between 0.001 and 0.03, to facilitate ability to form a thin substrate and to allow multiple antenna elements to be employed with minimal level of electric interference, and to provide a polymeric material having excellent strength properties.
The claimed range of the dielectric dissipation factor overlaps the rnage of Kim. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (M.P.E.P. §2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Stiebler/Guzek/Hsu by forming a second encapsulant having a plurality of blocks as encapsulant bumps covering the antenna patterns as taught by Lee, wherein the second encapsulant includes polymeric material as taught by Kim to have the semiconductor device, further including a second encapsulant deposited over the antenna substrate, wherein the second encapsulant includes a high dielectric constant of greater than 4.0 and a low dielectric dissipation factor of less than 0.01, and wherein the second encapsulant includes an encapsulant bump over an antenna of the antenna substrate, in order to provide a degree of protection for the underlying structure and prevent oxidation of the antenna patterns, and to obtain a high performance package with integrated antenna; and to facilitate forming a thin antenna substrate that allows multiple antenna elements to be employed with minimal level of electric interference, and to provide a polymeric material having excellent strength properties (Lee, ¶0002, ¶0027, ¶0043; Kim, ¶0003, ¶0022, ¶0024).
Regarding claim 15, Stiebler in view of Guzek and Hsu discloses the method of claim 14. Further, Stiebler does not specifically disclose the method, further including depositing a first encapsulant over the antenna substrate, wherein the first encapsulant includes a high dielectric constant of greater than 4.0 and a low dielectric dissipation factor of less than 0.01, and wherein the first encapsulant includes an encapsulant bump over an antenna of the antenna substrate.
However, Lee teaches forming an encapsulant (220) (Lee, Fig. 1K, ¶0002, ¶0027, ¶0043) over the antenna pattern (APN1), wherein the encapsulant (220) is formed as a plurality of blocks on the core dielectric layer (110B) to cover the antenna pattern (APN1) and expose portions of the first surface of the core dielectric layer (110B), to provide a degree of protection for the underlying structure and prevent oxidation of the antenna patterns, and to obtain a high performance package with integrated antenna.
Further, Kim teaches forming a polymeric composition (Kim, Fig. 11, ¶0003, ¶0022-¶0025) for the antenna substrate having a high dielectric constant of greater than 4.0 (e.g., 5 or more; 6 or more; or between about 8 and 30) and a low dielectric dissipation factor of between 0.001 and 0.03, to facilitate ability to form a thin substrate and to allow multiple antenna elements to be employed with minimal level of electric interference, and to provide a polymeric material having excellent strength properties.
The claimed range of the dielectric dissipation factor overlaps the rnage of Kim. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (M.P.E.P. §2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Stiebler/Guzek/Hsu by forming an encapsulant having a plurality of blocks as encapsulant bumps covering the antenna patterns as taught by Lee, wherein the encapsulant includes polymeric material as taught by Kim to have the method, further including depositing a first encapsulant over the antenna substrate, wherein the first encapsulant includes a high dielectric constant of greater than 4.0 and a low dielectric dissipation factor of less than 0.01, and wherein the first encapsulant includes an encapsulant bump over an antenna of the antenna substrate, in order to provide a degree of protection for the underlying structure and prevent oxidation of the antenna patterns, and to obtain a high performance package with integrated antenna; and to facilitate forming a thin antenna substrate that allows multiple antenna elements to be employed with minimal level of electric interference, and to provide a polymeric material having excellent strength properties (Lee, ¶0002, ¶0027, ¶0043; Kim, ¶0003, ¶0022, ¶0024).
Claims 4-5 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0197829 to Stiebler in view of Guzek (US 2021/0134731) and Hsu (US Patent No. 9,627,346) as applied to claim 1 (claim 14), and further in view of Yeon (US 2021/0091017).
Regarding claims 4-5, Stiebler in view of Guzek and Hsu discloses the semiconductor device of claim 1. Further, Stiebler does not specifically disclose the semiconductor device, wherein the antenna substrate includes a first antenna substrate and a second antenna substrate disposed over the semiconductor assembly (as claimed in claim 4); wherein the first antenna substrate is offset with respect to the second antenna substrate (as claimed in claim 5).
However, Yeon teaches forming antenna in package (AiP) device (300) (Yeon, Fig. 3, ¶0030-¶0031, ¶0038-¶0044, ¶0112) comprising a first antenna device (e.g., 380, including substrate 502/506) (Yeon, Figs. 3, 5, ¶0040-¶0043, ¶0047-¶0050) and a second antenna device (e.g., 370, including substrate 502/506) disposed over the semiconductor assembly (202) and formed separate from fabrication of the semiconductor assembly (202) including a semiconductor device (203/205), wherein the first antenna device (380) has different size and is offset with respect to the second antenna device (370), to provide antenna devices having different capabilities and functionalities to provide an efficient AiP package.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Stiebler/Guzek/Hsu by forming a plurality of discrete antenna devices on the semiconductor assembly as taught by Yeon to have the semiconductor device, wherein the antenna substrate includes a first antenna substrate and a second antenna substrate disposed over the semiconductor assembly (as claimed in claim 4); wherein the first antenna substrate is offset with respect to the second antenna substrate (as claimed in claim 5), in order to provide antenna devices having different capabilities and functionalities to provide an efficient AiP package (Yeon, ¶0030, ¶0038, ¶0040-¶0044).
Regarding claims 17-18, Stiebler in view of Guzek and Hsu discloses the method of claim 14. Further, Chuang does not specifically disclose the method, wherein forming the antenna substrate includes: forming a first antenna substrate; forming a second antenna substrate; and disposing the first antenna substrate and the second antenna substrate over the semiconductor assembly (as claimed in claim 17); wherein the first antenna substrate is offset with respect to the second antenna substrate (as claimed in claim 18).
However, Yeon teaches forming antenna in package (AiP) device (300) (Yeon, Fig. 3, ¶0030-¶0031, ¶0038-¶0044, ¶0112) comprising a first antenna device (e.g., 380, including substrate 502/506) (Yeon, Figs. 3, 5, ¶0040-¶0043, ¶0047-¶0050) and a second antenna device (e.g., 370, including substrate 502/506) disposed over the semiconductor assembly (202) and formed separate from fabrication of the semiconductor assembly (202) including a semiconductor device (203/205), wherein the first antenna device (380) has different size and is offset with respect to the second antenna device (370), to provide antenna devices having different capabilities and functionalities to provide an efficient AiP package.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Stiebler/Guzek/Hsu by forming a plurality of discrete antenna devices disposed on the semiconductor assembly as taught by Yeon to have the method, wherein forming the antenna substrate includes: forming a first antenna substrate; forming a second antenna substrate; and disposing the first antenna substrate and the second antenna substrate over the semiconductor assembly (as claimed in claim 17); wherein the first antenna substrate is offset with respect to the second antenna substrate (as claimed in claim 18), in order to provide antenna devices having different capabilities and functionalities to provide an efficient AiP package (Yeon, ¶0030, ¶0038, ¶0040-¶0044).
Claims 7 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0197829 to Stiebler in view of Guzek (US 2021/0134731).
With respect to claim 7, Stiebler discloses a semiconductor device (e.g., three-dimensional (3D) integrated circuit (IC) (3DIC) assembly having an antenna substrate and active interposer) (Stiebler, Fig. 2, ¶0005-¶0007, ¶0026-¶0042), comprising:
a semiconductor assembly (e.g., active interposer 34 on the carrier substrate 38 of the 3DIC assembly 32) (Stiebler, Fig. 2, ¶0026-¶0032) including,
an interposer substrate (e.g., 34/44) (Stiebler, Fig. 2, ¶0026),
a conductive via (66) (Stiebler, Fig. 2, ¶0032) formed through the interposer substrate (34/44),
a semiconductor die (e.g., IC chip 68) (Stiebler, Fig. 2, ¶0034); and
an antenna substrate (e.g., 36) (Stiebler, Fig. 2, ¶0026-¶0027) formed separate from the semiconductor assembly (34/38) and mounted to the semiconductor assembly (34/38) with a bonding material (e.g., metallization 54 of the antenna substrate 36 is bonded to the patterned metallization 62 of the active interposer 34 by a solder patch) (Stiebler, Fig. 2, ¶0032-¶0033), wherein a first portion of the bonding material (e.g., metallization 54 with a solder patch) (Stiebler, Fig. 2, ¶0033) is disposed directly on a back surface of the semiconductor die (IC chip 68).
Regarding limitation “an antenna substrate formed separate from the semiconductor assembly and mounted to the semiconductor assembly”, it is noted that the above language is directed towards the process of making a semiconductor device comprising an antenna substrate and a semiconductor assembly. It is well settled that "product-by-process" limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985), which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language "an antenna substrate formed separate from the semiconductor assembly and mounted to the semiconductor assembly" only requires a structure, a semiconductor device comprising an antenna substrate and a semiconductor assembly, which does not distinguish the invention from Stiebler, who teaches the structure as claimed.
Further, Stiebler does not specifically disclose a semiconductor die disposed in an opening of the interposer substrate, and a first encapsulant deposited into the opening between the interposer substrate and semiconductor die.
However, Guzek teaches forming an integrated circuit package having an interposer with an embedded die (Guzek, Fig. 11B, ¶0018-¶0020, ¶0034-¶0044), wherein a semiconductor die (402) (Guzek, Figs. 4, 11B, ¶0035) is disposed in an opening of the interposer substrate (412), and a first encapsulant (mold compound 510) (Guzek, Figs. 5, 11B, ¶0036) deposited into the opening between the interposer substrate (412) and semiconductor die (402). Further, the package substrate (1160/1170) is bonded to the back side of the assembly (900) including the interposer with an embedded die (Guzek, Fig. 11B, ¶0044) with a bonding material (1164/1174), and forming the underfill material (1162) having a second portion disposed between the package substrate (1160) and the first encapsulant (mold compound 510) (Guzek, Figs. 5, 11B, ¶0044) and directly on a back surface of the first encapsulant (510), to provide improved stacked integrated circuit package including an interposer material selected to match the package substrate to minimize the coefficient of thermal expansion mismatch to the die material, and thus to minimize warpage in stacking 3D IC assembly (Guzek, ¶0002, ¶0018-¶0020, ¶0044).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Stiebler by forming an interposer with an embedded die surrounded by the first encapsulant as taught by Guzek to have the semiconductor device, comprising: a semiconductor die disposed in an opening of the interposer substrate, and a first encapsulant deposited into the opening between the interposer substrate and semiconductor die, in order to provide improved stacked integrated circuit package including an interposer material selected to match the package substrate to minimize the coefficient of thermal expansion mismatch to the die material, and thus to minimize warpage in stacking 3D IC assembly (Guzek, ¶0002, ¶0018-¶0020, ¶0044).
With respect to claim 20, Stiebler discloses a method of making a semiconductor device (e.g., forming a three-dimensional (3D) integrated circuit (IC) (3DIC) assembly having an antenna substrate and active interposer) (Stiebler, Fig. 2, ¶0005-¶0007, ¶0026-¶0042), comprising:
providing a semiconductor assembly (e.g., active interposer 34 on the carrier substrate 38 of the 3DIC assembly 32) (Stiebler, Fig. 2, ¶0026-¶0032) including,
an interposer substrate (e.g., 34/44) (Stiebler, Fig. 2, ¶0026),
a conductive via (66) (Stiebler, Fig. 2, ¶0032) formed through the interposer substrate (34/44),
a semiconductor die (e.g., IC chip 68) (Stiebler, Fig. 2, ¶0034); and
forming an antenna substrate (e.g., 36) (Stiebler, Fig. 2, ¶0026-¶0027) separate from the semiconductor assembly (34/38) and mounted to the semiconductor assembly (34/38) with a bonding material (e.g., metallization 54 of the antenna substrate 36 is bonded to the patterned metallization 62 of the active interposer 34 by a solder patch) (Stiebler, Fig. 2, ¶0032-¶0033), wherein a first portion of the bonding material (e.g., metallization 54 with a solder patch) (Stiebler, Fig. 2, ¶0033) is disposed directly on a back surface of the semiconductor die (IC chip 68).
Further, Stiebler does not specifically disclose a semiconductor die disposed in an opening of the interposer substrate, and a first encapsulant deposited into the opening between the interposer substrate and semiconductor die.
However, Guzek teaches forming an integrated circuit package having an interposer with an embedded die (Guzek, Fig. 11B, ¶0018-¶0020, ¶0034-¶0044), wherein a semiconductor die (402) (Guzek, Figs. 4, 11B, ¶0035) is disposed in an opening of the interposer substrate (412), and a first encapsulant (mold compound 510) (Guzek, Figs. 5, 11B, ¶0036) deposited into the opening between the interposer substrate (412) and semiconductor die (402). Further, the package substrate (1160/1170) is bonded to the back side of the assembly (900) including the interposer with an embedded die (Guzek, Fig. 11B, ¶0044) with a bonding material (1164/1174), and forming the underfill material (1162) having a second portion disposed between the package substrate (1160) and the first encapsulant (mold compound 510) (Guzek, Figs. 5, 11B, ¶0044) and directly on a back surface of the first encapsulant (510), to provide improved stacked integrated circuit package including an interposer material selected to match the package substrate to minimize the coefficient of thermal expansion mismatch to the die material, and thus to minimize warpage in stacking 3D IC assembly (Guzek, ¶0002, ¶0018-¶0020, ¶0044).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Stiebler by forming an interposer with an embedded die surrounded by the first encapsulant as taught by Guzek to have the method, comprising: a semiconductor die disposed in an opening of the interposer substrate, and a first encapsulant deposited into the opening between the interposer substrate and semiconductor die, in order to provide improved stacked integrated circuit package including an interposer material selected to match the package substrate to minimize the coefficient of thermal expansion mismatch to the die material, and thus to minimize warpage in stacking 3D IC assembly (Guzek, ¶0002, ¶0018-¶0020, ¶0044).
Claims 8 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0197829 to Stiebler in view of Guzek (US 2021/0134731) as applied to claim 7 (claim 20), and further in view of Lee (US 2020/0044306).
Regarding claim 8, Stiebler in view of Guzek discloses the semiconductor device of claim 7. Further, Stiebler does not specifically disclose the semiconductor device, further including a second encapsulant deposited over the antenna substrate.
However, Lee teaches forming an encapsulant (220) (Lee, Fig. 1K, ¶0002, ¶0027, ¶0043) over the antenna pattern (APN1), wherein the encapsulant (220) is formed as a plurality of blocks on the core dielectric layer (110B) to cover the antenna pattern (APN1) and expose portions of the first surface of the core dielectric layer (110B), to provide a degree of protection for the underlying structure and prevent oxidation of the antenna patterns, and to obtain a high performance package with integrated antenna.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Stiebler/Guzek by forming a second encapsulant having a plurality of blocks as encapsulant bumps covering the antenna patterns as taught by Lee to have the semiconductor device, further including a second encapsulant deposited over the antenna substrate, in order to provide a degree of protection for the underlying structure and prevent oxidation of the antenna patterns, and to obtain a high performance package with integrated antenna (Lee, ¶0002, ¶0027, ¶0043).
Regarding claim 21, Stiebler in view of Guzek discloses the method of claim 20. Further, Stiebler does not specifically disclose the semiconductor device, further including depositing a first encapsulant over the antenna substrate.
However, Lee teaches forming an encapsulant (220) (Lee, Fig. 1K, ¶0002, ¶0027, ¶0043) over the antenna pattern (APN1), wherein the encapsulant (220) is formed as a plurality of blocks on the core dielectric layer (110B) to cover the antenna pattern (APN1) and expose portions of the first surface of the core dielectric layer (110B), to provide a degree of protection for the underlying structure and prevent oxidation of the antenna patterns, and to obtain a high performance package with integrated antenna.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Stiebler/Guzek by forming a first encapsulant having a plurality of blocks as encapsulant bumps covering the antenna patterns as taught by Lee to have the method, further including depositing a first encapsulant over the antenna substrate, in order to provide a degree of protection for the underlying structure and prevent oxidation of the antenna patterns, and to obtain a high performance package with integrated antenna (Lee, ¶0002, ¶0027, ¶0043).
Claims 9 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0197829 to Stiebler in view of Guzek (US 2021/0134731) as applied to claim 7 (claim 20), and further in view of Hsu (US Patent No. 9,627,346).
Regarding claim 9, Stiebler in view of Guzek discloses the semiconductor device of claim 7. Further, Stiebler does not specifically disclose that a second portion of the bonding material extends over a side surface of the antenna substrate.
However, Hsu teaches forming a semiconductor structure (Hsu, Fig. 1, 2A-2B, Col. 1, lines 19-28; lines 55-67; Col. 2, lines 1-17; Col. 3, lines 1-43; Col. 4, lines 5-19) comprising a package (10) having a larger package size attached to the package substrate (20) by using a plurality of electrical connectors (e.g., solder connectors 18) and bonding material (22) disposed at the lateral edges of the package (10) and surrounding the plurality of electrical connectors (18) along the periphery of the package (10), to provide additional bonding and support to the ball/bump connectors, and thus to enhance the reliability of the package (Hsu, Col. 1, lines 23-28; Col. 4, lines 16-19).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Stiebler/Guzek by forming a bonding material at the lateral edges of the package as a second bonding portion as taught by Hsu, wherein the bonding material surrounds the plurality of electrical connectors between the package and the semiconductor assembly, and wherein the package includes an antenna substrate to have the semiconductor device, wherein a second portion of the bonding material extends over a side surface of the antenna substrate, in order to provide additional bonding and support to the ball/bump connectors, and thus to enhance the reliability of the package (Hsu, Col. 1, lines 23-28; Col. 4, lines 16-19).
Regarding claim 22, Stiebler in view of Guzek discloses the method of claim 20. Further, Stiebler does not specifically disclose that a second portion of the bonding material extends over a side surface of the antenna substrate.
However, Hsu teaches forming a semiconductor structure (Hsu, Fig. 1, 2A-2B, Col. 1, lines 19-28; lines 55-67; Col. 2, lines 1-17; Col. 3, lines 1-43; Col. 4, lines 5-19) comprising a package (10) having a larger package size attached to the package substrate (20) by using a plurality of electrical connectors (e.g., solder connectors 18) and bonding material (22) disposed at the lateral edges of the package (10) and surrounding the plurality of electrical connectors (18) along the periphery of the package (10), to provide additional bonding and support to the ball/bump connectors, and thus to enhance the reliability of the package (Hsu, Col. 1, lines 23-28; Col. 4, lines 16-19).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Stiebler/Guzek by forming a bonding material at the lateral edges of the package as a second bonding portion as taught by Hsu, wherein the bonding material surrounds the plurality of electrical connectors between the package and the semiconductor assembly, and wherein the package includes an antenna substrate to have the method, wherein a second portion of the bonding material extends over a side surface of the antenna substrate, in order to provide additional bonding and support to the ball/bump connectors, and thus to enhance the reliability of the package (Hsu, Col. 1, lines 23-28; Col. 4, lines 16-19).
Claims 10-11 and 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0197829 to Stiebler in view of Guzek (US 2021/0134731) as applied to claim 7 (claim 200, and further in view of Yeon (US 2021/0091017).
Regarding claims 10-11, Stiebler in view of Guzek discloses the semiconductor device of claim 7. Further, Stiebler does not specifically disclose the semiconductor device, wherein the antenna substrate includes a first antenna substrate and a second antenna substrate disposed over the semiconductor assembly (as claimed in claim 10); wherein the first antenna substrate is offset with respect to the second antenna substrate (as claimed in claim 11).
However, Yeon teaches forming antenna in package (AiP) device (300) (Yeon, Fig. 3, ¶0030-¶0031, ¶0038-¶0044, ¶0112) comprising a first antenna device (e.g., 380, including substrate 502/506) (Yeon, Figs. 3, 5, ¶0040-¶0043, ¶0047-¶0050) and a second antenna device (e.g., 370, including substrate 502/506) disposed over the semiconductor assembly (202) and formed separate from fabrication of the semiconductor assembly (202) including a semiconductor device (203/205), wherein the first antenna device (380) has different size and is offset with respect to the second antenna device (370), to provide antenna devices having different capabilities and functionalities to provide an efficient AiP package.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Stiebler/Guzek by forming a plurality of discrete antenna devices on the semiconductor assembly as taught by Yeon to have the semiconductor device, wherein the antenna substrate includes a first antenna substrate and a second antenna substrate disposed over the semiconductor assembly (as claimed in claim 10); wherein the first antenna substrate is offset with respect to the second antenna substrate (as claimed in claim 11), in order to provide antenna devices having different capabilities and functionalities to provide an efficient AiP package (Yeon, ¶0030, ¶0038, ¶0040-¶0044).
Regarding claims 23-24, Stiebler in view of Guzek discloses the method of claim 20. Further, Stiebler does not specifically disclose the method, wherein forming the antenna substrate includes: forming a first antenna substrate; forming a second antenna substrate; and disposing the first antenna substrate and the second antenna substrate over the semiconductor assembly (as claimed in claim 23); wherein the first antenna substrate is offset with respect to the second antenna substrate (as claimed in claim 24).
However, Yeon teaches forming antenna in package (AiP) device (300) (Yeon, Fig. 3, ¶0030-¶0031, ¶0038-¶0044, ¶0112) comprising a first antenna device (e.g., 380, including substrate 502/506) (Yeon, Figs. 3, 5, ¶0040-¶0043, ¶0047-¶0050) and a second antenna device (e.g., 370, including substrate 502/506) disposed over the semiconductor assembly (202) and formed separate from fabrication of the semiconductor assembly (202) including a semiconductor device (203/205), wherein the first antenna device (380) has different size and is offset with respect to the second antenna device (370), to provide antenna devices having different capabilities and functionalities to provide an efficient AiP package.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Stiebler/Guzek by forming a plurality of discrete antenna devices disposed on the semiconductor assembly as taught by Yeon to have the method, wherein forming the antenna substrate includes: forming a first antenna substrate; forming a second antenna substrate; and disposing the first antenna substrate and the second antenna substrate over the semiconductor assembly (as claimed in claim 23); wherein the first antenna substrate is offset with respect to the second antenna substrate (as claimed in claim 24), in order to provide antenna devices having different capabilities and functionalities to provide an efficient AiP package (Yeon, ¶0030, ¶0038, ¶0040-¶0044).
Claims 12 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0197829 to Stiebler in view of Guzek (US 2021/0134731) as applied to claim 7 (claim 20), and further in view of Chuang et al. (US 2020/0212537, hereinafter Chuang).
Regarding claim 12, Stiebler in view of Guzek discloses the semiconductor device of claim 7. Further, Stiebler does not specifically disclose the semiconductor device, wherein the antenna substrate fans out from the semiconductor assembly.
However, Chuang teaches forming a semiconductor device, wherein the antenna substrate (38) (Chuang, Figs. 18, 22A, ¶0013, ¶0036, ¶0046) fans out from the semiconductor assembly (56/77), to provide a fan-out package including an antenna with customized bandwidths of the multi-band antennas.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Stiebler/Guzek by forming an antenna package as taught by Chuang to have the semiconductor device, wherein the antenna substrate fans out from the semiconductor assembly, in order to provide a fan-out package including an antenna with customized bandwidths of the multi-band antennas (Chuang, ¶0002, ¶0013, ¶0046).
Regarding claim 25, Stiebler in view of Guzek discloses the method of claim 20. Further, Stiebler does not specifically disclose the method, wherein the antenna substrate fans out from the semiconductor assembly.
However, Chuang teaches forming a semiconductor device, wherein the antenna substrate (38) (Chuang, Figs. 18, 22A, ¶0013, ¶0036, ¶0046) fans out from the semiconductor assembly (56/77), to provide a fan-out package including an antenna with customized bandwidths of the multi-band antennas.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Stiebler/Guzek by forming an antenna package as taught by Chuang to have the method, wherein the antenna substrate fans out from the semiconductor assembly, in order to provide a fan-out package including an antenna with customized bandwidths of the multi-band antennas (Chuang, ¶0002, ¶0013, ¶0046).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0197829 to Stiebler in view of Guzek (US 2021/0134731) as applied to claim 7, and further in view of Lin (US 2018/0096974).
Regarding claim 13, Stiebler in view of Guzek discloses the semiconductor device of claim 7. Further, Stiebler does not specifically disclose the semiconductor device, wherein the semiconductor assembly includes multiple layers of core material with different coefficient of thermal expansions.
However, Lin teaches forming the semiconductor assembly (210/240/220) (Lin, Fig. 1F, ¶0028-¶0033, ¶0039-¶0040) including multiple layers of core material (212/240/220) with different coefficient of thermal expansions (CTE) (Lin, Fig. 1F, ¶0033, ¶0040), wherein the materials of the substrates (212) of the semiconductor chips (210) and the molding compound (240) are different, which causes a CTE mismatch therebetween. However, the interposer (220) is disposed on the semiconductor chips (210) and the molding compound (240) and has the CTE to improve CTE mismatch problem of the semiconductor package, and to suppress the warpage problem of the semiconductor package (Lin, Fig. 1F, ¶0028-¶0033, ¶0040).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Stiebler/Guzek by forming the semiconductor assembly includes multiple layers of core material as taught by Lin to have the semiconductor device, wherein the semiconductor assembly includes multiple layers of core material with different coefficient of thermal expansions, in order to improve CTE mismatch problem of the semiconductor package, and to suppress the warpage problem of the semiconductor package (Lin, ¶0033, ¶0040).
Response to Arguments
Applicant’s arguments with respect to claims 1-2, 4-5, 7-15, 17-18, and 20-25 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891
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