Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of claims 1-6 in the reply filed on 6/30/2026 is acknowledged. The traversal is on the ground(s) that there is not a search burden on Examiner sufficient to require restriction. This is not found persuasive because the invention of claim 7-10 require additional/different structure than those claims in claims 1-6. Specifically, claims 7-10 require elements such as micro-bumps, a thickened metal layer, and a cutting channel, which require searching different classes/subclasses and different search queries.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ho (US 20210225662 A1) in view of Chen (US 20210020599 A1).
Regarding claim 1, Ho discloses a semiconductor package structure (Fig. 7), comprising a lead frame (comprising 100a and 100b), comprising a supporting part (100a) and a circuit part (100b); a semiconductor component (111) electrically connected to the circuit part (Fig. 7 shows 111 connected to 100b by lead 113), and a molding layer (117) covering the semiconductor component (Shown in Fig. 7). However, Ho does not disclose a nanotwinned metal layer located on the supporting part, the semiconductor component being disposed on the nanotwinned metal layer, the nanotwinned metal layer being located between the supporting part and the semiconductor component, and the molding layer covering the nanotwinned metal layer.
On the other hand, Chen discloses a nanotwinned copper layer (Fig. 6 shows a nanotwinned copper layer comprising at least nanotwinned copper layers 411 and 422). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Ho according to the teachings of Chen such that a nanotwinned copper layer would be disposed atop the supporting part of Ho’s lead frame such that the nanotwinned copper layer would be between the support part and the semiconductor component, and the molding layer would cover the nanotwinned copper layer. One would have been motivated to combine Ho and Chen because of the desirable mechanical and electrical properties of using nanotwinned copper as a bonding structure (Chen para. 52 “those skilled in the art to which the present invention pertains can understand that, since nano-twins copper grains on one side grow towards the nano-twins copper grains on the opposite side and merge therewith, the electrical connecting structure formed therefrom can achieve improved mechanical strength, conductivity, stability and reliability”.
Regarding claim 2, Ho further discloses the semiconductor component comprising a die (Fig. 7, 111) and a contact (The bonding pad on top of the die, not labeled; para. 19 “Two ends of the conductive wire 113 are connected to the bonding pad on the die 111”), and the contact is formed on an outer surface of the die (Shown in fig. 7).
Regarding claim 3, Ho further discloses a lead (Fig. 7, 113), wherein the lead electrically connects the circuit part of the lead frame and the contact of the semiconductor component (Shown).
Regarding claim 4, Chen further discloses wherein the nanotwinned metal layer is a nanotwinned copper layer (Para. 54 “first nano-twins copper layer 411… second nano-twins copper layer 422”).
Regarding claim 5, Ho further discloses wherein the lead frame is made by copper (Para. 18 “The material of lead frame 100 may be Cu-based alloys such as oxygen free copper, deoxidized copper…”).
Regarding claim 6, Ho further discloses wherein the semiconductor package structure is formed by wafer-level packaging (Figs. 1-7 show the device being formed by wafer-level packaging and according a similar process to the manufacturing process shown in Applicant’s figs. 2-7).
Conclusion
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/S.J.S./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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