DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the method step of, “applying an electromagnetic interference (EMI) coating to the die attach film layer,” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 9, and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation, “an epoxy molding coupled with the carrier substrate and covering an exposed surface of the chiplet; and a die attach film layer positioned about the chiplet, wherein: the die attach film layer extends between and separates the chiplet and the epoxy molding,” in lines 6-10 of the claim. It is unclear if the epoxy molding is covering an exposed surface of the chiplet, or if the die attach film layer, which extends between and separates the chiplet and the epoxy molding, is covering an exposed surface of the chiplet. When viewed as a whole, the phrase, “covering an exposed surface,” communicates the meaning of covering or coating an uncovered surface and conflicts with the phrase, “the die attach film layer extends between and separates the chiplet and the epoxy molding”. For the purpose of this office action, the above quoted limitation of claim 1 is interpreted to have the following meaning: an epoxy molding coupled with the carrier substrate and on an upper surface of the chiplet; and a die attach film layer positioned about the chiplet, wherein: the die attach film layer extends between and separates the chiplet and the epoxy molding.
Claim 9 recites the limitation, “an epoxy molding coupled with the carrier substrate and covering an exposed surface of each of the plurality of chiplets,” in lines 10-11 of the claim and recites an additional limitation, “each die attach film layer extends between and separates the respective chiplet and the epoxy molding,” in lines 15-16 of the claim. It is unclear if the epoxy molding is covering an exposed surface of the chiplet, or if the die attach film layer, which extends between and separates the respective chiplet and the epoxy molding, is covering an exposed surface of the respective chiplet. When viewed as a whole, the phrase, “covering an exposed surface,” communicates the meaning of covering or coating an uncovered surface and conflicts with the additional limitation, “each die attach film layer extends between and separates the respective chiplet and the epoxy molding”. For the purpose of this office action, the limitation, “an epoxy molding coupled with the carrier substrate and covering an exposed surface of each of the plurality of chiplets,” of claim 9 is interpreted to have the following meaning: an epoxy molding coupled with the carrier substrate and on an upper surface of each of the plurality of chiplets.
Claim 17 recites the limitation, “applying an epoxy molding to the carrier substrate that covers an exposed surface of the chiplet, wherein the die attach film layer extends between and separates the chiplet and the epoxy molding,” in lines 11-13 of the claim. It is unclear if the epoxy molding is covering an exposed surface of the chiplet, or if the die attach film layer, which extends between and separates the chiplet and the epoxy molding, is covering an exposed surface of the chiplet. When viewed as a whole, the phrase, “covers an exposed surface,” communicates the meaning of covering or coating an uncovered surface and conflicts with the phrase, “the die attach film layer extends between and separates the chiplet and the epoxy molding”. For the purpose of this office action, the above quoted limitation of claim 17 is interpreted to have the following meaning: applying an epoxy molding to the carrier substrate, wherein the epoxy molding is on an upper surface of the chiplet, wherein the die attach film layer extends between and separates the chiplet and the epoxy molding.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6, 8-14, 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Tang et al. (US 11900197 B1; hereinafter referred to as "Tang”) in view of Shen et al. (US 20170018510 A1; hereinafter referred to as "Shen”) and further in view of Kawabata (US PGPub 20180374799 A1; hereinafter referred to as "Kawabata”).
Re claim 1: Tang teaches a flip chip package (FIG. 2: el. 200; col. 5: line 16-28), comprising: a carrier substrate (FIG. 2: el. 240; col. 5: line 16-28); a chiplet electrically and physically coupled with the carrier substrate via a plurality of interconnects (FIG. 2: el. 230; col. 5: line 16-28, col. 6: line 59 - col. 7: line 12); an epoxy molding (FIG. 2: el. 270; col. 5: line 61 - col. 6: line 2) coupled with the carrier substrate and covering an exposed surface of the chiplet (FIG. 2: el. 270|epoxy molding 270 is coupled into the carrier substrate 240 and covers the chiplet 230); and a die attach film layer positioned about the chiplet (FIG. 2: el. 202; col. 5: line 29-41), wherein: the die attach film layer extends between and separates the chiplet and the epoxy molding (FIG. 2: el. 202; col. 5: line 29-41|die attach film layer 202 is positioned between and separates the chiplet 230 from the epoxy molding 270). Tang is silent as to the coefficient of thermal expansion and Young’s modulus of the die attach film layer. Tang is also silent to an underfill positioned between the carrier substrate and the chiplet.
In a similar field of endeavor, Shen teaches a flip chip package (FIG. 6D; para. 45), comprising: a carrier substrate (FIG. 6D: el. 420S; para. 26); a chiplet (FIG. 6D: el. 110; para. 25) electrically and physically coupled with the carrier substrate via a plurality of interconnects (FIG. 6D: el. 434; para. 31); and a die attach film layer positioned about the chiplet (FIG. 6D: el. 474; para. 31)|die attach film layer 474 positioned about chiplet 110). Shen teaches the die attach film layer has a coefficient of thermal expansion of between 30 ppm/C and 35 ppm/C (para. 49, 26|Shen discloses a coefficient of thermal expansion of 12 ppm/C and further teaches the coefficient of thermal expansion as a result effective variable to reduce the warpage of adjoining layers). In the absence of an indication that the claimed range produces unexpected results or has criticality, it would have been obvious at the time of the effective filling date of the claimed invention to adjust the coefficient of thermal expansion of the die attach film layer, to achieve the claimed range of between and including 30ppm/C to 35ppm/C, as a matter of routine optimization. Shen also teaches the die attach film layer has a Young’s modulus of between 4 GPa and 5 GPa, inclusive (para. 31|Shen specifically discloses a Young’s modulus of less than 10 GPa, and as per MPEP 2144.05(i), "in the case where the claimed ranges ‘overlap or lie inside ranges disclosed by the prior art’ a prima facie case of obviousness exists”). Shen further teaches a benefit of a low Young’s modulus of the die attach film which encapsulates the chiplet is an increase in compliance of the die attach film.
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Tang and Shen, to enable using a die attach film layer with the mechanical and thermal properties of the die attach film layer of Shen in the flip chip package of Tang, for the benefit of increased compliance of the die attach film and reduced ability of the die attach film to transfer stress to adjoining layers.
The combination of Tang and Shen does not directly disclose an underfill positioned between the carrier substrate and the chiplet.
In a similar field of endeavor, Kawabata teaches a chip package (FIG. 14; para. 89), comprising: a carrier substrate (FIG. 14: el. 20; para. 44); a chiplet electrically and physically coupled with the carrier substrate via a plurality of interconnects (FIG. 14: el. 31, 24; para. 44, 46); an underfill positioned between the carrier substrate and the chiplet (FIG. 14: el. 51; para. 48). Kawabata further teaches a benefit of the underfill layer is insulation protection of the plurality of solder interconnects existing between the chiplet and the carrier substrate (para. 48).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Kawabata with the teachings of the combination of Tang and Shen, to enable using the underfill of Kawabata in the flip chip package of the combination of Tang and Shen, for the benefit of providing insulation protection to the plurality of interconnects and for the well-known benefit of improving adhesion of chiplets and interconnects to a carrier substrate.
Re claim 2: The combination of Tang, Shen, and Kawabata teaches the flip chip package of claim 1, further comprising: an electromagnetic interference (EMI) coating (Tang - FIG.2: el. 280; col. 5: line 42-60) that extends between the die attach film layer and the epoxy molding (Tang - FIG. 2: el. 280, 202, 270|EMI coating 280 extends between die attach film layer 202 and epoxy molding 270).
Re claim 3: The combination of Tang, Shen, and Kawabata teaches the flip chip package of claim 2, wherein: the EMI coating comprises at least one of graphene, copper, nickel, titanium, cobalt, gold, silver, silicon, vanadium, or glass (Tang - col. 5: line 42-60| EMI coating comprises copper).
Re claim 6: The combination of Tang, Shen, and Kawabata teaches the flip chip package of claim 2, wherein: the EMI coating (Tang - el. 280; col. 5: line 42-60|EMI coating 280 formed of a multilayer consisting of a steel layer on top of a copper layer on top of a bottom steel layer) comprises: a metallic layer (Tang - el. 280; col. 5: line 42-60|bottom steel layer of EMI coating 280); a non-magnetic layer (Tang - el. 280; col. 5: line 42-60|copper layer of EMI coating 280) positioned atop the metallic layer; and a ferromagnetic layer (Tang - el. 280; col. 5: line 42-60|top steel layer of EMI coating 280) positioned atop the non-magnetic layer.
Re claim 8: The combination of Tang, Shen, and Kawabata teaches the flip chip package of claim 1, wherein: the die attach film layer extends between and separates the epoxy molding from the chiplet, the underfill, and the interconnects (Tang – FIG. 2: el. 202, 280, 270, 230; col. 5: line 42 - col. 6: line 2|Tang teaches die attach film layer 202 extends between and separates the epoxy molding 270 (formed over EMI coating 280) from chiplet 230 and underlying interconnects) (Kawabata - FIG. 14: el. 40, 60, 31, 51, 24; para. 48, 90 |Kawabata teaches die attach film 40 extends between and separates the epoxy coated metal EMI shielding layer 60 from underfill 51, and additionally from chiplet 31 and interconnects 24).
Re claim 9: Tang teaches a flip chip package (FIG. 2: el. 200; col. 5: line 16-28), comprising: a carrier substrate (FIG. 2: el. 240; col. 5: line 16-28); a plurality of chiplets, wherein: each chiplet of the plurality of chiplets is electrically and physically coupled with the carrier substrate via a respective plurality of interconnects (FIG. 2: el. 230, 236; col. 5: line 16-28, col. 6: line 59 - col. 7: line 12); and chiplets of the plurality of chiplets are spaced apart from another along a surface of the carrier substrate (FIG. 2: el. 230, 236, 240|chiplets 230, 236 spaced apart from another along carrier substrate 240; an epoxy molding (FIG. 2: el. 270; col. 5: line 61 - col. 6: line 2) coupled with the carrier substrate and covering an exposed surface of each of the plurality of chiplets (FIG. 2: el. 270|epoxy molding 270 is coupled into the carrier substrate 240 and covers the chiplet 230 and chiplet 236); and a plurality of die attach film layers, wherein: each die attach film layer of the plurality of die attach film layers is positioned about a respective chiplet of the plurality of chiplets (FIG. 2: el. 202; col. 5: line 29-41|die attach film layers formed of portions of 202 surrounding the sides and top of each respective chiplet 230, 236); each die attach film layer extends between and separates the respective chiplet and the epoxy molding (FIG. 2: el. 202; col. 5: line 29-41|die attach film layers 202 extend between and separate each respective chiplet 230, 236 from epoxy molding 270). Tang is silent as to the coefficient of thermal expansion and Young’s modulus of the die attach film layers. Tang is also silent to a plurality of underfills.
In a similar field of endeavor, Shen teaches a flip chip package (FIG. 6D; para. 45), comprising: a plurality of chiplets (FIG. 6D: el. 110, 110; para. 25), and a die attach film layer positioned about the chiplets (FIG. 6D: el. 474; para. 31). Shen teaches the die attach film layer positioned about each respective chiplet has a coefficient of thermal expansion of between 30 ppm/C and 35 ppm/C (para. 49, 26|Shen discloses a coefficient of thermal expansion of 12 ppm/C and further teaches the coefficient of thermal expansion as a result effective variable to reduce the warpage of adjoining layers). In the absence of an indication that the claimed range produces unexpected results or has criticality, it would have been obvious at the time of the effective filling date of the claimed invention to adjust the coefficient of thermal expansion of the die attach film layer, to achieve the claimed range of between and including 30ppm/C to 35ppm/C, as a matter of routine optimization. Shen also teaches the die attach film layer positioned about each respective chiplet has a Young’s modulus of between 4 GPa and 5 GPa, inclusive (para. 31|Shen specifically discloses a Young’s modulus of less than 10 GPa, and as per MPEP 2144.05(i), "in the case where the claimed ranges ‘overlap or lie inside ranges disclosed by the prior art’ a prima facie case of obviousness exists”). Shen further teaches a benefit of a low Young’s modulus of the die attach film which encapsulates the chiplet is an increase in compliance of the die attach film.
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Tang and Shen, to enable using a die attach film layer with the mechanical and thermal properties of the die attach film layer of Shen in the flip chip package of Tang, for the benefit of increased compliance of the die attach film and reduced ability of the die attach film to transfer stress to adjoining layers.
The combination of Tang and Shen does not directly disclose a plurality of underfills, wherein each underfill of the plurality of underfills is positioned between the carrier substrate and a respective chiplet of the plurality of chiplets.
In a similar field of endeavor, Kawabata teaches a chip package (FIG. 14; para. 89), comprising: a carrier substrate (FIG. 14: el. 20; para. 44); a plurality of chiplets (FIG. 14: el. 31, 32), wherein: each chiplet of the plurality of chiplets is electrically and physically coupled with the carrier substrate via a respective plurality of interconnects; (FIG. 14: el. 31, 32, 24; para. 44, 46); a plurality of underfills (FIG. 14: el. 51, 52), wherein each underfill of the plurality of underfills is positioned between the carrier substrate and a respective chiplet of the plurality of chiplets (FIG. 14: el. 51, 52; para. 48). Kawabata further teaches a benefit of each underfill is insulation protection of the plurality of solder interconnects existing between each chiplet and the carrier substrate (para. 48).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Kawabata with the teachings of the combination of Tang and Shen, to enable using the plurality of underfills of Kawabata in the flip chip package of the combination of Tang and Shen, for the benefit of providing insulation protection to the plurality of interconnects and for the well-known benefit of improving adhesion of chiplets and interconnects to a carrier substrate.
Re claim 10: The combination of Tang, Shen, and Kawabata teaches the flip chip package of claim 9, wherein: the carrier substrate comprises an organic substrate (Tang - col. 5: line 16-28|Tang teaches the carrier substrate as a printed circuit board; Shen - para. 3-5|Shen teaches that wiring substrates such as printed circuit boards comprise organic polymers).
Re claim 11: The combination of Tang, Shen, and Kawabata teaches the flip chip package of claim 9, further comprising: a plurality of electromagnetic interference (EMI) coatings, wherein each EMI coating of the plurality of EMI coatings extends between the epoxy molding and a respective die attach film layer of the plurality of die attach film layers (Tang - FIG.2: el. 280; para. 27|discrete sub-sections of element 280 provide a plurality of EMI coatings which extend between a respective die attach layer and the epoxy molding).
Re claim 12: The combination of Tang, Shen, and Kawabata teaches the flip chip package of claim 11, wherein: each of the plurality of EMI coatings comprises multiple layers (Tang - el. 280; col. 5: line 42-60|EMI coating 280 formed of a multilayer consisting of a steel layer on top of a copper layer on top of a bottom steel layer).
Re claim 13: The combination of Tang, Shen, and Kawabata teaches the flip chip package of claim 11, wherein: each of the plurality of EMI coatings comprises at least one metallic layer (Tang - el. 280; col. 5: line 42-60|EMI coating 280 formed of a multilayer including a metallic steel layer).
Re claim 14: The combination of Tang, Shen, and Kawabata teaches the flip chip package of claim 9, wherein: each die attach film layer extends between and separates the epoxy molding from the respective chiplet, a respective underfill, and the interconnects (Tang – FIG. 2: el. 202, 280, 270, 230, 236; col. 5: line 42 - col. 6: line 2|Tang teaches each die attach film layer 202 extends between and separates the epoxy molding 270 (formed over EMI coating 280) from respective chiplet 230, 236 and underlying interconnects) (Kawabata - FIG. 14: el. 40, 60, 31, 51, 24; para. 48, 90 |Kawabata teaches die attach film 40 extends between and separates the epoxy coated metal EMI shielding layer 60 from underfill 51, and additionally from chiplet 31 and interconnect 24).
Re claim 16: The combination of Tang, Shen, and Kawabata teaches the flip chip package of claim 9, wherein: each die attach film layer comprises a conductive material (Shen – para. 31) (Kawabata – para. 44, 59).
Re claim 17: Tang teaches a method of producing a flip chip package, comprising: electrically and physically coupling a chiplet to a carrier substrate via a plurality of interconnects (FIG. 3: el. 310; col. 7: line 66 – col. 8: line 2; FIG. 2: el. 230, 240; col. 5: line 16-28, col. 6: line 59 - col. 7: line 12); applying a die attach film layer to an exposed surface of the chiplet (FIG. 3: el. 320; col. 8: line 2-9; FIG. 2: el. 202; col. 5: line 29-41|die attach film layer 202 positioned on the sides and top of the chiplet 230); and applying an epoxy molding to the carrier substrate that covers an exposed surface of the chiplet, wherein the die attach film layer extends between and separates the chiplet and the epoxy molding (FIG. 2: el. 202; col. 5: line 29-41|die attach film layer 202 positioned on the sides and top of the chiplet 230; die attach film layer 202 is positioned between and separates the chiplet 230 from the epoxy molding 270). Tang is silent as to the coefficient of thermal expansion and Young’s modulus of the die attach film layer. Tang is also silent to applying an underfill between the chiplet, the carrier substrate, and the plurality of interconnects.
In a similar field of endeavor, Shen teaches a method of producing a flip chip package, comprising: electrically and physically coupling a chiplet to a carrier substrate via a plurality of interconnects (FIG. 8B, 6D: el. 420S, 110, 434; para. 26, 25, 31, 57); applying a die attach film layer to an exposed surface of the chiplet (FIG. 8C: el. 474; para. 31, 58). Shen teaches the die attach film layer has a coefficient of thermal expansion of between 30 ppm/C and 35 ppm/C (para. 49, 26|Shen discloses a coefficient of thermal expansion of 12 ppm/C and further teaches the coefficient of thermal expansion as a result effective variable to reduce the warpage of adjoining layers). In the absence of an indication that the claimed range produces unexpected results or has criticality, it would have been obvious at the time of the effective filling date of the claimed invention to adjust the coefficient of thermal expansion of the die attach film layer, to achieve the claimed range of between and including 30ppm/C to 35ppm/C, as a matter of routine optimization. Shen also teaches the die attach film layer has a Young’s modulus of between 4 GPa and 5 GPa, inclusive (para. 31|Shen specifically discloses a Young’s modulus of less than 10 GPa, and as per MPEP 2144.05(i), "in the case where the claimed ranges ‘overlap or lie inside ranges disclosed by the prior art’ a prima facie case of obviousness exists”). Shen further teaches a benefit of a low Young’s modulus of the die attach film which encapsulates the chiplet is an increase in compliance of the die attach film.
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Tang and Shen, to enable using a die attach film layer with the mechanical and thermal properties of the die attach film layer of Shen in the flip chip package of Tang, for the benefit of increased compliance of the die attach film and reduced ability of the die attach film to transfer stress to adjoining layers.
The combination of Tang and Shen does not directly disclose applying an underfill between the chiplet, the carrier substrate, and the plurality of interconnects.
In a similar field of endeavor, Kawabata teaches a method of producing a chip package (para. 51), comprising: electrically and physically coupling a chiplet to a carrier substrate via a plurality of interconnects (FIG. 2; para. 54); applying an underfill between the chiplet, the carrier substrate, and the plurality of interconnects (FIG. 3; para. 55). Kawabata further teaches a benefit of the underfill application is insulation protection of the plurality of solder interconnects existing between the chiplet and the carrier substrate (para. 48).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Kawabata with the teachings of the combination of Tang and Shen, to enable using the underfill of Kawabata in the flip chip package of the combination of Tang and Shen, for the benefit of providing insulation protection to the interconnects and for the well-known benefit of improving adhesion of chiplets and interconnects to a carrier substrate.
Re claim 18: The combination of Tang, Shen, and Kawabata teaches the method of producing a flip chip package of claim 17, wherein: the underfill comprises an electrically-insulating adhesive (Kawabata - para. 48).
Re claim 19: The combination of Tang, Shen, and Kawabata teaches the method of producing a flip chip package of claim 17, wherein: the plurality of interconnects comprise solder bumps (Tang – FIG. 2; col. 8: line 57 – col. 9: line 2|Tang teaches solder bumps for forming electrical connections between package parts) (Shen – FIG. 6D: el. 434; para. 31) (Kawabata – para. 46); and electrically and physically coupling the chiplet to the carrier substrate comprises remelting the solder bumps to join electrical pads of the chiplet with electrical connectors of the carrier substrate (Kawabata – para. 54).
Re claim 20: The combination of Tang, Shen, and Kawabata teaches the method of producing a flip chip package of claim 17, further comprising: applying an electromagnetic interference (EMI) coating to the die attach film layer, wherein the EMI coating is disposed between the die attach film and the epoxy molding (Tang – FIG. 4: el. 410; col. 8: line 15-30; FIG. 2: el. 280; col. 5: line 29-41|EMI coating 280 formed on surface of die attach film layer; EMI coating is disposed between the die attach film 202 and the epoxy molding 270).
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Tang in view of Shen and Kawabata as applied to claim 2 above, and further in view of Lin et al. (US PGPub 20170200682 A1; hereinafter referred to as "Lin”).
Re claim 4: The combination of Tang, Shen, and Kawabata fails to directly disclose the flip chip package of claim 2, wherein: the EMI coating comprises: an adhesion layer; a shield metal layer positioned atop the adhesion layer; and a cap layer positioned atop the shield metal layer.
In a similar field of endeavor, Lin teaches a flip chip package (para. abstract, 18), comprising: a carrier substrate (FIG. 1A: el. 10; para. 16); a chiplet electrically and physically coupled with the carrier substrate (FIG. 1A: el. 11a; para. 18); a die attach film layer positioned about the chiplet (FIG. 1A: el. 12; para. 20); and an electromagnetic interference (EMI) coating (FIG. 1A: el. 13, 14a, 14b, 15; para. 16, 21, 29). Lin teaches the flip chip package of claim 2, wherein: the EMI coating comprises: an adhesion layer (FIG. 1A: el. 13; para. 21-22 |seed layer 13 used as adhesion layer to increase adhesion of the EMI shield layers 14 to the package); a shield metal layer positioned atop the adhesion layer (FIG. 1A: el. 14a, 14b; para. 23); and a cap layer positioned atop the shield metal layer (FIG. 1A: el. 15; para. 29). Lin further teaches a benefit of the adhesion layer 13 is to improve adhesion between the EMI shielding layers and the surface of a package body formed by the encapsulating die attach layer 12 (para. 22).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Lin with the teachings of the combination of Tang, Shen, and Kawabata, to enable using the adhesion layer and the protection layer of Lin in the EMI coating of the combination of Tang, Shen, and Kawabata, for the benefit of improving adhesion between the EM interference coating and the surface of the die attach layer.
Re claim 5: The combination of Tang, Shen, Kawabata, and Lin teaches the flip chip package of claim 4, wherein: the adhesion layer has a thickness of between 200 nm and 300 nm, inclusive (Lin - FIG. 1b: item 1|seed adhesion layer formed with a thickness of 200nm) the shield metal layer has a thickness of between 3 µm and 6 µm, inclusive (Lin – FIG. 1b: item 1|layered EMI shield formed with a thickness of 5.4 µm) (Tang - col. 6: line 43-51; claim 5); and the cap layer has a thickness of between 200 nm and 300 nm, inclusive (Lin – FIG. 1b: item 1; para. 32-33|Lin discloses a thickness of the protective cap layer of 100 nm and further teaches the thickness of the EMI coating layer including the thickness of the cap layer is a result effective variable to obtain a desired thickness for protection while minimizing a manufacturing cost). In the absence of an indication that the claimed range produces unexpected results or has criticality, it would have been obvious at the time of the effective filling date of the claimed invention to adjust the thickness of the protective cap layer, to achieve the claimed range of 200 nm to 300 nm, as a matter of routine optimization.
Claims 7 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Tang in view of Shen and Kawabata as applied to claim 1 and 9 above, and further in view of Lee et al. (US PGPub 20220223566 A1; hereinafter referred to as "Lee”).
Re claim 7: The combination of Tang, Shen, and Kawabata fails to teach the flip chip package of claim 1, wherein: the chiplet comprises a first chiplet; and the flip chip package further comprises a second chiplet stacked atop the first chiplet.
In a similar field of endeavor, Lee teaches a flip chip package (FIG. 1A: el. 1; para. 9, 25), comprising: a carrier substrate (FIG. 1A: el. 100; para. 25); a chiplet electrically and physically coupled with the carrier substrate via a plurality of interconnects (FIG. 1A: el. 200, CS1; para. 34, 42|chiplet 200 coupled via interconnects CS1); and a die attach film layer positioned about the chiplet (FIG. 1A: el. BA; para. 68). Lee teaches the flip chip package of claim 1, wherein: the chiplet comprises a first chiplet (FIG. 1A: el. 200; para. 34); and the flip chip package further comprises a second chiplet (FIG. 1A: el. 300; para. 47) stacked atop the first chiplet (FIG 1A: el. 200, 300). Lee further teaches a benefit of stacking chips in a chip package is the ability to achieve a large capacity as well as miniaturization in the chip package (para. 3).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Lee with the teachings of the combination Tang, Shen, and Kawabata, to enable using the stacked chip structure of Lee in the flip chip package of the combination of Tang, Shen, and Kawabata, for the benefit of both a large capacity and miniaturization in the chip package.
Re claim 15: The combination of Tang, Shen, and Kawabata fails to teach the flip chip package of claim 9, wherein: at least one chiplet of the plurality of chiplets is vertically stacked with an additional chiplet.
In a similar field of endeavor, Lee teaches a flip chip package (FIG. 2L), comprising: a carrier substrate (FIG. 2L: el. 100; para. 111); a plurality of chiplets (FIG. 2L: el. 200, 300, 400; para. 111), and a die attach film layer positioned about the chiplets (FIG. 2L: el. MD: BA; para. 112). Lee teaches the flip chip package of claim 9, wherein: at least one chiplet (FIG. 2L: el. 200; para. 111) of the plurality of chiplets (FIG. 2L: el. 200, 300, 400; para. 111|plurality of chiplets including chiplets 200, 300, 400, as well as laterally adjacent chiplets) is vertically stacked with an additional chiplet (FIG. 2L: el. 300). Lee further teaches a benefit of stacking chips in a chip package is the ability to achieve a large capacity as well as miniaturization in the chip package (para. 3).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Lee with the teachings of the combination Tang, Shen, and Kawabata, to enable using the lateral and stacked chip structure of Lee in the flip chip package of the combination of Tang, Shen, and Kawabata, for the benefit of both a large capacity and miniaturization in the chip package.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEVIN GOODLING whose telephone number is (571)272-2552. The examiner can normally be reached M-F 7:30am - 5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/D.G./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
Prosecution Insights