DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 2 and 16-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sekiya (US 2007/0166146 A1, of record).
Regarding claims 2 and 16-19:
re claim 2, Sekiya discloses a wafer 2 (Figs. 1-3 and [0014]) having an outer circumferential chamfered portion 8, wherein the outer chamfered portion is formed between an outer edge of a front surface 4 of the wafer and an outer edge of a back surface 6 of the wafer (e.g., in Figs. 2-3, outer edges of the front 4 and back 6 surfaces are considered to be the edges where the horizontal portions of “4” and “6” end, and the curved side “8” begins), comprising:
a flat surface 16 (Figs. 1-3 and [0016]) inclined from a direction orthogonal to a front surface 4 (Fig. 3 and [0016, lines 5-8]) of the wafer 2 and formed in a region of the outer circumferential chamfered portion 8 (Fig. 3).
re claim 16, the wafer of claim 2, wherein the flat surface 16 has an elliptical shape (Fig. 4);
re claim 17, the wafer of claim 2, wherein the flat surface 16 has an elliptical shape that has a major axis 18 (Fig. 4 and [0016]) parallel to a circumferential direction of the wafer 2;
re claim 18, the wafer of claim 2, wherein the surface 16 (Fig. 3) is formed inward in the
radial direction of the wafer 2 from the outermost circumferential edge (dotted outermost edge shown in Fig. 3) of the wafer in a range shorter than a length of the outer circumferential chamfered portion in the radial direction of the wafer; wherein each flat surface 16 is formed on a side of an outer circumference of the wafer beyond the outer edges of the front surface and back surface of the wafer, the outer edges of the wafer forming opposite ends of the outer
circumferential chamfered portion of the wafer (e.g., in Figs. 2-3, outer edges of the front 4 and back 6 surfaces are considered to be the edges where the horizontal portions of “4” and “6” end, and the curved side “8” begins); and
re claim 19, the wafer of claim 2, wherein the flat surface 16 is formed along a crystal orientation [0016];
Therefore, Sekiya anticipates claim 2 and 16-19.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3, 4, 7-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Arikado et al. (US 2003/003608 A1; hereinafter, “Arikado”) in view of Sekiya.
Regarding claim 1:
Arikado discloses a wafer 91 (Fig. 37 and [0249]) having an outer circumferential chamfered portion 92 (Note: Merriam-Webster defines “chamfer” as beveled edge), the wafer having a front surface 95 (Figs. 38-39A) and a back surface (opposite “95” in Figs. 38-39A), comprising:
at least three flat surfaces 94a, 94b, 94c (Figs. 39A, 41, 42, [0249] and [0262]) formed along a circumferential direction of the wafer in a region of the outer circumferential chamfered portion (Fig. 42), wherein the flat surfaces are [inclined] to the front surface and back surface of the wafer;
wherein the flat surfaces define circular arcs between adjacent ones thereof, respectively (e.g., in Fig. 43, circular arcs are between 94a/94b, 94b/94c, 94c/94a, etc.), and at least two of the circular arcs have lengths different from each other (e.g., in a clockwise direction, a length of the circular arc between 94a/94b is different from that between 94c/94a).
Arikado does not disclose the flat surfaces are orthogonal to both the front and back surfaces, i.e., Arikado essentially discloses the inclined flat surfaces are created on the face of the wafer (Figs. 38-39A)
Sekiya teaches [0003], when detection means are disposed on a wafer in a manner similar to the flat surfaces in Arikado, local defects are created that lead to a decrease in effective area for forming semiconductor devices and in the strength of the wafer. Sekiya teaches a flat detection surface 16 (Figs. 1-3 and [0016]) created on an outer circumferential chamfered portion 8 and orthogonal to the front 4 and back 6 of the wafer 2. Sekiya discloses creating detection flats in such location prevents local defect to the face of a wafer and does not markedly decrease the strength of the wafer [0004].
It would have been obvious to one of ordinary skill in the art to modify Arikado by repositioning the flat surfaces to be orthogonal to the front and back surfaces of the wafer, as taught by Sekiya, because the modification could significantly prevent local defects on the front/face of the wafer and prevent decrease in the wafer’s strength.
Regarding claim 3:
Arikado discloses a front/back surface determination method for determining a front or back surface of a wafer 91 (Fig. 38 and [0249]) having an outer circumferential chamfered portion 92 (Note: Merriam-Webster defines “chamfer” as beveled edge) and including at least three flat surfaces 94 (i.e., 94a, 94b, 94c, see Figs. 39A, 41, 42, [0249] and [0262]) formed along a circumferential direction of the wafer in a region of the outer circumferential chamfered portion, the flat surfaces defining circular arcs between adjacent ones thereof, respectively (e.g., in Fig. 43, circular arcs are between 94a/94b, 94b/94c, 94c/94a, etc.), and at least two of the circular arcs having lengths different from each other (e.g., in a clockwise direction, a length of the circular arc between 94a/94b is different from that between 94c/94a) , comprising:
a detection step of irradiating a side surface of the outer circumferential chamfered portion, the side surface including the flat surfaces 94, with light 99 [0277] along the circumferential direction of the wafer by a sensor 98/108 (Fig. 44 and [0277]) having a light transmitter unit 98 that irradiates the side surface of the outer circumferential chamfered portion with the light 99 and a light receiver unit 108 (Fig. 44 and [0277]) that receives reflected light from the side surface, thereby detecting a plurality of the flat surfaces based on the reflected light received at the light receiver unit [0277], and
a determination step of determining, from intervals of the at least three flat surfaces detected in the detection step, which one of the front and back surfaces of the wafer is directed upward (i.e., the three flat surface 94a, 94b, 94c are formed, at known intervals; accordingly, when a wafer, as shown in Fig. 42, is rotated clockwise at a constant speed, the time intervals between the reflected light received from each of the three flat surfaces is known/measured, and from the three time intervals, e.g., 94a-94c-94b---94a-94c-9b, etc., then it is known that the front of the wafer is directed upward; on the other hand, if the measured intervals are 94a-94b-94c---94a-94b-94c, etc., then it is known the back of the wafer is directed upward).
Arikado does not disclose the sensor 98/108 (Fig. 44) is positioned radially to the side of the wafer, i.e., Arikado discloses the inclined flat surfaces are created on the face of the wafer (Figs. 38-39A); accordingly, Arikado positions the sensor 98/108 above the wafer in a manner essentially orthogonal to the face of the wafer.
Sekiya teaches [0003], when detection means are disposed on a wafer in a manner similar to the flat surfaces in Arikado, local defects are created that lead to a decrease in effective area for forming semiconductor devices and in the strength of the wafer. Sekiya teaches a flat detection surface 16 (Figs. 1-3 and [0016]) created on an outer circumferential chamfered portion 8 and orthogonal to the front 4 and back 6 of the wafer 2. Sekiya discloses creating detection flats in such location prevents local defect to the face of a wafer and does not markedly decrease the strength of the wafer [0004].
It would have been obvious to one of ordinary skill in the art to modify Arikado by repositioning the flat surfaces to be orthogonal to the front and back surfaces of the wafer, as taught by Sekiya, because the modification could significantly prevent local defects on the front/face of the wafer and prevent decrease in the wafer’s strength. Also, when Arikado is modified as taught by Sekiya, it would have been obvious to position the sensor 98/108 radially to the side of the wafer because the flats are facing radially outward from the side of the wafer, i.e., in order to properly use the sensor 98/108, it must be positioned such that the light 99 is emitted directly toward the flat surfaces. Furthermore, it would have been obvious to utilize the information from the intervals between the flat surfaces to determine which side of the wafer is up or down in order to prevent unwanted processing of a wrong side of a wafer.
Regarding claim 4:
Arikado discloses a front/back surface determination method for determining a front or back surface of a wafer 91 (Fig. 38 and [0249]) having an outer circumferential chamfered portion 92, the wafer including a flat surface 94 (Fig. 39 and [0262]) inclined from a direction orthogonal to the front surface of the wafer 91 (e.g., upper surface of wafer 91 in Fig. 38) and formed in a region of the outer circumferential chamfered portion 92 (Fig. 38), comprising:
irradiating a side surface of the outer circumferential chamfered portion (Fig. 44 and [0275-0277]), the side surface including the flat surface 94, with light 99 [0277] along a circumferential direction of the wafer 91 by a sensor 98/108 (Fig. 44 and [0277]) having a light transmitter unit 98 that irradiates the side surface of the outer circumferential chamfered portion with the light 99 and a light receiver unit 108 that receives reflected light from the side surface, and determining, based on the reflected light from the side surface, which one of the front and back surfaces of the wafer is directed upward (i.e., the three flat surface 94a, 94b, 94c are formed, at known intervals; accordingly, when a wafer, as shown in Fig. 42, is rotated clockwise at a constant speed, the time intervals between the reflected light received from each of the three flat surfaces is known/measured, and from the three time intervals, e.g., 94a-94c-94b---94a-94c-9b, etc., then it is known that the front of the wafer is directed upward; on the other hand, if the measured intervals are 94a-94b-94c---94a-94b-94c, etc., then it is known the back of the wafer is directed upward).
Arikado does not disclose the sensor 98/108 (Fig. 44) is positioned radially to the side of the wafer, i.e., Arikado discloses the inclined flat surfaces are created on the face of the wafer (Figs. 38-39A); accordingly, Arikado positions the sensor 98/108 above the wafer in a manner essentially orthogonal to the face of the wafer.
Sekiya teaches [0003], when detection means are disposed on a wafer in a manner similar to the flat surfaces in Arikado, local defects are created that lead to a decrease in effective area for forming semiconductor devices and in the strength of the wafer. Sekiya teaches a flat detection surface 16 (Figs. 1-3 and [0016]) created on an outer circumferential chamfered portion 8 and orthogonal to the front 4 and back 6 of the wafer 2. Sekiya discloses creating detection flats in such location prevents local defect to the face of a wafer and does not markedly decrease the strength of the wafer [0004].
It would have been obvious to one of ordinary skill in the art to modify Arikado by repositioning the flat surfaces to be orthogonal to the front and back surfaces of the wafer, as taught by Sekiya, because the modification could significantly prevent local defects on the front/face of the wafer and prevent decrease in the wafer’s strength. Also, when Arikado is modified as taught by Sekiya, it would have been obvious to position the sensor 98/108 radially to the side of the wafer because the flats are facing radially outward from the side of the wafer, i.e., in order to properly use the sensor 98/108, it must be positioned such that the light 99 is emitted directly toward the flat surfaces. Furthermore, it would have been obvious to utilize the information from the intervals between the flat surfaces to determine which side of the wafer is up or down in order to prevent unwanted processing of a wrong side of a wafer.
Regarding claims 7-13:
re claim 7, Sekiya discloses the outer circumferential chamfered portion 8 is formed between an outer edge of a front surface 4 (Figs. 1-3 and [0014]) of the wafer and an outer edge of a back surface 6 of the wafer and wherein the flat surface 16 are formed entirely in a region of the outer circumferential chamfered portion 8 (Fig. 3);
re claim 8, Sekiya discloses each flat surface 16 has an elliptical shape (Fig. 4);
re claim 9, Sekiya discloses each flat surface 16 has an elliptical shape that has a major axis 18 (Fig. 4 and [0016]) parallel to a circumferential direction of the wafer 2;
re claim 10, Sekiya discloses each flat surface 16 (Fig. 3) is formed inward in the
radial direction of the wafer 2 from the outermost circumferential edge (dotted outermost edge shown in Fig. 3) of the wafer in a range shorter than a length of the outer circumferential chamfered portion in the radial direction of the wafer; wherein each flat surface 16 is formed on a side of an outer circumference of the wafer beyond the outer edges of the front surface and back surface of the wafer, the outer edges of the wafer forming opposite ends of the outer
circumferential chamfered portion of the wafer (e.g., in Figs. 2-3, outer edges of the front 4 and back 6 surfaces are considered to be the edges where the horizontal portions of “4” and “6” end, and the curved side “8” begins);
re claim 11, Sekiya discloses at least one of the three flat surfaces 16 is formed along a crystal orientation [0016];
re claim 12, Arikado discloses the flat surfaces (94a, 94b, 94c in Fig. 72) are formed relatively close to one another in a central angle range of 90°; and
re claim 13, Sekiya discloses the circular arc between a first 94a (Fig. 42) and a second 94b of adjacent ones of the flat surfaces and wherein the circular arc between the second 94b and a third 94c of adjacent ones of the flat surfaces are each smaller than 90°.
Therefore, Arikado (in view of Sekiya) renders obvious claims 7-13.
Claim(s) 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sekiya.
Regarding claims 14 and 15:
Sekiya anticipates claim 2 and discloses (in [0015]) the flat surface 16 preferably extends substantially perpendicular to the face 4 and the back 4 (Fig. 3). However, Sekiya does not explicitly disclose a range for an angle that would be considered “substantially perpendicular”. Accordingly, Sekiya does not disclose a range of an angle greater than 0° and equal or smaller than 5° (or greater than 0° and equal or smaller than 1°).
Although Sekiya does not explicitly disclose a range as currently claimed, the current claims are deemed obvious because the prior art discloses the general conditions of the claimed invention and specifically discloses the flat surface is “substantially perpendicular”. In other words, Sekiya does not disclose (or require) the flat surface to be exactly 90°; accordingly, it would have been obvious to one of ordinary skill in the art to specify ranges as currently claimed because such ranges are “substantially perpendicular”.
Claim(s) 20-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sekiya in view of Arikado.
Regarding claims 20 and 21:
Sekiya anticipates claim 2 but does not disclose at least three flat surfaces and the flat surfaces are formed relatively close to one another in a central angle range of 90°, wherein the circular arc between a first and a second of adjacent ones of the flat surfaces and wherein the circular arc between the second and a third of adjacent ones of the flat surfaces are each smaller than 90°.
Arikado teaches at least three flat surfaces (94a, 94b, 94c in Fig. 42) formed relatively close to one another in a central angle range of 90°, wherein the circular arc between a first and a second of adjacent ones of the flat surfaces and wherein the circular arc between the second and a third of adjacent ones of the flat surfaces are each smaller than 90°. Arikado discloses such flat surfaces can be used to determine different crystal orientations on a wafer (e.g., [0023 and 0069]).
It would have been obvious to one of ordinary skill in the art to modify Sekiya by incorporating at least three flat surfaces, a taught by Arikado, because the modification would provide means for determining different crystal orientations on a wafer.
Remarks
The objection to the title is withdrawn in view of the amendment.
The rejections of claims 5 and 6 under 35 U.S.C. 112(b) are rendered moot in view of the cancelation of claims 5 and 6.
Applicant’s remarks have been carefully reviewed and considered, but they are moot in view of the new grounds of rejections. With regard to applicants remarks that no portion of ARIKADO is cited in support of anything with respect to determining “which one of the front and back surfaces of the wafer is directed upward.” The examiner respectfully notes that one of ordinary skill in the art would readily realize various aspects of the wafer can be determined from the signal received from ARIKADO because the flat surfaces are formed at specific intervals. For example, the rate at which each of the flat surfaces is detected relative to the other two flat surfaces could be easily measured, and when the wafer is rotated at a known speed, there will be a specific time between surface 94a and 94b, and this specific time depends directly on whether the wafer is facing upward or facing downward. Therefore, the examiner respectfully disagrees that one of ordinary skill in the art would need an explicit disclosure from ARIKADO to realize that the sensed signals from the flat surfaces could be readily used to determine which side of the wafer is facing upward (or downward).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEX H MALSAWMA whose telephone number is (571)272-1903. The examiner can normally be reached M-F (4-12 Hours, between 5:30AM-10PM).
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/LEX H MALSAWMA/Primary Examiner, Art Unit 2892
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