Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
1. Applicant's election, with traverse, of claims 1-15 in the “Response to Restriction Requirement” filed on 06/10/2026 is acknowledged and entered by the Examiner.
Applicant’s traversal arguments, in “Applicant Arguments/Remarks Made” with the reply “Response to Election / Restriction Filed” filed on 06/10/2026, see “Applicant respectfully notes that in the Inventive Concept Election, the Restriction Requirement states that "Invention Group I and Group II are related as process and product made". Thus, the Office submits that Claims 1-15 and claims 16-19 both are directed to process. Claims 16-19 are directed to a non-transitory computer readable medium that, when executed by a controller of a processing chamber, causes the processing chamber to form a semiconductor device by performing all of the same method steps recited by claim 1. Accordingly, a search of the method of claim 1 will result in the same art to evaluate claims 16-19. Thus, there is no search burden. The Species Election, therefore, should be withdrawn and claims 16-19 should be rejoined”, (remarks on page 7) have been fully considered. The examiner respectfully disagrees with the Applicant’s arguments for the following reasons:
Firstly, Species I-II, as claimed, are independent or distinct because they have been disclosed in separate figures and different embodiments, and are characterized by mutually exclusive characteristics, as detailed below.
Species I: A method of forming a semiconductor device, as
described in (Fig. 1; [0005, 0009, 0030-0056]), of which claims 1-15 appear to read upon.
Species II: A non-transitory computer readable medium including instructions, that, when executed by a controller of a processing chamber, causes the processing chamber to perform operations, as described in (Fig. 5; [0006, 0013, 0076-0085]), of which claims 16-19 appear to read upon.
Please note that a listing of claims readable upon the Species I-II in this Office Action is only a guide line, and not a binding to the applicant to elect from. However, as detailed below later, Applicant must include an identification of the species that is elected, and a listing of all claims readable thereon, including any claims subsequently added.
Species I-II as claimed are independent or distinct because they have been disclosed in separate figures and different embodiments, and are characterized by mutually exclusive characteristics as follows:
Regarding Species I and II, are mutually exclusive with “to remove each of the plurality of release layers to form a plurality of voids in the superlattice structure, the plurality of semiconductor material layers extending between an epitaxial source region and an epitaxial drain region, the epitaxial source region and the epitaxial drain region substantially free of defects; and forming a self-aligned dielectric material in each of the plurality of voids on a sidewall of the epitaxial source region and on a sidewall of the epitaxial drain region” (Fig. 1; [0005, 0009, 0030-0056]) in Species I, and, “a non-transitory computer readable medium including instructions, that, when executed by a controller of a processing chamber, causes the processing chamber to perform operations o” (Fig. 5; [0006, 0013, 0076-0085]) in Species II.
Thus , there is a search and/or examination burden for the patentably distinct species as set forth above because at least the following reasons apply: the species or groupings of patentably indistinct species have acquired a separate status in the art due to their recognized divergent subject matter as exemplified by the aforementioned mutually exclusive characteristics, while the species or groupings of patentably indistinct species require a different field of search (different search strategies or search queries, as evidenced by the above-defined distinctions between the species) (see MPEP § 808.02) and/or the prior art applicable to one species would not likely be applicable to another species; and/or the inventions are likely to raise different non-prior art issues under 35 U.S.C. 101 and/or 35 U.S.C. 112, first paragraph.
The requirement is still deemed proper and is therefore made FINAL.
This office action consider claims 1-15 pending for prosecution, wherein claims 16-20 are withdrawn from further consideration, and claims 1-15 are presented for examination.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (100; Fig 3A; [0063]) = (element 100; Figure No. 3A; Paragraph No. [0063]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
2. Claims 1-2, 5, 7-8, and 10-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ching et al. (US 20230369458 A1; hereinafter Ching).
Regarding claim 1, Ching teaches a method of forming a semiconductor device (see the entire document, specifically Fig. 1A+; [0006+], and as cited below), comprising:
selectively etching a superlattice structure ({110, 120}; Figs. 8A-8D in view of Fig. 1A, 2A; [0027-0028, 0017-0018]) on a substrate (105; Figs. 8A-8D in view of Fig. 1A; [0017, 0028]), the superlattice structure ({110, 120}; Figs. 8A-8D in view of Fig. 1A, 2A; [0027-0028, 0017-0018]) comprising a plurality of semiconductor material layers and a corresponding plurality of release layers alternatingly arranged in a plurality of stacked pairs, to remove each of the plurality of release layers ({110}; Figs. 8A-8D in view of Fig. 1A, 2A; [0027-0028, 0017-0018]) to form a plurality of voids ({310}; Figs. 8A-8D in view of Fig. 1A, 2A; [0027-0028, 0017-0018]) in the superlattice structure, the plurality of semiconductor material layers ({120}; Figs. 8A-8D in view of Fig. 1A, 2A; [0027-0028, 0017-0018]) extending between an epitaxial source region ({210}; Figs. 8A-8D in view of Fig. 5A, 6A; [0023]) and an epitaxial drain region ({210}; Figs. 8A-8D in view of Fig. 5A, 6A; [0023]), the epitaxial source region ({210}; Figs. 8A-8D in view of Fig. 5A, 6A; [0023]) and the epitaxial drain region ({210}; Figs. 8A-8D in view of Fig. 5A, 6A; [0023]) substantially free of defects; and
forming a self-aligned dielectric material ({370, 380, 390}; Figs. 9A-9D in view of Fig. 1A, 2A; [0031-0033]) in each of the plurality of voids ({310}; Figs. 8A-8D in view of Fig. 1A, 2A; [0027-0028, 0017-0018]) on a sidewall of the epitaxial source region ({210}; Figs. 9A-9D in view of Fig. 5A, 6A; [0023]) and on a sidewall of the epitaxial drain region ({210}; Figs. 9A-9D in view of Fig. 5A, 6A; [0023]) .
Regarding claim 2, Ching teaches all of the features of claim 1.
Ching further teaches wherein self-aligned dielectric material ({370, 380, 390}; Figs. 9A-9D in view of Fig. 1A, 2A; [0031-0033]) comprises a low-K dielectric material (see [0032]).
Regarding claim 5, Ching teaches all of the features of claim 1.
Ching further teaches wherein the self-aligned dielectric material ({370, 380, 390}; Figs. 9A-9D in view of Fig. 11C; [0043]) has a thickness in a range of from 3 nm to 15 nm (see [0043]; distance between layers 120 is 4 nanometers to about 10 nanometers).
Regarding claim 7, Ching teaches all of the features of claim 1.
Ching further teaches wherein forming the self-aligned dielectric material ({370, 380, 390}; Figs. 9A-9D in view of Fig. 1A, 2A; [0031-0033]) comprises a flowable CVD and ALD process (see [0029]).
Regarding claim 8, Ching teaches all of the features of claim 1.
Ching further comprising forming the epitaxial source region ({210}; Figs. 8A-8D in view of Fig. 7A-7D; [0023]) adjacent a first end of the superlattice structure and the epitaxial drain region ({210}; Figs. 8A-8D in view of Fig. 7A-7D; [0023]) adjacent a second opposing end of the superlattice structure prior to selectively etching the release layers.
Regarding claim 10, Ching teaches all of the features of claim 1.
Ching further teaches wherein the plurality of semiconductor material layers ({120}; Figs. 8A-8D in view of Fig. 1A, 2A; [0027-0028, 0017-0018]) comprise silicon (Si) (see [0017]), and wherein the plurality of release layers ({110}; Figs. 8A-8D in view of Fig. 1A, 2A; [0027-0028, 0017-0018]) comprise silicon germanium (SiGe) (see [0017]).
Regarding claim 11, Ching teaches all of the features of claim 1.
Ching further teaches wherein the method is performed in a processing chamber without breaking vacuum (see [0029]).
Regarding claim 12, Ching teaches all of the features of claim 1.
Ching further comprising forming a replacement gate ({510}; Figs. 11A-11D; [0035]) in the plurality of voids adjacent to the self-aligned dielectric material ({370, 380, 390}; Figs. 9A-9D in view of Fig. 11C; [0043]).
Regarding claim 13, Ching teaches all of the features of claim 12.
Ching further teaches wherein the replacement gate comprises ({510}; Figs. 11A-11D; [0035]; metal gate 510 includes a work function metal layer) one or more of a high-K dielectric material, an oxide layer, and a work function material.
Regarding claim 14, Ching teaches all of the features of claim 1.
Ching further comprising forming a gate electrode ({510}; Figs. 11A-11D; [0035]) on a top surface of the superlattice structure.
Regarding claim 15, Ching teaches all of the features of claim 14.
Ching further teaches wherein the gate electrode ({510}; Figs. 11A-11D; [0035]; metal gate 510 includes a work function metal layer) comprises one or more of a high-K dielectric material, a work function material, and a conductive material
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
3. Claims 3-4 are rejected under 35 U.S.C.103 as being unpatentable over Ching et al. (US 20230369458 A1; hereinafter Ching), in view of Ching et al. (US 20170278865 A1; hereinafter Ching ‘865).
Regarding claim 3, Ching teaches all of the features of claim 2.
Ching further teaches wherein the low-K dielectric material ({370, 380, 390}; Figs. 9A-9D in view of Fig. 1A, 2A; [0031-0033]) comprises one of more of (see below for “silicon carbooxynitride (SiCON), silicon oxynitride (SiON), silicon nitride (SiN), silicon carbide (SiC), and the like”).
As noted above, Ching does not expressly disclose “wherein the low-K dielectric material ({370, 380, 390}; Figs. 9A-9D in view of Fig. 1A, 2A; [0031-0033]) comprises one of more of silicon carbooxynitride (SiCON), silicon oxynitride (SiON), silicon nitride (SiN), silicon carbide (SiC), and the like”.
However, in the analogous art, Ching ‘865 teaches a semiconductor device ([Abstract]), wherein (Fig. 1+; [0006+]) spacers (280; Fig. 11; [0031]) contain silicon carbon oxynitride (SiCON).
It would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to modify the spacer material of Ching in view of the spacer material of Ching ‘865, and thereby, modified Ching’s (by Ching ‘865) method will have wherein the low-K dielectric material ({370, 380, 390}; Figs. 9A-9D in view of Fig. 1A, 2A; [0031-0033]) comprises one of more of silicon carbooxynitride (SiCON), silicon oxynitride (SiON), silicon nitride (SiN), silicon carbide (SiC), and the like (in view of Ching ‘865 [0031]; silicon carbon oxynitride (SiCON)) .
The ordinary artisan would have been motivated to modify Ching in the manner set forth above, at least, because this inclusion provides a silicon carbon oxynitride (Ching ‘865 [0031]), where silicon carbon oxynitride is well-known low-k dielectric material has a high thermal stability and resistance to oxidation, which helps increase the reliability of the device.
Regarding claim 4, Ching teaches all of the features of claim 3.
Ching further teaches wherein the low-K dielectric material comprises one of more of silicon carbooxynitride (SiCON) (in view of Ching ‘865 [0031]; silicon carbon oxynitride (SiCON)).
4. Claim 6 is rejected under 35 U.S.C.103 as being unpatentable over Ching et al. (US 20230369458 A1; hereinafter Ching), in view of the following statement.
Regarding claim 6, Ching teaches all of the features of claim 5.
Ching further teaches wherein the self-aligned dielectric material ({370, 380, 390}; Figs. 9A-9D in view of Fig. 11C; [0043]) has a thickness (see below for “in a range of from 2 nm to 6 nm”).
While Ching does not expressly teach wherein the self-aligned dielectric material has a thickness in a range of from 2 nm to 10 nm, some if its values fall within the claim range of a thickness in a range of from 2 nm to 10 nm, in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. See MPEP 2144.05, I.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to enable using “distance 570 is measured from the boundaries of the wires 120. In some embodiments, the distance 570 is in a range between about 4 nanometers and about 10 nanometers” ([0043]), as disclosed in prior art Ching, to arrive at the recited limitation of wherein the self-aligned dielectric material ({370, 380, 390}; Figs. 9A-9D in view of Fig. 11C; [0043]) has a thickness in a range of from 2 nm to 6 nm
(see [0043]; where some of the values from a thickness range between about 4 nanometers and about 10 nanometers, specifically 4 nm – 6 nm, are within the claimed thickness range; see MPEP § 2144.05.I).
5. Claim 9 is rejected under 35 U.S.C.103 as being unpatentable over Ching et al. (US 20230369458 A1; hereinafter Ching), in view of Bomberger et al. (US 20230197716 A1; hereinafter Bomberger).
Regarding claim 9, Ching teaches all of the features of claim 9.
Ching further teaches forming (see below for “a liner layer on”) the epitaxial source region ({210}; Figs. 8A-8D in view of Fig. 5A, 6A; [0023]) and on the epitaxial drain region ({210}; Figs. 8A-8D in view of Fig. 5A, 6A; [0023]), (see below for “the liner layer comprising boron (B) doped epitaxial silicon or arsenic (As) doped epitaxial silicon”).
As noted above, Ching does not expressly disclose ”forming a liner layer on the epitaxial source region and on the epitaxial drain region, the liner layer comprising boron (B) doped epitaxial silicon or arsenic (As) doped epitaxial silicon
However, in the analogous art, Bomberger teaches a method includes forming a fin structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers ([Abstract]), wherein (Fig. 1+; [0006+]) source/drain liners (215; Figs. 2D, 2H, 3, 4, [0043, 0077]) may be provided on the fins (206) in the source/drain trenches (217), where (215; Figs. 2D, 2H, 3, 4, [0043, 0077]) lines a source/drain structure ({280a, 280b}; [0077]). The source/drain liners (215; Fig. 2D; [0043]) may include a boron-doped epitaxial material, such as a boron doped SiGe material for a PMOS transistor.
It would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Bomberger’s doped liner layer into Ching’s method, and thereby, modified Ching’s (by Lin) method will have a liner layer (in view of Bomberger 215; Figs. 2D, 2H, 3, 4, [0043, 0077]) on the epitaxial source region ({210}; Figs. 8A-8D in view of Fig. 5A, 6A; [0023]) and on the epitaxial drain region ({210}; Figs. 8A-8D in view of Fig. 5A, 6A; [0023]), the liner layer (in view of Bomberger 215; Figs. 2D, 2H, 3, 4, [0043, 0077]) comprising boron (B) doped epitaxial silicon or arsenic (As) doped epitaxial silicon .
The ordinary artisan would have been motivated to modify Ching in the manner set forth above, at least, because this inclusion provides source/drain liners that include a boron-doped epitaxial material, such as a boron doped SiGe material (Bomberger [0043-0044]), where a feature of a material for the liners is to withstand temperatures, such as anneal temperatures, associated with gate structure formation, which helps protect devices layers.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Omar Mojaddedi whose telephone number is 313-446-6582. The examiner can normally be reached on Monday – Friday, 8:00 a.m. to 4:00 p.m..
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/OMAR F MOJADDEDI/Examiner, Art Unit 2898
Prosecution Insights