Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Elections/Restrictions
Applicant’s election without traverse of invention I (Claims 1-17) in the reply filed on 07/20/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 06/10/2025, 12/08/2025 and 06/12/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 16-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “generally” in claim 16 is a relative term which renders the claim indefinite. The term “generally” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Specifically, claim 16, line 8 recites the limitation “the bottom wall is generally free of the conductive material”. It is difficult to determine whether or not the conductive material contacts the bottom wall of the feature, and the proportion of the conductive material disposing on the bottom wall. Thus, claim 12 is indefinite under 35 U.S.C. 112(b) for indefiniteness. For the examination’s purpose, examiner has interpreted said limitation to mean “the bottom wall is free of the conductive material”.
Claim 17 is indefinite by virtue of its dependency on claim 16.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-5 and 7-13 are rejected under 35 U.S.C. 103 as being unpatentable over US20100210105A1; Baek et al.; (hereinafter “Baek”) in view of US20210242082A1; Maniscalco et al.; (hereinafter “Maniscalco”).
Regarding Claim 1, Baek teaches a method of forming an advanced memory device ([0003-0004]), comprising:
forming a dielectric material layer (#160, Figure 2) over a first sidewall, a second sidewall, and a bottom wall, of one or more features (#150), wherein the first sidewall is spaced apart from the second sidewall and the bottom wall is disposed between the first sidewall and the second sidewall (Figure 2, trench #150 comprises bottom wall between opposing sidewalls);
depositing a liner material (#170) directly on the dielectric material layer (#160) on the first sidewall, the second sidewall, and the bottom wall;
selectively depositing a conductive material on a remaining portion of the liner material (Figure 6, [0032], conductive layer #195 is selectively deposited on a remaining portion of barrier layer #170/#175).
Baek does not explicitly teach removing at least a portion of the liner material from the bottom wall.
However, Maniscalco teaches a method of forming interconnect structure in semiconductor device ([0004-0005]), comprising removing at least a portion of liner material from the bottom wall (Figure 3C, [0057-0058], liner #120 is removed from bottom surface of recess #108).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Baek with the teaching of Maniscalco in order to reduce via resistance for interconnect structures according to Maniscalco, [0057].
Regarding Claim 2, Baek in view of Maniscalco teaches the method as described in claim 1, wherein Baek further teaches forming the liner material (#170, Figure 2) is deposited conformally on the first sidewall and the second sidewall (sidewalls of trench #150).
Regarding Claim 3, Baek in view of Maniscalco teaches the method as described in claim 1, wherein Baek further teaches the liner material is deposited by an atomic layer deposition process, a chemical vapor deposition process, or a combination thereof ([0028], barrier #170 is deposited by CVD or ALD).
Regarding Claim 4, Baek in view of Maniscalco teaches the method as described in claim 1, wherein Baek further teaches the conductive material is deposited utilizing a selective atomic layer deposition process, a selective chemical vapor deposition process, or a combination thereof ([0032], conductive #195 is selectively deposited by such as ALD).
Regarding Claim 5, Baek in view of Maniscalco teaches the method as described in claim 1, wherein Baek further teaches the conductive material is only deposited over the liner material ([0032], conductive #195 forms only on barrier layer #175).
Regarding Claim 7, Baek in view of Maniscalco teaches the method as described in claim 1, wherein Baek further teaches recessing the liner material (Figures 3-4, barrier layer #170/#175 is recessed).
Regarding Claim 8, Baek in view of Maniscalco teaches the method as described in claim 7, wherein Baek further teaches the conductive material is recessed with the liner material, or is selectively deposited on the remaining portion of the liner material after recessing the liner material ([0033], conductive #195 on barrier #175 can be further recessed).
Regarding Claim 9, Baek in view of Maniscalco teaches the method as described in claim 1, wherein Baek further teaches filling the one or more features with a sacrificial material after depositing the liner material (Figure 3, [0029], sacrificial layer #180 is deposited on barrier layer #170).
Regarding Claim 10, Baek in view of Maniscalco teaches the method as described in claim 9.
Baek does not explicitly teach recessing the liner material is conducted prior to filling the one or more features.
However, Maniscalco teaches recessing the liner material is conducted prior to filling the one or more features (Figures 3C-D, [0058-0059], liner #120 is recessed prior to filling recess #108 with conductive material #242).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Baek with the teaching of Maniscalco for reason set forth in rejection of claim 1.
Regarding Claim 11, Baek in view of Maniscalco teaches the method as described in claim 9, wherein Baek further teaches the liner material is recessed simultaneously or sequentially with the sacrificial material (Figures 3-4, barrier #170/175 is recessed with sacrificial layer #180).
Regarding Claim 12, Baek in view of Maniscalco teaches the method as described in claim 9, wherein Baek further teaches the liner material comprises titanium nitride, titanium silicon nitride, titanium aluminide, titanium aluminum nitride, polycrystalline silicon, amorphous silicon, molybdenum nitride, molybdenum silicide, titanium, ruthenium, tungsten, molybdenum, tantalum nitride, tungsten nitride, tungsten silicide, tungsten carbon nitride, tungsten silicon nitride, niobium nitride, titanium aluminum nitride, titanium silicon nitride, tantalum silicon nitride, ruthenium titanium nitride, lanthanum nitride, or a combination thereof ([0028], barrier #170 comprises such as TiN).
Regarding Claim 13, Baek in view of Maniscalco teaches the method as described in claim 9, wherein Baek further teaches the conductive material comprises titanium nitride, titanium silicon nitride, polycrystalline silicon, molybdenum nitride, molybdenum silicide, titanium, tantalum, ruthenium, tungsten, molybdenum, platinum, nickel, cobalt, tantalum nitride, tungsten nitride, niobium nitride, titanium aluminide, titanium aluminum nitride, titanium silicide, titanium silicon nitride, tantalum silicide, tantalum silicon nitride, ruthenium titanium nitride, nickel silicide, cobalt silicide, iridium oxide, ruthenium oxide or a combination thereof, and combinations thereof ([0032], conductive #195 comprises such as W or Mo).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Baek in view of Maniscalco, and further in view of US2024035587A1; Nian et al.; (hereinafter “Nian”).
Regarding Claim 6, Baek in view of Maniscalco teaches the method as described in claim 1.
Baek in view of Maniscalco does not explicitly teach depositing the liner material, removing the portion of the liner material, and depositing the conductive material are conducted without a vacuum break.
However, Nian teaches a semiconductor memory device ([0029]), comprising depositing the liner material, removing the portion of the liner material, and depositing the conductive material (see rejection of claim 1 regarding deposition and removal of materials) are conducted without a vacuum break ([0027], processing tools #102-112, including such as deposition tool #102 and etching tool #108, [0016], can be used to process semiconductor device without vacuum break).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Baek in view of Maniscalco with the teaching of Nian in order to prevent or reduce humidity or other contaminations to the devices during processes according to Nian, [0026] or [0079].
Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Baek in view of Maniscalco, and further in view of US20220352201A1; Hinoue et al.; (hereinafter “Hinoue”)
Regarding Claim 14, Baek in view of Maniscalco teaches the method as described in claim 13, wherein Baek further teaches the conductive material comprises molybdenum, tungsten, or a combination thereof ([0032], conductive #195 comprises such as W or Mo).
Baek in view of Maniscalco does not explicitly teach the conductive material is selectively deposited by contacting the liner material with one or more precursors of molybdenum, tungsten, or combinations thereof.
However, Hinoue teaches a 3D memory device ([0005]), comprising a conductive material is selectively deposited by contacting the liner material with one or more precursors of molybdenum, tungsten, or combinations thereof ([0139], liner material contacts metal-containing precursor gas of tungsten to induce deposition of metal in memory openings).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Baek in view of Maniscalco with the teaching of Hinoue by known methods to yield predictable results (deposition of metal layer contacting liner layer in memory opening). See MPEP 2143(I)(A).
Regarding Claim 15 (currently amended), Baek in view of Maniscalco and Hinoue teaches the method as described in claim 14, wherein Baek further teaches the one or more precursors of molybdenum comprises molybdenum chloride, molybdenum oxychloride, a molybdenum based metal organic compound, or a combination thereof, and/or the one or more precursors of tungsten comprises tungsten chloride (see rejection of claim 14, [0139] of Hinoue, precursor gas of tungsten comprises tungsten pentachloride).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over US20250056792A1; Lee et al.; (hereinafter “Lee”) in view of Baek.
Regarding Claim 16, Lee teaches an advanced memory array ([0006]), comprising:
a feature having a first sidewall opposed to a second sidewall, and a bottom wall (Figure 2 or Figure 26, channel trench #CH_T includes opposing sidewalls and bottom wall);
a dielectric material layer formed over the first sidewall, second sidewall, and the bottom wall (Figure 2, insulating pattern #175 and insulating layer #171 form over sidewalls and bottom wall of trench #CH_T);
a liner (#CH_IF, [0175]) formed over the dielectric material layer on the first sidewall, second sidewall and the bottom wall (#CH_IF forms over sidewalls and bottom wall of trench #CH_T); and
a conductive material (#WLb) formed over the liner (#CH_IF) on the first sidewall and the second sidewall, wherein the bottom wall is generally free of the conductive material (bottom wall of trench #CH_T does not contact word line #WLb), and wherein the conductive material formed over the liner on the first sidewall is electrically separated from the conductive material formed over the liner on the second sidewall (word lines #WL1 and #WL2 are electrically isolated);
wherein the conductive material comprises molybdenum, ruthenium, tungsten, titanium nitride, titanium, or a combination thereof ([0092] or [0033]).
Lee does not explicitly teach the liner comprises titanium nitride, titanium silicon nitride, amorphous silicon, polycrystalline silicon, molybdenum nitride, molybdenum silicide, or a combination thereof.
However, Baek teaches a liner comprises titanium nitride, titanium silicon nitride, amorphous silicon, polycrystalline silicon, molybdenum nitride, molybdenum silicide, or a combination thereof ([0028], barrier #170 comprises TiN).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Lee with the teaching of Baek, as it would be a simple substitution of one known element (liner material of Lee) for another (liner material of Baek) to obtain predictable results. See MPEP 2143(I)(B).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Baek, and further in view of CN110943033A; (hereinafter “033”); see attached machine translation.
Regarding Claim 17 (currently amended), Lee in view of Baek teaches the advanced memory array as described in claim 16.
Lee in view of Baek does not explicitly teach an aspect ratio of the feature, having a width measured from the liner, is less than or about 20:1.
However, 033 teaches a trench structure in DRAM ([0005]), wherein an aspect ratio of a feature, having a width measured from the liner, is less than or about 20:1 ([0054-0055] or [0072], aspect ratio of trench #12 can be such as 15:1).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Lee in view of Baek with the teaching of 033 in order to increase cross-sectional area of active region and subsequent process window, and reduce contact resistance according to 033, [0043].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US20240422987A1 – Figures 3-4
US20070051994A1 – Figure 4B, [0027]
US20220029015A1 – Figures 2C-J
US20230088149A1 – Figures 8A-B, [0046]
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/TIEN TRAN/Examiner, Art Unit 2812
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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