Prosecution Insights
Last updated: August 17, 2026
Application No. 18/438,499

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Non-Final OA §102§103
Filed
Feb 11, 2024
Examiner
MAZUMDER, DIDARUL A
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
NANYA TECHNOLOGY Corporation
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
638 granted / 738 resolved
+18.4% vs TC avg
Moderate +8% lift
Without
With
+8.4%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
35 currently pending
Career history
764
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
58.5%
+18.5% vs TC avg
§102
25.1%
-14.9% vs TC avg
§112
11.8%
-28.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 738 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION This action is responsive to the application No. 18/438,499 filed on June 22, 2026. Information Disclosure Statement 3. Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered. Specification 4. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: “Semiconductor Device Comprising Hybrid Bonding Using Magnetic Material”. Election/Restrictions 5. Applicant’s election without traverse of claims 1-7, drawn to device, in the reply filed on 06/22/2026 is acknowledged. 6. Claims 8-17 are cancelled from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected method device claims, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 06/22/2026. Claim Objections 7. Claim 1 is objected to because of the following informalities: In the following, the claims should be recited to fix grammatical error, and/or smooth flow of claim languages/phrases: 1. (Currently Amended) A semiconductor device, comprising: a first semiconductor wafer comprising: a first substrate; a first metallization layer disposed on a top surface of the first substrate; a first dielectric layer disposed on the first metallization layer; a first magnetic structure embedded in the first dielectric layer; and a first metal pad embedded in the first dielectric layer, wherein the first metal pad connects with a first interconnect structure in the first metallization layer; and a second semiconductor wafer disposed on the first semiconductor wafer, wherein the second semiconductor wafer comprises: a second substrate; a second metallization layer disposed on a top surface of the second substrate; a second dielectric layer disposed on the second metallization layer; a second magnetic structure embedded in the second dielectric layer; and a second metal pad embedded in the second dielectric layer, wherein the second metal pad connects with a second interconnect structure in the first metallization layer; wherein the first magnetic structure is aligned with and in direct contact with the second magnetic structure, and a top surface of the first dielectric layer is in direct contact with a top surface of the second dielectric layer. Appropriate corrections are needed. Claim Rejections - 35 USC § 102 8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 9. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 10. Claims 1, 3-7 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Huang et al. (US 2018/0033773 A1). Regarding independent claim 1, Huang et al. teaches a semiconductor device, comprising (Fig. 4C): a first semiconductor wafer (20 called second die, para [0050] which is an inherent part of the semiconductor wafer 200, see Fig. 2A) comprising: a first substrate (20, see Fig. 2A); a first metallization layer (250 interconnect structure, para [0051]) disposed on a top surface of the first substrate (20); a first dielectric layer (218, para [0028]) disposed on the first metallization layer (250); a first magnetic structure (220, para [0051]) embedded in the first dielectric layer (218); and a first metal pad (216, para [0028]) embedded in the first dielectric layer (218), wherein the first metal pad (216) connects with a first interconnect structure (212/215) in the first metallization layer (250); and a second semiconductor wafer (10 called first die, para [0050] which is an inherent part of the semiconductor wafer 100, see Fig. 2A) disposed on the first semiconductor wafer (20), wherein the second semiconductor wafer (10) comprises: a second substrate (10, see Fig. 2A); a second metallization layer (150, para [0017]) disposed on a top surface of the second substrate (10); a second dielectric layer (118, para [0019]) disposed on the second metallization layer (150); a second magnetic structure (120, para [0051]) embedded in the second dielectric layer (118); and a second metal pad (116, para [0017]) embedded in the second dielectric layer (118), wherein the second metal pad (116) connects with a second interconnect structure (112/115) in the first metallization layer (150); wherein the first magnetic structure (220) is aligned with and in direct contact with the second magnetic structure (120), and a top surface of the first dielectric layer (218) is in direct contact with a top surface of the second dielectric layer (118). Regarding claim 3, Huang et al. teaches wherein (Fig. 4C), the first magnetic structure (220) and the second magnetic structure (120) have opposite polarities (see para [0031]). Regarding claim 4, Huang et al. teaches wherein (Fig. 4C), further comprising: a package structure (30, para [0049]) covering the first semiconductor wafer (20) and the second semiconductor wafer (10). Regarding claim 5, Huang et al. teaches wherein (Fig. 4C), the second semiconductor wafer (100: 10, see Fig. 2A) comprises a conductive via (330, para [0052]) extending from a bottom surface of the second substrate (10) to the second interconnect structure (112/115) of the second metallization layer (150). Regarding claim 6, Huang et al. teaches wherein (Fig. 4C), a top surface of the first metal pad (216) is coplanar with a top surface of the first magnetic structure (220) and a top surface of the second metal pad (116) is coplanar with a top surface of the second magnetic structure (120). Regarding claim 7, Huang et al. teaches wherein (Fig. 4C), the first metal pad (216) is aligned with and in direct contact with the second metal pad (116). Claim Rejections - 35 USC § 103 11. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 12. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 13. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 14. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: a. Determining the scope and contents of the prior art. b. Ascertaining the differences between the prior art and the claims at issue. c. Resolving the level of ordinary skill in the pertinent art. d. Considering objective evidence present in the application indicating obviousness or non-obviousness. 15. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 2018/0033773 A1) as applied to claim 1 above, and further in view of in view of Liao (US 2025/0006669 A1). Regarding claim 2, Huang et al. teach all of the limitations of claim 1 from which this claim depends. Huang et al. teaches wherein (Fig. 4C), the first magnetic structure (220) and the second magnetic structure (120) comprise a material (iron (Fe), cobalt (Co), nickel (Ni), para [0021]) selected from the group consisting of iron oxides, iron-cobalt alloy, iron-nickel alloy, iron-aluminum alloy or combinations thereof (para [0021]). Huang et al. is silent to explicitly disclose wherein, the first magnetic structure and the second magnetic structure comprise a material selected from the group consisting of iron oxides, iron-cobalt alloy, iron-nickel alloy, iron-aluminum alloy or combinations thereof. Liao teaches wherein (Fig. 1K), the first magnetic structure (402, para [0046]) comprises a material selected from the group consisting of iron oxides, iron-cobalt alloy, iron-nickel alloy, iron-aluminum alloy or combinations thereof (para [0046]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Liao, and modify the magnetic material of metal element of Huang et al., into metal alloy or oxide, in order to achieve higher mechanical/thermal stability, magnetic property control and superior bonding process. Examiner’s Note 16. Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182. Examiner has cited particular paragraphs and/or columns/lines in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention. Conclusion 17. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIDARUL MAZUMDER whose telephone number is (571)272-8823. The examiner can normally be reached M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. 18. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DIDARUL A MAZUMDER/Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Feb 11, 2024
Application Filed
Jul 14, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12708039
3DIC Package and Method Forming the Same
3y 7m to grant Granted Aug 11, 2026
Patent 12707784
DISPLAY MODULE
2y 10m to grant Granted Aug 11, 2026
Patent 12707788
OPTOELECTRONIC SEMICONDUCTOR COMPONENT AND PANEL
2y 8m to grant Granted Aug 11, 2026
Patent 12702041
SEMICONDUCTOR DEVICE
2y 10m to grant Granted Aug 04, 2026
Patent 12696815
SEMICONDUCTOR PACKAGE AND A METHOD OF MANUFACTURING THE SAME
2y 10m to grant Granted Jul 28, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
95%
With Interview (+8.4%)
2y 1m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 738 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month