DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1-20 are pending in the application and are currently being examined. No claims have been amended. No claims have been canceled. No new claims have been added.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 2/12/2024 are being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 8-9, 11, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Thomas et al. (US 2022/0199620 A1, hereafter Thomas) in view of Huang et al. (US 2021/0257258 A1, hereafter Huang).
Regarding claim 1, Thomas teaches in Fig. 5 a method for forming a gate stack of a transistor, comprising:
forming a high-k dielectric layer (315 around 215A, [0042]);
forming a p-dipole dopant source layer (515, [0066], which may be formed of an aluminum oxide, [0047]) over the high-k dielectric layer (315);
performing a thermal drive-in process (step 525, [0067]) that drives aluminum from the p-dipole dopant source layer (515) into the high-k dielectric layer (315); and
after removing the p-dipole dopant source layer (515) (step 525, [0067]), forming at least one electrically conductive gate layer (510A, [0068]) over the high-k dielectric layer (315).
Thomas does not teach the p-dipole dopant source layer includes an aluminum layer (the doping layer of Thomas is an aluminum alloy [0047]). However, Huang states that metals or alloys can be used to form metal doping layers [0033] meaning an aluminum layer from Huang is an obvious variant of the aluminum oxide layer of Thomas.
Regarding claim 8, Thomas in view of Huang teach the method of claim 1. Thomas further teaches in Fig. 5 wherein the transistor (151, [0025]) includes a stack of channel layers (215A, [0066]),
wherein the forming of the high-k dielectric layer (315, [0042]) includes forming the high-k dielectric layer (315) around each channel layer (215A) of the stack of channel layers (215A) (The high-k dielectric layers are disposed around each individual channel layer).
Regarding claim 9, Thomas in view of Huang teach the method of claim 1. While Thomas in view of Huang does not explicitly teach the p-dipole dopant source layer is a first p-dipole dopant source layer and the thermal drive-in process is a first thermal drive-in process; and the method further comprises: forming a second p-dipole dopant source layer over the high-k dielectric layer, and performing a second thermal drive-in process that drives aluminum from the second p-dipole dopant source layer into the high-k dielectric layer, one of ordinary skill in the art would find a second p-dipole dopant source layer and subsequent second thermal drive-in process to be a duplication of parts (See MPEP 2104.04). As the result from both thermal drive-in processes is the expected increase of aluminum dopants in the high-k dielectric layer, one of ordinary skill in the art would be motivated to add a second p-dipole dopant source layer and subsequent second thermal drive-in process to Thomas in order to get the expected result of an increased dopant concentration to a desired amount depending on the requirements of the device.
Regarding claim 11, in Fig. 5 Thomas teaches a method comprising:
forming a first interfacial layer (315' over 215A, [0075]) over a first channel member (215A, [0066]) and a second interfacial layer (315' over 215B, [0075]) over a second channel member (215B, [0066]);
forming a first gate dielectric (315 over 215A, [0042]) over the first interfacial layer (315' over 215A, [0075]) and a second gate dielectric (315 over 215B, [0042]) over the second interfacial layer (315' over 215B, [0075]);
performing a dipole engineering process including a dipole loop (ALD cycles in [0106]), wherein the dipole loop includes:
performing an atomic layer deposition (ALD) process ([0059 and 0106]) to form [a dopant] layer (515, [0066]) over the first gate dielectric (315 over 215A) but not the second gate dielectric (315 over 215B) (in Fig. 5, dipole dopant layer is deposited on each gate dielectric layer but removed from the second gate dielectric),
performing a thermal drive-in process (done in step 525, [0067]) that drives aluminum from [the dopant] layer (515) into the first gate dielectric (315 over 215A), and
removing the [dopant layer] (515, done in step 525, [0067]); and
forming a gate electrode (510A, [0068], done in step 530, [0068]) over the first gate dielectric (315 over 215A) and the second gate dielectric (315 over 215B).
Thomas does not teach the dopant layer includes an aluminum layer (the doping layer of Thomas is an aluminum alloy [0047]). However, Huang states that metals or alloys can be used to form metal doping layers [0033] meaning an aluminum layer from Huang is an obvious variant of the aluminum oxide layer of Thomas.
Thomas is silent on the drive-in process increasing an aluminum concentration in the first gate dielectric by less than about 5%. However, one of ordinary skill in the art would be able to reach this doping increase through routine optimization. The doping concentration is not described as a critical limitation, so one of ordinary skill would know to adjust the parameters of the drive in process to get to a dopant concentration increase of less than about 5% (See MPEP 2144.05).
Regarding claim 18, in Fig. 5 Thomas teaches a method comprising:
forming a device including a first gate region (151, [0025]) and a second gate region (152, [0025]),
wherein the first gate (151) region includes a first channel member (215A, [0066]), a first gate dielectric (315 over 215A, [0042]) over the first channel member (215A), and a first gate electrode layer (510A, [0068]) over the first gate dielectric (315 over 215A),
wherein the second gate region (152) includes a second channel member (215B, [0066]), a second gate dielectric (315 over 215B, [0042]) over the second channel member (215B), and a second gate electrode layer (510B, [0068]) over the second gate dielectric (315 over 215B),
wherein the first gate dielectric (315 over 215A) and the second gate dielectric (315 over 215A) include different concentrations of [a dopant] (Thomas only dopes the first gate dielectric with the p-type dopant, meaning the second gate dielectric has none of said dopant driven-in), and
wherein the forming of the device includes:
forming [a dopant] layer (515, [0066]) over the first gate dielectric (315 over 215A) but not the second gate dielectric (315 over 215A),
performing an annealing process (step 525, [0067]) that drives [the dopant] from the [dopant] layer into the first gate dielectric (315 around 214A),
removing the [dopant] layer (step 525, [0067]), and
forming the first gate electrode layer (510A) over the first gate dielectric (315 around 214A) and the second gate electrode layer (510B) over the second gate dielectric (315 around 214A) (done in steps 530, 535, and 540, [0068]).
Thomas does not teach the dopant layer being an aluminum layer (the doping layer of Thomas is an aluminum alloy [0047]). However, Huang states that metals or alloys can be used to form metal doping layers [0033] meaning an aluminum layer from Huang is an obvious variant of the aluminum oxide layer of Thomas.
Thomas in view of Huang is silent on the drive-in process increasing an aluminum concentration in the first gate dielectric by less than about 5%. However, one of ordinary skill in the art would be able to reach this doping increase through routine optimization. The doping concentration is not described as a critical limitation, so one of ordinary skill would know to adjust the parameters of the drive in process to get to a dopant concentration increase of less than about 5% (See MPEP 2144.05).
Claim(s) 2-6 and 13-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Thomas in view of Huang, and further in view of More et al. (US 2022/0052045 A1, hereafter More).
Regarding claim 2, Thomas in view of Huang teach the method of claim 1. Thomas in view of Huang fail to teach the p-dipole dopant source layer further includes an aluminum oxide layer. However, More teaches a similar method in Fig. 14A and 14B in which a dopant layer (104, [0054]) is deposited on a gate dielectric (102A, [0053]) for the purposes of doping the gate dielectric [0054]. More further teaches that while 104 is shown to be a single layer, multiple layers may be formed as said doping layer [0055]. This would make a multi-layered dipole dopant layer an obvious variant of the single layer. Thomas further discloses that the doping layer may contain aluminum oxide [0047]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the dipole dopant layer of Thomas in view of Huang to be multi-layered layer as taught by More and further including an aluminum oxide layer as taught by Thomas in order to get the expected result of a dual layered dipole dopant layer for doping the gate dielectric layer with aluminum.
Regarding claim 3, Thomas in view of Huang in further view of More teach the method of claim 2. Thomas in view of Huang in further view of More do not explicitly teach wherein the forming of the p-dipole dopant source layer includes: forming the aluminum layer over the high-k dielectric layer; and forming the aluminum oxide layer over the aluminum layer. However, as Thomas in view of Huang in further view of More teach a dual layered dipole dopant layer for the purposes of doping the gate dielectric layer with aluminum, one of ordinary skill in the art would find it obvious to try forming the aluminum layer over the high-k dielectric layer; and forming the aluminum oxide layer over the aluminum layer as there are limited orderings of these layers (here, only 2 options). One of ordinary skill in the art would have a reasonable expectation of success as both the aluminum layer and the aluminum oxide layer are known dopant layers, leading to an end result of a doped gate dielectric layer (See MPEP 2143.02).
Regarding claim 4, Thomas in view of Huang in further view of More teach the method of claim 2. Thomas in view of Huang in further view of More do not explicitly teach wherein the forming of the p-dipole dopant source layer includes: forming the aluminum oxide layer over the high-k dielectric layer; and forming the aluminum layer over the aluminum oxide layer. However, as Thomas in view of Huang in further view of More teach a dual layered dipole dopant layer for the purposes of doping the gate dielectric layer with aluminum, one of ordinary skill in the art would find it obvious to try forming the aluminum oxide layer over the high-k dielectric layer; and forming the aluminum layer over the aluminum oxide layer as there are limited orderings of these layers (here, only 2 options). One of ordinary skill in the art would have a reasonable expectation of success as both the aluminum layer and the aluminum oxide layer are known dopant layers, leading to an end result of a doped gate dielectric layer (See MPEP 2143.02).
Regarding claim 5, Thomas in view of Huang teach the method of claim 1. Thomas in view of Huang fail to teach the p-dipole dopant source layer further includes an aluminum nitride layer. However, More teaches a similar method in Fig. 14A and 14B in which a dopant layer (104, [0054]) is deposited on a gate dielectric (102A, [0053]) for the purposes of doping the gate dielectric [0054]. More further teaches that while 104 is shown to be a single layer, multiple layers may be formed as said doping layer [0055]. This would make a multi-layered dipole dopant layer an obvious variant of the single layer. Thomas further discloses that the doping layer may contain aluminum nitride [0047]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the dipole dopant layer of Thomas in view of Huang to be multi-layered layer as taught by More and further including an aluminum nitride layer as taught by Thomas in order to get the expected result of a dual layered dipole dopant layer for doping the gate dielectric layer with aluminum.
Regarding claim 6, Thomas in view of Huang teach the method of claim 1. Thomas in view of Huang fail to teach the p-dipole dopant source layer further includes an aluminum oxide layer and an aluminum nitride layer. However, More teaches a similar method in Fig. 14A and 14B in which a dopant layer (104, [0054]) is deposited on a gate dielectric (102A, [0053]) for the purposes of doping the gate dielectric [0054]. More further teaches that while 104 is shown to be a single layer, multiple layers may be formed as said doping layer [0055]. This would make a multi-layered dipole dopant layer an obvious variant of the single layer. Thomas further discloses that aluminum oxide and aluminum nitride are suitable materials for a dopant layer [0047]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the dipole dopant layer of Thomas in view of Huang to be multi-layered layer as taught by More and further including an aluminum oxide layer and an aluminum nitride layer as taught by Thomas in order to get the expected result of a multi-layered dipole dopant layer for doping the gate dielectric layer with aluminum.
Regarding claim 13, Thomas in view of Huang teach the method of claim 11. Thomas in view of Huang fail to teach the ALD process is a first ALD process; and the dipole loop further includes:
performing a second ALD process to form an aluminum oxide layer over the first gate dielectric, and wherein the performing of the thermal drive-in process further drives aluminum from the aluminum oxide layer into the first gate dielectric. Thomas does however, teach the ALD process may include multiple cycles ([0060]).
More teaches a similar method in Fig. 14A and 14B in which a dopant layer (104, [0054]) is deposited by ALD on a gate dielectric (102A, [0053]) for the purposes of doping the gate dielectric [0054]. More further teaches that while 104 is shown to be a single layer, multiple layers may be formed as said doping layer [0055]. This would make a multi-layered dipole dopant layer an obvious variant of the single layer prior to the thermal drive-in step. Thomas further discloses that the doping layer may contain aluminum oxide [0047]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the ALD process to form the dipole loop of Thomas in view of Huang to form a multi-layered layered dipole layer as taught by More and further including an aluminum oxide layer as taught by Thomas in order to get the expected result of a dual layered dipole dopant layer for doping the gate dielectric layer with aluminum.
Regarding claim 14, Thomas in view of Huang teach the method of claim 11. Thomas in view of Huang fail to teach the ALD process is a first ALD process; and the dipole loop further includes:
performing a second ALD process to form an aluminum nitride layer over the first gate dielectric, and wherein the performing of the thermal drive-in process further drives aluminum from the aluminum nitride layer into the first gate dielectric. Thomas does however, teach the ALD process may include multiple cycles ([0060]).
More teaches a similar method in Fig. 14A and 14B in which a dopant layer (104, [0054]) is deposited by ALD on a gate dielectric (102A, [0053]) for the purposes of doping the gate dielectric [0054]. More further teaches that while 104 is shown to be a single layer, multiple layers may be formed as said doping layer [0055]. This would make a multi-layered dipole dopant layer an obvious variant of the single layer prior to the thermal drive-in step. Thomas further discloses that the doping layer may contain aluminum nitride [0047]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the ALD process to form the dipole loop of Thomas in view of Huang to form a multi-layered layered dipole layer as taught by More and further including an aluminum nitride layer as taught by Thomas in order to get the expected result of a dual layered dipole dopant layer for doping the gate dielectric layer with aluminum.
Regarding claim 15, Thomas in view of Huang teach the method of claim 11. Thomas in view of Huang fail to teach the ALD process is a first ALD process; and the dipole loop further includes: performing a second ALD process to form an aluminum oxide layer over the first gate dielectric, performing a third ALD process to form an aluminum nitride layer over the first gate dielectric, and wherein the performing of the thermal drive-in process further drives aluminum from the aluminum oxide layer and the aluminum nitride layer into the first gate dielectric. Thomas does however, teach the ALD process may include multiple cycles ([0060]).
More teaches a similar method in Fig. 14A and 14B in which a dopant layer (104, [0054]) is deposited by ALD on a gate dielectric (102A, [0053]) for the purposes of doping the gate dielectric [0054]. More further teaches that while 104 is shown to be a single layer, multiple layers may be formed as said doping layer [0055]. This would make a multi-layered dipole dopant layer an obvious variant of the single layer prior to the thermal drive-in step. Thomas further discloses that the doping layer may contain aluminum oxide and aluminum nitride [0047]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the ALD process to form the dipole loop of Thomas in view of Huang to form a multi-layered layered dipole layer as taught by More and further including an aluminum oxide layer and an aluminum nitride layer as taught by Thomas in order to get the expected result of a dual layered dipole dopant layer for doping the gate dielectric layer with aluminum.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Thomas in view of Huang, and further in view of Cheng (US 2021/0384313 A1).
Regarding claim 10, Thomas in view of Huang teach the method of claim 1. Thomas further teaches in Fig. 5 the high-k dielectric layer is a first high-k dielectric layer. Thomas in view of Huang fail to teach after the removing of the p-dipole dopant source layer and before the forming of the at least one electrically conductive gate layer over the high-k dielectric layer, forming a second high-k dielectric layer over the first high-k dielectric layer. However, Cheng teaches a similar method in which a first high-k dielectric is doped (222, [0024]) and subsequently covered by a second high-k dielectric layer (230, [0024]). This second dielectric layer is formed in order to prevent gate leakage ([0024] of Cheng). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the gate dielectric of Thomas in view of Huang to include a second, undoped high-k dielectric layer over the first, doped high-k dielectric material.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Thomas in view of Huang in view of Yoshikawa (US 2019/0148402 A1).
Regarding claim 7, Thomas in view of Huang teach the method of claim 1. Thomas in view of Huang are silent on wherein the forming of the p-dipole dopant source layer includes forming the aluminum layer using an aluminum chloride (AlCl3) precursor and a trimethylaluminum (TMA) precursor.
However, Yoshikawa teaches a deposition method of forming an aluminum layer in which the precursors can be a combination of both aluminum chloride ([0063]) and trimethylaluminum ([0063]). These precursors are used to form an aluminum layer ([0032]). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the ALD process of Thomas in view of Huang in order to use aluminum chloride and trimethylaluminum as precursors to form an aluminum layer.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Thomas in view of Huang in view of Yoshikawa and in view of Liu et al. (US 2024/0087899 A1, hereafter Liu).
Regarding claim 12, Thomas in view of Huang teach the method of claim 11. Thomas teaches further teaches the method includes repeating the cycle of the ALD process until the aluminum layer has a target thickness (Thomas states 1 or more cycles may be performed to deposit 1-2 nm of dipole shifter material, [0059]).
However, Thomas in view of Huang are silent on a cycle of the ALD process includes:
flowing a first deposition gas into a process chamber, wherein the first deposition gas includes aluminum chloride (AlCl3),
flowing a second deposition gas into the process chamber, wherein the second deposition gas includes trimethylaluminum (TMA).
However, Yoshikawa teaches a deposition method of forming an aluminum layer in which the precursors can be a combination of both aluminum chloride ([0063]) and trimethylaluminum ([0063]). These precursors are used to form an aluminum layer ([0032]). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the ALD process of Thomas in view of Huang in order to use aluminum chloride and trimethylaluminum as precursors to form an aluminum layer.
Thomas in view of Huang and in further view of Yoshikawa fail to teach a purging step between cycles. However, Liu teaches an ALD process in which a purge gas is introduced into the processing chamber in order to remove residual reactive compounds or byproducts from the reaction zone ([0026]). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the ALD process taught by Thomas in view of Huang and in further view of Yoshikawa in order to get the expected result of removing unwanted material from the processing region.
Claim(s) 16-17 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Thomas in view of Huang in view of Chen et al. (US 2022/0320337 A1, hereafter Chen).
Regarding claim 16, Thomas in view of Huang teach the method of claim 11.
Thomas in view of Huang teach the dipole loop (ALD cycles in [0106]) is a first dipole loop, the aluminum layer (315 around 215A, [0042]) is a first aluminum layer, the ALD process (ALD cycles in [0106]) is a first ALD process, and the thermal drive-in process (done in step 525, [0067]) is a first thermal drive-in process.
Thomas in view of Huang fail to teach wherein:
the dipole engineering process further includes a second dipole loop including:
performing a second ALD process to form a second aluminum layer over the second gate dielectric,
performing a second thermal drive-in process that drives aluminum from the second aluminum layer into the second gate dielectric, thereby increasing an aluminum concentration in the second gate dielectric by less than about 5%, and
removing the second aluminum layer.
However, Chen teaches a similar process in Figs. 17-25 in which the dipole engineering process includes a second dipole loop including:
performing a second ALD process (shown in Figs. 20-21) to form a second [dopant] layer (179, [0062]) over the second gate dielectric (157, [0056], around 106b, [0023]),
performing a second thermal drive-in process (shown in Figs. 21-22) that drives [dopants] from the second [dopant] layer (179) into the second gate dielectric (157 around 106b), and
removing the second [dipole] layer (described in [0063]).
Thomas in view of Huang in further view of Chen is silent on the drive-in process increasing an aluminum concentration in the second gate dielectric by less than about 5%. However, one of ordinary skill in the art would be able to reach this doping increase through routine optimization. The doping concentration is not described as a critical limitation, so one of ordinary skill would know to adjust the parameters of the drive in process to get to a dopant concentration increase of less than about 5% (See MPEP 2144.05). While Chen teaches the dopants to possibly be aluminum oxide and not just aluminum in the dipole layer ([0059]), Chen further teaches that any suitable dopant may be used ([0059]), and Thomas in view of Huang teach aluminum to be a suitable dopant, specifically in P-type devices ([0047] of Thomas). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the ALD process of Thomas in view of Huang to include a second ALD process and second thermal drive-in process in order to have differences in concentrations of dopants in the gate electrodes to allow for improved device density ([0026] of Chen).
Regarding claim 17, Thomas in view of Huang in further view of Chen teach the method of claim 16, wherein:
the performing of the second ALD process further forms the second aluminum layer over the first gate dielectric; and
the performing of the second thermal drive-in process further drives aluminum from the second aluminum layer into the first gate dielectric.
Thomas in view of Huang in further view of Chen is silent on the drive-in process increasing an aluminum concentration in the first gate dielectric by less than about 5%. However, one of ordinary skill in the art would be able to reach this doping increase through routine optimization. The doping concentration is not described as a critical limitation, so one of ordinary skill would know to adjust the parameters of the drive in process to get to a dopant concentration increase of less than about 5% (See MPEP 2144.05).
Regarding claim 19, Thomas in view of Huang teach the method of claim 18. Thomas in view of Huang teach wherein the aluminum layer (315 around 215A, [0042]) is a first aluminum layer, and the annealing process (done in step 525, [0067]) is a first annealing process.
Thomas in view of Huang fail to teach wherein the forming of the device further includes:
forming a second aluminum layer over the first gate dielectric and the second gate dielectric,
performing a second annealing process that drives aluminum from the second aluminum layer into the first gate dielectric and the second gate dielectric, thereby increasing an atomic concentration of aluminum in the second gate dielectric and the atomic concentration of aluminum in the first gate dielectric by less than about 5%, and
removing the second aluminum layer.
However, Chen teaches a similar process in Figs. 17-25 including:
forming a second [dopant] layer (179, [0062]) over the first gate dielectric (157, [0056], around 106c, [0023]) and the second gate dielectric (157, [0056], around 106b, [0023]),
performing a second annealing process (shown in Figs. 21-22, [0063]) that drives [dopants] from the second [dopant] layer (179) into the first gate dielectric (157 around 106c) and the second gate dielectric (157 around 106b), and
removing the second [dipole] layer (described in [0063]).
Thomas in view of Huang in further view of Chen is silent on the drive-in process increasing an aluminum concentration in the second gate dielectric by less than about 5%. However, one of ordinary skill in the art would be able to reach this doping increase through routine optimization. The doping concentration is not described as a critical limitation, so one of ordinary skill would know to adjust the parameters of the drive in process to get to a dopant concentration increase of less than about 5% (See MPEP 2144.05). While Chen teaches the dopants to possibly be aluminum oxide and not just aluminum in the dipole layer ([0059]), Chen further teaches that any suitable dopant may be used ([0059]), and Thomas in view of Huang teach aluminum to be a suitable dopant, specifically in P-type devices ([0047] of Thomas). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the ALD process of Thomas in view of Huang to include a second ALD process and second thermal drive-in process in order to have differences in concentrations of dopants in the gate electrodes to allow for improved device density ([0026] of Chen).
Regarding claim 20, Thomas in view of Huang in further view of Chen teach the method of claim 18. Figs. 17-25 of Chen further teach a third gate region (in area including channel 106a, [0023]);
wherein the third gate region includes a third channel member (106a, [0023]), a third gate dielectric (157, [0056], around 106a, [0023]) over the third channel member (106a);
wherein the first gate dielectric (157, [0056], around 106c, [0023]), the second gate dielectric (157, [0056], around 106b, [0023]), and the third gate dielectric (157 around 106a) include different concentrations of aluminum (As each gate dielectric undergo different anneal processes, they inherently will include different concentrations of aluminum); and
the forming of the device further includes:
forming a third aluminum layer (181, [0064]) over the first gate dielectric (157 around 106c), the second gate dielectric (157 around 106b), and the third gate dielectric (157 around 106a),
performing a third annealing process (shown in Figs. 23-24, [0064]) that drives aluminum from the third aluminum layer into the first gate dielectric (157 around 106a), the second gate dielectric (157 around 106a), and the third gate dielectric (157 around 106a), and
removing the third aluminum layer (described in [0064]).
While Thomas in view of Huang in further view of Chen fail to teach a third gate electrode layer over the third gate dielectric, one of ordinary skill in the art would find it obvious to make a third gate electrode, as Thomas in view of Huang teach a second gate electrode, rendering a third to be a duplication of parts (See MPEP 2104.04).
Conclusion
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/SAMMANTHA K SALAZ/Examiner, Art Unit 2892
/ERIC W JONES/Primary Examiner, Art Unit 2892
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