DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a NON-FINAL OFFICE ACTION in response to the Amendment/ Remarks filed 11/18/2025. Claim 4 is cancelled.
Claims 1-3 and 5-21 are pending in the Application, of which Claims 1, 10 and 18 are independent.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/16/2025 has been entered.
Response to Arguments
Applicant's arguments Amendment/ Remarks filed 08/25/2025, with respect to the rejection of Claims 1-3 and 5-21 under 35 U.S.C. 102(a)(1) as being anticipated by Russell et al. (Pub. No. US 20100128541), have been fully considered but they are not persuasive, as set forth in the present office action .
Drawings Objections is withdrawn in view of Applicant’s Remarks/ Arguments.
Claim rejections under 35 USC 112b is withdrawn due to Applicant’s amendment to the Claims.
Applicant argues that Russell fails to disclose "a write assist configuration circuit configured to shift configuration data through a shift register of the first write assist enable circuit and the second write assist enable circuit to designate the second write driver circuit for activation," as recited in the claims. Instead, Russell appears to describe a system using threshold voltage registers, comparators, and “AND” gates to apply write assist voltage. Russell is simply silent to any shifting of configuration data through a shift register of multiple write assist enable circuits to activate specific write driver circuits corresponding to certain operational characteristics, as claimed.
In response to Applicant arguments, the Examiner notes that using threshold voltage registers, comparators, and “AND” gates for implementing the write assist bit (WRITE ASSIST BIT) in Russell is a design choice, in lieu of using a write assist configuration circuit configured to shift configuration data, as claimed.
For example, in para. [0027] FIG. 2, Russell discloses, in the case of a write operation to a selected cache line (row) that includes defective cells, an asserted write assist bit (WRITE ASSIST BIT) is provided to the input of AND logic gate 49. Write assist enable signal WRITE ASSIST EN is asserted, and array VDD multiplexer logic 50 causes transistor 56 to become conductive and provide power supply voltage WRITE VDD to the supply voltage terminals of the memory cells of the selected cache line, thus increasing the write margin of the selected cache line. Note that in one embodiment, WRITE VDD may be a fixed voltage of about 0.7 volts, READ VDD may be a fixed voltage of about 1 volt, and VDD may be variable between about 1 volt and 0.75 volts.
Clearly, the asserted write assist bit (WRITE ASSIST BIT) in Russell is functionally equivalent to the write assist configuration circuit as Claimed, since the purpose of both designs is intended to repair defective cells by adjusting the WRITE VDD voltage.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 5-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Russell et al. (Pub. No. US 20100128541) Pub. Date: 2010-05-27.
Regarding independent Claims 1, 10 and 18, Russell discloses an integrated circuit and method having a memory with configurable read/write operations, comprising:
a memory array comprising …., the second memory cell having an operational characteristic different than that of the first memory cell; FIG. 2, [0021] Memory array 16 includes a plurality of memory cells, corresponding to “first and a second memory cell” such as for example, memory cells 22-30, organized in rows and columns. A row includes a word line and all of the memory cells coupled to the word line. For example, one row includes word line WL0 and memory cells 22, 23, and 24. A column includes a bit line, or bit line pair, and all of the memory cells coupled to the bit line, or bit line pair. For example, one column includes bit line pair BL0/BLB0 and memory cells 22, 25, and 28.
“the second memory cell having an operational characteristic different” [0025] Read assist VTH register 40 is for storing one or more bits that correspond to a read threshold voltage. The read assist threshold voltage is the voltage at which the first read failure occurs due to a marginal bitcell. Write assist VTH register 42 is for storing one or more bits that correspond to a write assist threshold voltage. The write assist threshold voltage is the voltage at which the first write failure occurs due to a marginal bitcell. For voltages above the write assist threshold voltage, write assist is disabled to save power since all bitcells can be reliably written.
a first write driver circuit configured to write first data to the first memory cell, and a second write driver circuit configured to write second data to the second memory cell; [0027] FIG. 2 Generally, in the case where a row of memory array 16 stores a single cache line and array power supply multiplexer 51 is coupled to all of the columns of the array, the corresponding read or write assist bit field is checked to see if the selected cache line requires a power supply voltage modification while being accessed. If the corresponding read or write assist bit field indicates that modification is necessary, the read or write assist bit is provided to array VDD multiplexer logic 50 and the appropriate assist power supply voltage is provided to the cache line. More specifically, in the case of a write operation to a selected cache line (row) that includes defective cells, an asserted write assist bit (WRITE ASSIST BIT) is provided to the input of AND logic gate 49. If the output of comparator 46 indicates that VID is less than or equal to write assist voltage threshold WRITE VTH, write assist enable signal WRITE ASSIST EN is asserted, and array VDD multiplexer logic 50 causes transistor 56 to become conductive and provide power supply voltage WRITE VDD to the supply voltage terminals of the memory cells of the selected cache line, thus increasing the write margin of the selected cache line.
a write assist configuration circuit configured to shift configuration data through a shift register …….., causing the second write assist enable circuit to configure the second write driver circuit to compensate for the operational characteristic of the second memory cell.
[0027] FIG. 2, More specifically, in the case of a write operation to a selected cache line (row) that includes defective cells, an asserted write assist bit (WRITE ASSIST BIT) is provided to the input of AND logic gate 49. If the output of comparator 46 indicates that VID is less than or equal to write assist voltage threshold WRITE VTH, write assist enable signal WRITE ASSIST EN is asserted, and array VDD multiplexer logic 50 causes transistor 56 to become conductive and provide power supply voltage WRITE VDD to the supply voltage terminals of the memory cells of the selected cache line, thus increasing the write margin of the selected cache line. Note that in one embodiment, WRITE VDD may be a fixed voltage of about 0.7 volts, READ VDD may be a fixed voltage of about 1 volt, and VDD may be variable between about 1 volt and 0.75 volts.
[0030] FIG. 4 illustrates a method 70 for operating a memory. At step 71 of method 70, a cache line is read. At decision step 72, it is determined if an error exists for a memory cell of the cache line. In the illustrated embodiment, error correction code (ECC) is used to detect the errors. Returning to decision step 74, if the error is not correctable by read assist, the NO path is taken to decision step 78 and it is determined if the error is correctable by write assist. If the error is correctable by write assist, the YES path is taken to step 79. At step 79 the write assist bit for the affected cache line entry in status array 32 is set. At step 80, it is determined if the write assist threshold WRITE VTH is less than VID. If the answer is no, the NO path is taken to step 84. If the write assist threshold WRITE VTH is less than VID, the YES path is taken to step 81 and the write assist threshold WRITE VTH is made equal to the current VID and the method continues to step 84.
Regarding independent Claims 2-3, 5, 6, 11-14, Russell discloses the write assist circuit is configured to operate at a first voltage to write the first data to the first memory cell and the second write circuit is configured to operate at a second voltage to write the second data to the second memory cell. [0027] FIG. 2 More specifically, in the case of a write operation to a selected cache line (row) that includes defective cells, an asserted write assist bit (WRITE ASSIST BIT) is provided to the input of AND logic gate 49. If the output of comparator 46 indicates that VID is less than or equal to write assist voltage threshold WRITE VTH, write assist enable signal WRITE ASSIST EN is asserted, and array VDD multiplexer logic 50 causes transistor 56 to become conductive and provide power supply voltage WRITE VDD to the supply voltage terminals of the memory cells of the selected cache line, thus increasing the write margin of the selected cache line. Note that in one embodiment, WRITE VDD may be a fixed voltage of about 0.7 volts, READ VDD may be a fixed voltage of about 1 volt, and VDD may be variable between about 1 volt and 0.75 volts. During a read operation to a selected cache line that includes defective cells, an asserted read assist bit (READ ASSIST BIT) is provided to the input of AND logic gate 48. If the output of comparator 44 indicates that VID is less than or equal to READ VTH, read assistance is needed, and array VDD multiplexer logic 50 causes transistor 54 to become conductive and provide power supply voltage READ VDD to the supply voltage terminals of the memory cells of the selected cache line, thus increasing the read margin of the selected cache line. Another embodiment may only use write assist bits and a write assist threshold voltage register. The use of read assist bits does not require the use of write assist bits and vice versa. The determination of which bits of array 16 are defective because of reduced read and/or write margins will be discussed below.
Regarding Claims 15-17, Russell discloses the memory cell having the defect; [0027] FIG. 2, During a read operation to a selected cache line that includes defective cells, an asserted read assist bit (READ ASSIST BIT) is provided to the input of AND logic gate 48. If the output of comparator 44 indicates that VID is less than or equal to READ VTH, read assistance is needed, and array VDD multiplexer logic 50 causes transistor 54 to become conductive and provide power supply voltage READ VDD to the supply voltage terminals of the memory cells of the selected cache line, thus increasing the read margin of the selected cache line. Another embodiment may only use write assist bits and a write assist threshold voltage register. The use of read assist bits does not require the use of write assist bits and vice versa. The determination of which bits of array 16 are defective because of reduced read and/or write margins will be discussed below.
Regarding Claim 7-9, 19-21, Russell discloses a register storing control data that indicates the first and second write circuit is to operate at the first and second voltage. [0024] Write assist VTH register 42 is for storing one or more bits that correspond to a write assist threshold voltage. The write assist threshold voltage is the voltage at which the first write failure occurs due to a marginal bitcell. For voltages above the write assist threshold voltage, write assist is disabled to save power since all bitcells can be reliably written. [0025] Read assist VTH register 40 is for storing one or more bits that correspond to a read threshold voltage. The read assist threshold voltage is the voltage at which the first read failure occurs due to a marginal bitcell. For voltages above the read assist threshold voltage, read assist is disabled to save power since all bitcells can be reliably read. However, for memory read accesses at or below the read assist threshold voltage, the read assist bits are enabled to determine which entries require read assistance since read failures can occur if read assist is not used at or below the read assist threshold voltage.
Prior Art References Cited
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See References Cited on PTO-892 form.
Kim et al. ((U.S. Patent No. 7,978,559) Referring to FIGS. 2 and 3, The write assist circuit 13 assists write operations to the memory cell 21. The write assist circuit 13 is not activated when a read operation from the memory cell 21 is performed, and is activated only when a write operation with respect to the memory cell 21 is performed. More particularly, the write assist circuit 13 includes a plurality of elements M4, M5, M6 connected in series between the power voltage source supplying the voltage VDD and the memory cell array 20.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARK FEATHERSTONE can be reached at (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: January 20, 2026
Non-Final Rejection 20260117
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV