DETAILED ACTION
Claims 1-20 are pending before the Office for review.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 4, 5, 7-8, 10-11, 13 and 15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim1-16 of U.S. Patent No. 11,935,746. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of pending application 18/439340 and US Patent 11.935,746 comprise overlapping subject matter wherein the claims of the pending application are rendered obvious by the issued patent.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 2, 4-5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over KONECNI et al (U.S. Patent Application Publication 2012/0129351) in view of LEE at al (U.S. Patent Application Publication 2010/0276789).
With regards to claim 1, Konecni discloses a method for forming a semiconductor device (200), comprising: forming a mask layer (206A) over a substrate (202), the mask layer (206A) having, as deposited, an internal stress, the internal stress having a first magnitude and a first direction (Figure 2A Paragraphs [0015], [0023]-[0027] discloses forming high stress layer 26 with a compressive strength); forming over the mask layer a stress-compensating layer (206B), the stress compensating layer having an internal stress having a second magnitude and having a second direction opposite to the first direction (Figure 2A Paragraphs [0015]-[0018], [0023]-[0027] discloses forming a low stress layer with a tensile strength).
Konecni does not explicitly disclose performing a thermal process on the mask layer and the stress-compensating layer, wherein after the thermal process, the internal stress of the mask layer has a third magnitude lower than the first magnitude and has the first direction.
Lee discloses a method of forming a semiconductor device comprising forming a hard mask layer having an internal stress and performing a thermal process to adjust the internal stress of the mask layer (Paragraphs [0010], [0015]-[0022] discloses depositing a first hardmask layer, 12, 22 having an initial tensile stress, and layers 13 and 23 have an opposite stress and performing a heat treatment to lower the stress value and change from tensile to compressive or compressive to tensile). As such Konecni as modified my Lee renders obvious performing a thermal process on the mask layer and the stress-compensating layer, wherein after the thermal process, the internal stress of the mask layer has a third magnitude lower than the first magnitude and has the first direction. (Paragraphs [0017]-[0025], Lee Paragraphs [0010], [0015]-[0022]).
It would have been prima facie obvious to one of ordinary skill in the art prior to the effective filing date of the invention to modify the method of Konecni to include thermal process as rendered by Lee because the reference of Lee discloses that such adjusting the stress prevents peeling of multiple layer hardmask with opposite stress during fabrication (Paragraph [0009]) and one of ordinary skill in the art prior to the effective filing date of the invention would have had a reasonable expectation of predictably achieving the desired mask layer using thermal process as rendered obvious by Lee. MPEP 2143D
With regards to claim 2, the modified teachings of Konecni renders obvious wherein the internal stress of the mask layer arises from at least one cause, the cause selected from the group consisting of a deposition process by which the mask layer was deposited (Konecni Paragraphs [0027], [0030] discloses internal stress can be adjusted by changing deposition conditions and levels of deposited stress increasing elements, adjusting deposition conditions).
With regards to claim 4, the modified teachings of Konecni renders obvious depositing a photoresist layer (208) on the stress compensating layer (206); photolithographically patterning the photoresist layer; and patterning the stress compensating layer through the patterned photoresist layer. (Konecni Paragraphs [0024]-[0027]).
With regards to claim 5, the modified teachings of Konecni renders obvious patterning the mask layer through the patterned stress compensating layer. (Konecni Paragraphs [0024]-[0027] discloses etching the mask layers 206A, B with resist pattern 208).
With regards to claim 7, the modified teachings of Konecni renders obvious wherein the step of performing a thermal process is performed before the step of depositing a photoresist layer. (Konecni Paragraphs [0024]-[0027] discloses forming the hardmask layers are formed to the desired stress levels Lee Paragraphs [0016]-[0022] discloses performing thermal process to adjust the stress). Selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results. MPEP 2144.04(IV)(C)
Claims 8 and 13 are ejected under 35 U.S.C. 103 as being unpatentable over KONECNI et al (U.S. Patent Application Publication 2012/0129351) in view of LEE at al (U.S. Patent Application Publication 2010/0276789), as applied to claims 1, 2, 4-5 and 7, in further view of NEMANI et al (U.S. Patent 8,153,348).
With regards to claim 8, Konecni discloses a method for forming a semiconductor device (200), comprising: forming a material layer (204) over a substrate (202); forming a mask layer (206A) over the material layer (204), the mask layer (206A) having, as deposited, an internal stress, the internal stress being either compressive or tensile (Figure 2A Paragraphs [0015], [0023]-[0027] discloses forming high stress layer 26 with a compressive strength); forming over the mask layer a stress-compensating layer (206B), the stress compensating layer having an internal stress that is opposite in direction of the internal stress of the mask layer (Figure 2A Paragraphs [0015]-[0018], [0023]-[0027] discloses forming a low stress layer with a tensile strength) wherein the stress compensating layer reduces the internal stress of the mask layer (Paragraph [0018] low stress layer may have low magnitude tensile stress to counteract effect of compressive stress in the high stress layer).
Konecni does not explicitly disclose where the mask layer comprises a material selected from the group consisting of silicon oxide, silicon nitride, silicon-oxy-nitride, a metal nitride and a metal oxide; performing a thermal process on the mask layer to further reduce the internal stress of the mask layer.
Lee discloses a method of forming a semiconductor device comprising forming a hard mask layer having an internal stress and performing a thermal process to adjust the internal stress of the mask layer (Paragraphs [0010], [0015]-[0022] discloses depositing a first hardmask layer, 12, 22 having an initial tensile stress, and layers 13 and 23 have an opposite stress and performing a heat treatment to lower the stress value and change from tensile to compressive or compressive to tensile). As such Konecni as modified my Lee renders obvious performing a thermal process on the mask layer and the stress-compensating layer, (Paragraphs [0017]-[0025], Lee Paragraphs [0010], [0015]-[0022]).
It would have been prima facie obvious to one of ordinary skill in the art prior to the effective filing date of the invention to modify the method of Konecni to include thermal process as rendered by Lee because the reference of Lee discloses that such adjusting the stress prevents peeling of multiple layer hardmask with opposite stress during fabrication (Paragraph [0009]) and one of ordinary skill in the art prior to the effective filing date of the invention would have had a reasonable expectation of predictably achieving the desired mask layer using thermal process as rendered obvious by Lee. MPEP 2143D
Nemani discloses a method of forming a semiconductor device comprising thermally treating a hardmask layer wherein the hard mask layer comprises silicon oxide and silicon oxy-nitride (Col. 14 lines 17-39) which renders obvious wherein the mask layer comprises a material selected from the group consisting of silicon oxide, silicon nitride, and silicon-oxynitride, a metal nitride and a metal oxide.
It would have been prima facie obvious to one of ordinary skill in the art prior to the effective filing date of the invention to further modify the modified teachings of Konecni to include the hardmask material as rendered obvious by Nemani because the reference of Nemani teaches that such hardmask eliminate the need for photoresist deposition and etching (Col. 3 lines 56-58) and one of ordinary skill in the art prior to the effective filing date of the invention would have had a reasonable expectation of predictably achieving the desired patterning using the hardmask as rendered obvious by Nemani. MPEP 2143D
With regards to claim 13, the modified teachings of Konecni renders obvious patterning the mask layer and the stress compensating layer using a photolithographic process. (Konecni Paragraphs [0024]-[0027] discloses etching the mask layers 206A, B with resist pattern 208).
Allowable Subject Matter
Claims 3, 6, 9,12, 14 and 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEPHANIE P. DUCLAIR whose telephone number is (571)270-5502. The examiner can normally be reached 9-6:30 M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Allen can be reached at 571-270-3176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/STEPHANIE P DUCLAIR/Primary Examiner, Art Unit 1713