Prosecution Insights
Last updated: October 01, 2026
Application No. 18/439,660

DISPLAY DEVICE

Non-Final OA §103
Filed
Feb 12, 2024
Priority
Jun 14, 2023 — RE 10-2023-0076411
Examiner
VALENZUELA, PATRICIA D
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Display Co., Ltd.
OA Round
2 (Non-Final)
90%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
652 granted / 722 resolved
+22.3% vs TC avg
Minimal +2% lift
Without
With
+2.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
82 currently pending
Career history
804
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
68.2%
+28.2% vs TC avg
§102
15.8%
-24.2% vs TC avg
§112
6.2%
-33.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 722 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bok(USPGPUB DOCUMENT: 2021/0200366, hereinafter Bok) in view of DominguezCastro (USPGPUB DOCUMENT: 2015/0358571, hereinafter DominguezCastro) and Lee (USPGPUB DOCUMENT: 2006/0044233, hereinafter Lee). Re claim 1 Bok discloses a display device comprising: a substrate(SUB) comprising: a display area(DA) comprising emission areas(RE/GE/BE), a non-emission area(NEA) as a separation region between the emission areas(RE/GE/BE), and light sensing areas(area of IRC)[1001] in parts of the non-emission area(NEA); and a non-display area(DA)(NDA) around the display area(DA); a circuit layer on the substrate(SUB); and an element layer on the circuit layer, and comprising: light emitting elements(LEL) in the emission areas(RE/GE/BE), respectively; and light sensing elements(IRC) in the light sensing areas(area of IRC)[1001], respectively, wherein the circuit layer comprises: light emitting pixel(510) drivers electrically connected to the light emitting elements(LEL), respectively; light sensing pixel electrically connected to the light sensing elements(IRC), respectively; data lines(Dj) electrically connected to the light emitting pixel(510) drivers; read-out line[1335]s(ROL) electrically connected to the light sensing pixel, and extending parallel to the data lines(Dj); Bok does not disclose first dummy lines(DE) extending in a first direction crossing the data lines(Dj), and comprising a first read-out line electrically connected to a first read-out line[1335] from among the read-out line[1335]s(ROL); and second dummy lines(DE) extending in a second direction parallel to the data lines(Dj) and crossing the first direction, and paired with the data lines(Dj), respectively, light sensing pixel drivers electrically connected to the light sensing elements(IRC), respectively; read-out line[1335]s(ROL) electrically connected to the light sensing pixel drivers, the second dummy lines(DE) comprising a first read-out connection line electrically connected to the first read-out bypass line. DominguezCastro discloses light sensing pixel drivers[0213 of DominguezCastro] , respectively; a first read-out connection line(SEL_PIX)[0240 of DominguezCastro] electrically connected to the first read-out bypass line(1110)[0134 of DominguezCastro]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of DominguezCastro to the teachings of Bok in order to have higher data reading-out rates [0002, DominguezCastro].2 In doing so, light sensing pixel drivers[0213 of DominguezCastro] electrically connected to the light sensing elements(IRC), respectively; read-out line[1335]s(ROL) electrically connected to the light sensing pixel drivers[0213 of DominguezCastro], the second dummy lines(DE) comprising a first read-out connection line(SEL_PIX)[0240 of DominguezCastro] electrically connected to the first read-out bypass line(1110)[0134 of DominguezCastro]. Bok and DominguezCastro does not disclose first dummy lines(DE) extending in a first direction crossing the data lines(Dj), and comprising a first read-out line electrically connected to a first read-out line[1335] from among the read-out line[1335]s(ROL); and second dummy lines(DE) extending in a second direction parallel to the data lines(Dj) and crossing the first direction, and paired with the data lines(Dj), respectively, Lee disclose first dummy lines(DE)(Dr1/Dw/Dr2) extending in a first direction crossing the data lines(Dj)(D1/D2/D3), and comprising a first read-out line electrically connected to a first read-out line from among the read-out lines(ROL) (162/164 of Lee); read-out lines(ROL) (162/164) electrically connected to the light sensing pixel drivers, It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Lee to the teachings of Bok in order to have higher data reading-out rates [0003, Lee].2 In doing so, the second dummy lines(DE) (Dr1/Dw/Dr2) comprising a first read-out connection line electrically connected to the first read-out bypass line(1110)[0134 of DominguezCastro]. Re claim 2 Bok and DominguezCastro and Lee disclose the display device of claim 1, wherein the data lines(Dj), the read-out line[1335]s(ROL), and the second dummy lines(DE) are located on at least one insulating layer covering the first dummy lines(DE). Re claim 3 Bok and DominguezCastro and Lee disclose the display device of claim 2, further comprising a scanning driving circuit configured to collect light sensing signals from the light sensing elements(IRC) through the light sensing pixel drivers [0213 of DominguezCastro] and the read-out line[1335]s(ROL), wherein the circuit layer further comprises read-out transmission lines in the non-display area(DA)(NDA), and electrically connected between the read-out line[1335]s(ROL) and the scanning driving circuit, and wherein from among the read-out transmission lines, a first read-out transmission line configured to transmit a signal of the first read-out line[1335] is electrically connected to the first read-out line[1335] through the first read-out connection line(SEL_PIX)[0240 of DominguezCastro] and the first read-out bypass line(1110)[0134 of DominguezCastro]. Re claim 4 Bok and DominguezCastro and Lee disclose the display device of claim 3, wherein a bypass area(area B in rows 1-10 in Fig 12)[0134 of DominguezCastro] on one side of the display area(DA) comprises: a central bypass middle area; a first bypass side area parallel to the bypass middle area in the first direction, and in contact with the non-display area(DA)(NDA); a second bypass side area between the bypass middle area and the first bypass side area; and a third bypass side area between the first bypass side area and the second bypass side area, wherein the data lines(Dj) comprise: a first data line in the first bypass side area; a second data line and a third data line in the second bypass side area; and a fourth data line in the third bypass side area, wherein the first dummy lines(DE) further comprise a first data bypass line electrically connected to the first data line, and a second data bypass line electrically connected to the fourth data line, wherein the second dummy lines(DE) further comprise: a first data connection line paired with the second data line, and electrically connected to the first data bypass line; and a second data connection line paired with the third data line, and electrically connected to the second data bypass line, and wherein the first read-out connection line(SEL_PIX)[0240 of DominguezCastro] is paired with the fourth data line. Re claim 5 Bok and DominguezCastro and Lee disclose the display device of claim 4, further comprising a display driving circuit configured to transmit data signals for the light emitting pixel(510) drivers to the data lines(Dj), wherein the circuit layer further comprises data transmission lines in the non-display area(DA)(NDA), and electrically connected between the data lines(Dj) and the display driving circuit, and wherein from among the data transmission lines: a first data transmission line configured to transmit a data signal of the first data line is electrically connected to the first data line through the first data bypass line and the first data connection line; a second data transmission line configured to transmit a data signal of the second data line is directly electrically connected to the second data line; a third data transmission line configured to transmit a data signal of the third data line is directly electrically connected to the third data line; and a fourth data transmission line configured to transmit a data signal of the fourth data line is electrically connected to the first data line through the second data bypass line and the second data connection line. Re claim 6 Bok and DominguezCastro and Lee disclose the display device of claim 5, wherein the substrate(SUB) comprises a main region comprising the display area(DA) and the non-display area(DA)(NDA), and a sub-region protruding from one side of the main region in the second direction, wherein the display driving circuit is on the sub-region of the substrate(SUB), wherein the scanning driving circuit is on a display circuit board connected to the sub-region of the substrate(SUB), wherein the data transmission lines are clustered in a part of the non-display area(DA)(NDA) parallel to the second bypass side area, and wherein the read-out transmission lines are clustered in another part of the non-display area(DA)(NDA) adjacent to the third bypass side area. Re claim 7 Bok and DominguezCastro and Lee disclose the display device of claim 6, wherein the first read-out line[1335] is located in the second bypass side area, wherein the read-out line[1335]s(ROL) further comprise a second read-out line[1335] in the third bypass side area, and wherein from among the read-out transmission lines, a second read-out transmission line configured to transmit a signal of the second read-out line[1335] is directly electrically connected to the second read-out line[1335]. Re claim 8 Bok and DominguezCastro and Lee disclose the display device of claim 7, wherein the first read-out bypass line(1110)[0134 of DominguezCastro] comprises a plurality of first read-out bypass line(1110)[0134 of DominguezCastro]s, wherein the first data bypass line comprises a plurality of first data bypass lines, wherein the second data bypass line comprises a plurality of second data bypass lines, and wherein at least one of the first read-out bypass line(1110)[0134 of DominguezCastro]s is located between the first data bypass lines in the second direction, or between the second data bypass lines in the second direction. Re claim 9 Bok and DominguezCastro and Lee disclose the display device of claim 7, wherein each of the first bypass side area, the second bypass side area, and the third bypass side area comprises: an adjacent region in contact with the non-display area(DA)(NDA) in the second direction; and a separation region as a remaining region excluding the adjacent region, wherein the first read-out bypass line(1110)[0134 of DominguezCastro] is located in the adjacent region of each of the first bypass side area, the second bypass side area, and the third bypass side area, and wherein the first data bypass line and the second data bypass line are located in the separation region of each of the first bypass side area, the second bypass side area, and the third bypass side area. Re claim 10 Bok and DominguezCastro and Lee disclose the display device of claim 7, wherein the bypass area(area B in rows 1-10 in Fig 12)[0134 of DominguezCastro] of the display area(DA) further comprises a fourth bypass side area between the first bypass side area and the third bypass side area, wherein the data lines(Dj) further comprise a fifth data line in the fourth bypass side area, wherein the read-out line[1335]s(ROL) further comprise a third read-out line[1335] in the first bypass side area, and a fourth read-out line[1335] in the fourth bypass side area, wherein the first dummy lines(DE) further comprise a second read-out bypass line(1110)[0134 of DominguezCastro] electrically connected to the third read-out line[1335], wherein the second dummy lines(DE) further comprise a second read-out connection line(SEL_PIX)[0240 of DominguezCastro] paired with the fifth data line, and electrically connected to the second read-out bypass line(1110)[0134 of DominguezCastro], and wherein from among the read-out transmission lines: a third read-out transmission line configured to transmit a signal of the third read-out line[1335] is electrically connected to the third read-out line[1335] through the second read-out connection line(SEL_PIX)[0240 of DominguezCastro] and the second read-out bypass line(1110)[0134 of DominguezCastro]; and a fourth read-out transmission line configured to transmit a signal of the fourth read-out line[1335] is directly electrically connected to the fourth read-out line[1335]. Re claim 11 Bok and DominguezCastro and Lee disclose the display device of claim 10, wherein the data lines(Dj) further comprise a sixth data line in the second bypass side area, wherein the first dummy lines(DE) further comprise a third data bypass line electrically connected to the fifth data line, and wherein the second dummy lines(DE) further comprise a third data connection line paired with the sixth data line, and electrically connected to the third data bypass line. Re claim 12 Bok and DominguezCastro and Lee disclose the display device of claim 10, wherein the fourth bypass side area comprises an adjacent region in contact with the non-display area(DA)(NDA) in the second direction, and a separation region as a remaining region excluding the adjacent region, wherein the first read-out bypass line(1110)[0134 of DominguezCastro] is located in the adjacent region of each of the second bypass side area and the third bypass side area, wherein the second read-out bypass line(1110)[0134 of DominguezCastro] is located in the adjacent region of each of the first bypass side area and the fourth bypass side area, and wherein the first data bypass line and the second data bypass line are located in the separation region of each of the first bypass side area, the second bypass side area, the third bypass side area, and the fourth bypass side area. Re claim 13 Bok and DominguezCastro and Lee disclose the display device of claim 12, wherein the circuit layer further comprises a first power supply line and a second power supply line in the non-display area(DA)(NDA), and configured to transmit a first power and a second power, respectively, for driving the light emitting elements(LEL), wherein the first dummy lines(DE) further comprise first auxiliary lines electrically connected to the second power supply line, and wherein the second dummy lines(DE) further comprise second auxiliary lines electrically connected to the first auxiliary lines and the second power supply line. Re claim 14 Bok and DominguezCastro and Lee disclose the display device of claim 13, wherein each of the first bypass side area, the second bypass side area, the third bypass side area, and the fourth bypass side area further comprises a buffer region between the adjacent region and the separation region, and wherein the first auxiliary lines are located in the buffer region of each of the first bypass side area, the second bypass side area, the third bypass side area, and the fourth bypass side area. Re claim 15 Bok and DominguezCastro and Lee disclose the display device of claim 7, wherein the circuit layer further comprises: a first power supply line and a second power supply line in the non-display area(DA)(NDA), and configured to transmit a first power and a second power, respectively, for driving the light emitting elements(LEL); and a first power line electrically connected between the light emitting pixel(510) drivers and the first power supply line, wherein one of the light emitting elements(LEL) is electrically connected between one of the light emitting pixel(510) drivers and the second power, wherein one of the light sensing elements(IRC) is electrically connected between an element output node of one of the light sensing pixel drivers [0213 of DominguezCastro] and the second power, wherein the one of the light emitting pixel(510) drivers comprises: a first transistor configured to generate a driving current for driving the one of the light emitting elements(LEL); a second transistor electrically connected between one of the data lines(Dj) and a first electrode of the first transistor; a third transistor electrically connected between a gate electrode of the first transistor and a second electrode of the first transistor; a fourth transistor electrically connected between a first initialization power line configured to transmit a first initialization power and the gate electrode of the first transistor; a fifth transistor electrically connected between the first power line and the first electrode of the first transistor; a sixth transistor electrically connected between the second electrode of the first transistor and the one of the light emitting elements(LEL); a seventh transistor electrically connected between a second initialization power line configured to transmit a second initialization power and the one of the light emitting elements(LEL); and an eighth transistor electrically connected between a bias power line configured to transmit a bias power and the first electrode of the first transistor, and wherein the one of the light sensing pixel drivers [0213 of DominguezCastro] comprises: a ninth transistor configured to be turned on according to a voltage level of the element output node; a tenth transistor electrically connected between a reset voltage line configured to transmit a reset voltage and the element output node; and an eleventh transistor electrically connected between one of the read-out line[1335]s(ROL) and the ninth transistor. Re claim 16 Bok discloses a display device comprising: a substrate(SUB) comprising: a display area(DA) comprising emission areas(RE/GE/BE), a non-emission area(NEA) as a separation region between the emission areas(RE/GE/BE), and light sensing areas(area of IRC)[1001] in parts of the non-emission area(NEA); and a non-display area(DA)(NDA) around the display area(DA); a circuit layer on the substrate(SUB); and an element layer on the circuit layer, and comprising: light emitting elements(LEL) in the emission areas(RE/GE/BE), respectively; and light sensing elements(IRC) in the light sensing areas(area of IRC)[1001], respectively, , and wherein the circuit layer comprises: light emitting pixel(510) electrically connected to the light emitting elements(LEL), respectively; light sensing pixel electrically connected to the light sensing elements(IRC); data lines(Dj) electrically connected to the light emitting pixel(510); read-out line[1335]s(ROL) electrically connected to the light sensing pixel, and extending parallel to the data lines(Dj); Bok does not disclose light sensing pixel drivers electrically connected to the light sensing elements(IRC), wherein a bypass area on one side of the display area(DA) comprises: a central bypass middle area; a first bypass side area parallel to the bypass middle area in a first direction, and in contact with the non-display area(DA)(NDA); a second bypass side area between the bypass middle area and the first bypass side area; and a third bypass side area between the first bypass side area and the second bypass side area; a first data bypass line extending in the first direction crossing the data lines(Dj), and electrically connected to a first data line in the first bypass side area from among the data lines(Dj); a first read-out bypass line extending in the first direction crossing the data lines(Dj), and electrically connected to a first read-out line[1335] from among the read-out line[1335]s(ROL); a first data connection line extending in a second direction parallel to the data lines(Dj) and crossing the first direction, the first data connection line paired with a second data line in the second bypass side area from among the data lines(Dj), and electrically connected to the first data bypass line; and a first read-out connection line extending in the second direction, and electrically connected to the first read-out bypass line. DominguezCastro discloses light sensing pixel drivers [0213 of DominguezCastro] electrically connected to the light sensing elements(IRC), wherein a bypass area(area B in rows 1-10 in Fig 12)[0134 of DominguezCastro] comprises: a central bypass middle area; a first bypass side area parallel to the bypass middle area in a first direction,; a second bypass side area between the bypass middle area and the first bypass side area; and a third bypass side area between the first bypass side area and the second bypass side area(area B in rows 1-10 in Fig 12)[0134 of DominguezCastro];; a first data connection line(SEL_PIX)[0240 of DominguezCastro] and a first read-out connection line(SEL_PIX)[0240 of DominguezCastro] extending in the second direction, and electrically connected to the first read-out bypass line(1110)[0134 of DominguezCastro]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of DominguezCastro to the teachings of Bok in order to have higher data reading-out rates [0002, DominguezCastro]. In doing so, light sensing pixel drivers [0213 of DominguezCastro] electrically connected to the light sensing elements(IRC), wherein a bypass area(area B in rows 1-10 in Fig 12)[0134 of DominguezCastro] on one side of the display area(DA) comprises: a central bypass middle area; a first bypass side area parallel to the bypass middle area in a first direction, and in contact with the non-display area(DA)(NDA); a second bypass side area between the bypass middle area and the first bypass side area; and a third bypass side area between the first bypass side area and the second bypass side area(area B in rows 1-10 in Fig 12)[0134 of DominguezCastro]; a first data bypass line extending in the first direction crossing the data lines(Dj), and electrically connected to a first data line in the first bypass side area from among the data lines(Dj); a first read-out bypass line extending in the first direction crossing the data lines(Dj), and electrically connected to a first read-out line[1335] from among the read-out line[1335]s(ROL); a first data connection line(SEL_PIX)[0240 of DominguezCastro] extending in a second direction parallel to the data lines(Dj) and crossing the first direction, the first data connection line paired with a second data line in the second bypass side area from among the data lines(Dj), and electrically connected to the first data bypass line(area B in rows 1-10 in Fig 12)[0134 of DominguezCastro]; and a first read-out connection line(SEL_PIX)[0240 of DominguezCastro] extending in the second direction, and electrically connected to the first read-out bypass line(1110)[0134 of DominguezCastro]. Bok and DominguezCastro does not disclose a first data bypass line extending in the first direction crossing the data lines(Dj), and electrically connected to a first data line in the first bypass side area from among the data lines(Dj); a first read-out bypass line extending in the first direction crossing the data lines(Dj), and electrically connected to a first read-out line[1335] from among the read-out line[1335]s(ROL); a first data connection line extending in a second direction parallel to the data lines(Dj) and crossing the first direction, the first data connection line paired with a second data line in the second bypass side area from among the data lines(Dj), and electrically connected to the first data bypass line; and a first read-out connection line extending in the second direction, and electrically connected to the first read-out bypass line. Lee disclose data lines(Dj) (D1/D2/D3), and electrically connected to a first data line(D1/D2/D3) in the first bypass side area from among the data lines(Dj) (D1/D2/D3); and electrically connected to a first read-out line from among the read-out lines(ROL) (162/164 of Lee); and a first read-out connection line(162/164 of Lee) extending in the second direction, It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Lee to the teachings of Bok in order to have higher data reading-out rates [0003, Lee].2 In doing so, a first data bypass line(1110)[0134 of DominguezCastro] extending in the first direction crossing the data lines(Dj) (D1/D2/D3), and electrically connected to a first data line(D1/D2/D3) in the first bypass side area from among the data lines(Dj) (D1/D2/D3); a first read-out bypass line(area B in rows 1-10 in Fig 12)[0134 of DominguezCastro] extending in the first direction crossing the data lines(Dj) (D1/D2/D3), and electrically connected to a first read-out line from among the read-out lines(ROL) (162/164 of Lee); a first data connection line(SEL_PIX)[0240 of DominguezCastro] extending in a second direction parallel to the data lines(Dj) (D1/D2/D3) and crossing the first direction, the first data connection line(SEL_PIX)[0240 of DominguezCastro] paired with a second data line(D1/D2/D3) in the second bypass side area from among the data lines(Dj) (D1/D2/D3), and electrically connected to the first data bypass line; and a first read-out connection line extending in the second direction, and electrically connected to the first read-out bypass line(area B in rows 1-10 in Fig 12)[0134 of DominguezCastro]. Re claim 17 Bok and DominguezCastro and Lee disclose the display device of claim 16, wherein the data lines(Dj) further comprise a third data line in the second bypass side area, and a fourth data line in the third bypass side area, wherein the first read-out connection line(SEL_PIX)[0240 of DominguezCastro] is paired with the fourth data line, and wherein the circuit layer further comprises: a second data bypass line extending in the first direction, and electrically connected to the fourth data line; and a second data connection line extending in the second direction, paired with the third data line, and electrically connected to the second data bypass line. Re claim 18 Bok and DominguezCastro and Lee disclose the display device of claim 17, further comprising: a scanning driving circuit configured to collect light sensing signals from the light sensing elements(IRC) through the light sensing pixel drivers [0213 of DominguezCastro] and the read-out line[1335]s(ROL); and a display driving circuit configured to transmit data signals for the light emitting pixel(510) drivers to the data lines(Dj), wherein the circuit layer further comprises: read-out transmission lines in the non-display area(DA)(NDA), and electrically connected between the read-out line[1335]s(ROL) and the scanning driving circuit; and data transmission lines in the non-display area(DA)(NDA), and electrically connected between the data lines(Dj) and the display driving circuit, wherein from among the data transmission lines: a first data transmission line configured to transmit a data signal of the first data line is electrically connected to the first data line through the first data bypass line and the first data connection line, a second data transmission line configured to transmit a data signal of the second data line is directly electrically connected to the second data line, a third data transmission line configured to transmit a data signal of the third data line is directly electrically connected to the third data line, and a fourth data transmission line configured to transmit a data signal of the fourth data line is electrically connected to the first data line through the second data bypass line and the second data connection line, and wherein from among the read-out transmission lines, a first read-out transmission line configured to transmit a signal of the first read-out line[1335] is electrically connected to the first read-out line[1335] through the first read-out connection line(SEL_PIX)[0240 of DominguezCastro] and the first read-out bypass line(1110)[0134 of DominguezCastro]. Re claim 19 Bok and DominguezCastro and Lee disclose the display device of claim 18, wherein the read-out line[1335]s(ROL) further comprise a second read-out line[1335] in the third bypass side area, and wherein from among the read-out transmission lines, a second read-out transmission line configured to transmit a signal of the second read-out line[1335] is directly electrically connected to the second read-out line[1335]. Re claim 20 Bok and DominguezCastro and Lee disclose the display device of claim 19, wherein the first read-out bypass line(1110)[0134 of DominguezCastro] comprises a plurality of first read-out bypass line(1110)[0134 of DominguezCastro]s, wherein the first data bypass line comprises a plurality of first data bypass lines, wherein the second data bypass line comprises a plurality of second data bypass lines, and wherein at least one of the first read-out bypass line(1110)[0134 of DominguezCastro]s is located between the first data bypass lines in the second direction, or between the second data bypass lines in the second direction. Re claim 21 Bok and DominguezCastro and Lee disclose the display device of claim 19, wherein each of the first bypass side area, the second bypass side area, and the third bypass side area comprises: an adjacent region in contact with the non-display area(DA)(NDA) in the second direction; and a separation region as a remaining region excluding the adjacent region, wherein the first read-out bypass line(1110)[0134 of DominguezCastro] is located in the adjacent region of each of the first bypass side area, the second bypass side area, and the third bypass side area, and wherein the first data bypass line and the second data bypass line are located in the separation region of each of the first bypass side area, the second bypass side area, and the third bypass side area. Re claim 22 Bok and DominguezCastro and Lee disclose the display device of claim 21, wherein the bypass area(area B in rows 1-10 in Fig 12)[0134 of DominguezCastro] of the display area(DA) further comprises a fourth bypass side area between the first bypass side area and the third bypass side area, wherein the data lines(Dj) further comprise a fifth data line in the fourth bypass side area, and a sixth data line in the second bypass side area, wherein the read-out line[1335]s(ROL) further comprise a third read-out line[1335] in the first bypass side area, and a fourth read-out line[1335] in the fourth bypass side area, wherein the circuit layer further comprises: a second read-out bypass line(1110)[0134 of DominguezCastro] extending in the first direction, and electrically connected to the third read-out line[1335]; a second read-out connection line(SEL_PIX)[0240 of DominguezCastro] extending in the second direction, paired with the fifth data line, and electrically connected to the second read-out bypass line(1110)[0134 of DominguezCastro]; a third data bypass line extending in the first direction, and electrically connected to the fifth data line; and a third data connection line extending in the second direction, paired with the sixth data line, and electrically connected to the third data bypass line, and wherein from among the read-out transmission lines: a third read-out transmission line configured to transmit a signal of the third read-out line[1335] is electrically connected to the third read-out line[1335] through the second read-out connection line(SEL_PIX)[0240 of DominguezCastro] and the second read-out bypass line(1110)[0134 of DominguezCastro]; and a fourth read-out transmission line configured to transmit a signal of the fourth read-out line[1335] is directly electrically connected to the fourth read-out line[1335]. Re claim 23 Bok and DominguezCastro and Lee disclose the display device of claim 22, wherein the fourth bypass side area comprises an adjacent region in contact with the non-display area(DA)(NDA) in the second direction, and a separation region as a remaining region excluding the adjacent region, wherein the first read-out bypass line(1110)[0134 of DominguezCastro] is located in the adjacent region of each of the second bypass side area and the third bypass side area, wherein the second read-out bypass line(1110)[0134 of DominguezCastro] is located in the adjacent region of each of the first bypass side area and the fourth bypass side area, and wherein the first data bypass line and the second data bypass line are located in the separation region of each of the first bypass side area, the second bypass side area, the third bypass side area, and the fourth bypass side area. Re claim 24 Bok and DominguezCastro and Lee disclose the display device of claim 23, wherein the circuit layer further comprises: a first power supply line and a second power supply line in the non-display area(DA)(NDA), and configured to transmit a first power and a second power, respectively, for driving the light emitting elements(LEL); and first auxiliary lines extending in the first direction, and electrically connected to the second power supply line, wherein each of the first bypass side area, the second bypass side area, the third bypass side area, and the fourth bypass side area further comprises a buffer region between the adjacent region and the separation region, and wherein the first auxiliary lines are located in the buffer region of each of the first bypass side area, the second bypass side area, the third bypass side area, and the fourth bypass side area. Response to Arguments Applicant’s arguments with respect to claim(s) 1-24 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PATRICIA D VALENZUELA whose telephone number is (571)272-9242. The examiner can normally be reached Monday-Friday 10am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Feb 12, 2024
Application Filed
Apr 02, 2026
Non-Final Rejection mailed — §103
Jul 01, 2026
Applicant Interview (Telephonic)
Jul 02, 2026
Response Filed
Sep 16, 2026
Examiner Interview Summary
Sep 23, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12721165
SEMICONDUCTOR CIRCUIT STRUCTURE WITH DIRECT DIE HEAT REMOVAL STRUCTURE
1y 0m to grant Granted Aug 25, 2026
Patent 12708031
SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREFOR
3y 1m to grant Granted Aug 11, 2026
Patent 12702000
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
3y 5m to grant Granted Aug 04, 2026
Patent 12701980
Layer-By-Layer Formation Of Through-Substrate Via
3y 4m to grant Granted Aug 04, 2026
Patent 12701999
SEMICONDUCTOR POWER MODULE
3y 0m to grant Granted Aug 04, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

2-3
Expected OA Rounds
90%
Grant Probability
92%
With Interview (+2.0%)
2y 2m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 722 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month