DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to the amended claims have been considered but are moot because the amendment required new grounds of rejection.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 11-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mitarai et al. (US 2015/0021081).
Regarding claim 1, Mitarai discloses a method of manufacturing a display device (fig. 2), the method comprising:
forming a display element layer and a pixel circuit layer on a first surface of a
substrate (S14, fig. 2, E1, fig. 3c and paragraph 0076);
forming an opening passing through the substrate from a second surface facing
the first surface to the first surface of the substrate to expose at least a portion of the pixel circuit layer (S17, fig. 2, V, fig. 3e and paragraphs 0079-0080);
filling the opening from the second surface of the substrate and forming a connection portion contacting the exposed portion of the pixel circuit layer (S19, fig. 2, TE, BE, fig. 3f and paragraph 0082); and
forming a capping layer having a pad opening exposing a portion of the
connection portion on the second surface of the substrate (S20, fig. 2, L14, fig. 3g and paragraph 0083),
wherein the opening is formed in a display area of the substrate at where an
image is displayed (figs. 3-4), and
wherein the capping layer (L14, fig. 3g) covers another portion of the connection portion (BE, fig. 3g) on the second surface of the substrate (fig. 3g and paragraph 0083).
Regarding claim 11, Mitarai further discloses wherein the forming of the pixel circuit layer comprises:
forming a semiconductor layer on the first surface of the substrate (figs. 3c-4 and paragraphs 0076, 0088-0100);
forming a gate electrode on the semiconductor layer (figs. 3c-4 and paragraphs 0076, 0088-0100);
forming a signal line disposed on a same layer as the gate electrode (figs. 3c-4 and paragraphs 0076, 0088-0100); and
forming a first transistor electrode and a second transistor electrode disposed on
the gate electrode and electrically connected to the semiconductor layer (figs. 3c-4 and paragraphs 0076, 0088-0100),
wherein the forming of the opening comprises exposing the signal line (figs. 3e-4 and paragraphs 0079, 0088-0100),
wherein the forming of the connection portion comprises forming a through
electrode filling the opening and a fan-out electrode covering the second surface of the substrate (figs. 3f-4 and paragraphs 0082, 0088-0100), and
wherein the through electrode extends continuously in a thickness direction of
the substrate between the signal line and the fan-out electrode, and comprises a
through end portion contacting a flat bottom surface of the signal line (figs. 3f-4 and paragraphs 0082, 0088-0100).
Regarding claim 12, Mitarai further discloses wherein the filling of an opening comprises:
filling a first opening and forming a first connection portion (fig. 3f and paragraphs 0082); and
filling a second opening spaced apart from the first opening and forming a
second connection portion (fig. 3f and paragraphs 0082, note: although one via is pictured, it is understood multiple vias are formed, as repetition of parts).
Regarding claim 13, Mitarai further discloses wherein the forming of the capping layer comprises:
forming a first pad opening exposing a portion of the first connection portion (fig. 3g and paragraph 0083); and
forming a second pad opening exposing a portion of the second connection
portion and spaced apart from the first pad opening (fig. 3g and paragraph 0083 note: although one pad is pictured, it is understood multiple pads are formed, as repetition of parts).
Regarding claim 14, Mitarai further discloseswherein the first connection portion has a first through electrode (TE, fig. 3g) and a first fan-out electrode (BE, fig. 3g), and the second connection portion has a second through electrode and a second fan-out electrode (fig. 3g and paragraph 0083 note: although one is pictured, it is understood multiples are formed, as repetition of parts).
.
Regarding claim 15, Mitarai further discloses wherein the first fan-out
electrode and the second fan-out electrode contact the second surface of the substrate (fig. 3g).
Regarding claim 16, Mitarai further discloses wherein the capping layer covers a portion of the first and second fan-out electrodes (fig. 3g).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Weber et al. (US 2013/0342099) in view of Mitarai et al. (US 2015/0021081).
Regarding claim 1, Weber discloses a method of manufacturing a display device, the method comprising:
forming a display element layer and a pixel circuit layer on a first surface of a substrate (24, figs. 1, 9 and Abstract and paragraphs 0023-0034, 0056);
forming an opening passing through the substrate from a second surface facing the first surface to the first surface of the substrate to expose at least a portion of the pixel circuit layer (figs. 1, 9 and Abstract and paragraph 0056);
filling the opening from the second surface of the substrate and forming a connection portion contacting the exposed portion of the pixel circuit layer; and forming a capping layer having a pad opening exposing a portion of the connection portion on the second surface of the substrate (paragraph 0049), wherein the opening is formed in a display area of the substrate at where an image is displayed (figs. 1, 9 and Abstract and paragraphs 0023-0034, 0056).
Weber does not explicitly disclose the added limitation of wherein the capping layer covers another portion of the connection portion on the second surface of the substrate. Weber more broadly discloses optional protective layers over the conductive layers on both sides of the substrate (fig. 6A and paragraph 0049). However, the use of protection or capping layers exposing only a portion of a connection pad was well known in the art at the time of filing and would therefore be deemed obvious to one of ordinary skill in the art at the time of filing. To illustrate such known teachings see Mitarai (fig. 3), for which the connection portion (BE and Te, fig. 3g) is covered with capping layer (L14, fig. 3g) that exposes BE and also covers another portion of BE (fig. 3g and paragraph 0083).
Regarding claim 2, Weber further discloses disposing a connection film and a driver electrically connected to the connection portion through the pad opening (paragraph 0031).
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Weber et al. (US 2013/0342099) in view of Mitarai et al. (US 2015/0021081) and further in view of Sauers et al. (US 2016/0329386).
Regarding claim 3, Weber in view of Mitarai discloses the method according to claim 1, as mentioned above. Weber does not disclose wherein the forming of the display element layer comprises:
forming a first electrode and a second electrode spaced apart from each other on the same layer; and
disposing a light emitting element between the first electrode and the second electrode.
However, such limitations of forming the display element are widely known and would therefore be deemed obvious to one of ordinary skill in the art at the time of filing. To illustrate such known teachings see Sauers as follows:
wherein forming the display element layer (84, figs. 4-5) comprises: forming a first electrode (36, fig. 4) and a second electrode (42, fig. 4) on the same layer (84, fig. 4) and spaced from each other; and disposing a light emitting element (38, fig. 4) between the first electrode and the second electrode (fig. 4 and paragraphs 0035-0036).
Regarding claim 4, Sauers further discloses wherein the forming of the display element layer comprises: forming a wavelength conversion layer on the light emitting element; and forming a color filter layer on the wavelength conversion layer, and wherein the wavelength conversion layer comprises a wavelength conversion particle and a scattering particle (paragraph 0040).
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over in view of Mitarai et al. (US 2015/0021081) Weber et al. (US 2013/0342099).
Regarding claims 17-18, Mitarai discloses the method according to claim 13, as mentioned above. Mitarai discloses a display device with pixel circuitry on one side of a substrate and an electrical via through the substrate to the other side of the substrate. Mitarai does not explicitly disclose further comprising:
disposing a first connection film and a first driver electrically connected to
the first connection portion through the first pad opening; and
disposing a second connection film and a second driver electrically
connected to the second connection portion through the second pad opening,
wherein the first and second connection films and the first and second
drivers are disposed below the second surface of the substrate or wherein the first driver is a scan driver, and the second driver is a data driver.
Weber discloses a display device with pixel circuitry on one side of a substrate and an electrical via through the substrate to the other side of the substrate connected to the appropriate display drivers (figs. 1-2, and paragraphs 0004, 0011-0012, 0029-0031)
It would have been obvious to one of ordinary skill in the art at the time of filing to have the via connections of Mitarai connected to the appropriate display drivers as taught by Weber for the purpose of functionality.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Mitarai et al. (US 2015/0021081).
Regarding claim 19, Mitarai discloses the method according to claim 1, as mentioned above. Mitarai further disclose wherein the capping layer is formed of an insulating layer (paragraph 0083). Mitarai does not explicitly disclose an inorganic material. The Examiner takes official notice that it would have been obvious to one of ordinary skill in the art at the time of filing to utilize an inorganic material as the capping layer.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent Application Publication 2018/0114820 discloses another example of a display device with a through substrate via connecting the front side to the back side of the display substrate.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
/DOUGLAS M MENZ/ Primary Examiner, Art Unit 2897 1/16/26
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