DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 3, 4, 5, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Harada (US 2017/0338818) in view of Yamazaki (US 2017/0033226) in view of Zhang (US 2017/0179192)
Regarding claim 2.
Harada teaches a display device comprising: a first transistor (fig 11:12[0171]) comprising a semiconductor layer (fig 11:14[0171]) comprising silicon [0171]; a first insulating layer (fig 11:24[0168]) over the first transistor (fig 11:12[0171]); a second transistor (fig 11:32[0169]) and a third transistor (fig 11:32[0169]) over the first transistor (fig 11:12[0171]), each of the second transistor (fig 11:32[0169]) and the third transistor (fig 11:32[0169]) comprising: a first gate electrode (fig 11:36[0169]) over the first insulating layer (fig 11:24[0168]);
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Harada does not teach each component of the second and third transistors in the above embodiment.
Harada teaches a second embodimenta display device comprising: a first transistor (fig 12a:500[0180]) comprising a semiconductor layer (fig 12a:301[0182]) comprising silicon (paragraph 0182); a first insulating layer (fig 12a:322[0188]) over the first transistor (fig 12a:500[0180]); a second transistor (fig 12a:400[0173]) and over the first transistor, each of the second transistor (fig 12a:400[0173]): a first gate electrode (fig 12b:405[0198]) over the first insulating layer (fig 12a:322[0188]); a metal oxide layer (fig 12b:230b[0210]) over the first gate electrode (fig 12b:405[0198]), and a second gate electrode (fig 12b:260[0218]) over the metal oxide layer (fig 12b:230b[0210]); a second insulating layer (fig 12b:280:[0230]) having a top surface; a third insulating layer (fig 12a:620[0231]) over the second insulating layer (fig 12b:280[0220]);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide components of the transistors in order that the carriers will flow through the semiconductor layer in a controlled fashion.
Harada does not teach the top surface of the top gate electrode is substantially level with the second insulating layer.
Yamazaki teaches a second insulating layer (fig 15a:410[0132]) having a top surface substantially level with a top surface of the second gate electrode (fig 15a:404[0278]) of the second gate transistor (fig 15a:2100[0278]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the gate electrode to be level with the surrounding dielectric in order to provide a gate contact area for subsequent connection with minimal variation in surface topography. The result of the combination is the second insulating layer has a top surface that is substantially level with a top surface of the second gate electrode of the second transistor and a top surface of the second gate electrode of the third transistor.
Harada does not teach the light emitting elements in the embodiment.
Zhang teaches a first conductor (fig 4:422b[0053]), a second conductor (fig 4:450[0053]), a third conductor, and a fourth conductor which are on a top surface; a plurality of light-emitting diodes (fig 4:440[0053]) comprising a first light-emitting diode (fig 5b:522[0056]) overlapping with the second transistor (fig 4:422[0053]) and a second light-emitting diode (fig 5b:524[0056]) overlapping with the third transistor (fig 4:422[0053]); and a substrate (fig 5b:575[0056]) over the plurality of light-emitting diodes (fig 5[0056]), wherein the plurality of light-emitting diodes (fig 3:344[0047]) is arranged in a matrix (fig 3 [0047]), wherein each of the plurality of light-emitting diodes (fig 4:440) comprises a first electrode (fig 4:446[0053]) and a second electrode (fig 4:430[0054]), wherein the first electrode (fig 4:446[0053]) of the first light-emitting diode (fig4:440[0053]) is electrically connected to the first conductor (fig 4:422b[0053]), wherein the second transistor (fig 4:422[0053]) is electrically connected to the first conductor (fig 4:422b[0053])wherein the second electrode (fig 4:430[0054]) of the first light-emitting diode (fig4:440[0053]) is electrically connected to the second conductor (fig 4:450[0053]), wherein the first electrode (fig 4:446[0053]) of the second light-emitting diode (fig4:440[0053]) is electrically connected to the third conductor, wherein the third transistor (fig 4:440[0053]) is electrically connected to the third conductor, wherein the second electrode of the second light-emitting diode (fig 4:440:0053]) is electrically connected to the fourth conductor (fig 4 [0053,0054]), and wherein the plurality of light-emitting diodes (fig4:440[0053]) is configured to emit light toward the substrate (fig 5b:575[0056]).
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It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention provide LED devices conductively bonded to the transistor structures so that voltage from the transistors will be supplied to the active region of the light emitters and thereby generate light (Zhang paragraph 5)
Regarding claim 3.
Harada in view of Yamazaki in view of Zhang teaches the structure of claim 2.
Zhang teaches at least one of the plurality of light-emitting diodes is a micro light-emitting diode (paragraph 51).
Regarding claim 4.
Harada in view of Yamazaki in view of Zhang teaches the structure of claim 2.
Harada teaches a display (fig 14:501[0235]) module comprising the display device (fig 14:540[0235]), and a connector (fig 14:520[0238]) or an integrated circuit electrically connected to the display device (fig 14:540[0235]).
Regarding claim 5.
Harada in view of Yamazaki in view of Zhang teaches the structure of 4.
Harada teaches at least one of an antenna (wireless signal reception portion) (fig 14:511[0236]), a battery, a housing, a camera, a speaker, a microphone, and an operation button.
Regarding claim 16.
Harada in view of Yamazaki in view of Zhang teaches the structure of claim 2.
Zhang teaches wherein in a cross-sectional view in a channel length direction of the second transistor (fig 4:440[0053]), a width of the first conductor is larger than a width of the first electrode of the first light- emitting diode and a width of the second conductor is larger than a width of the second electrode of the first light-emitting diode (see annotated fig 4) (paragraph 53).
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Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Harada (US 2017/0338818) in view of Yamazaki (US 2017/0033226) in view of Zhang (US 2017/0179192) as applied to claim 2 and further in view of Rhee (US 2017/0207249).
Regarding claim 17.
Harada in view of Yamazaki in view of Zhang teaches the structure of claim 2.
Zhang teaches wherein the first electrode of the first light-emitting diode (fig 4:440[0053]) is electrically connected (fig 4:430[0054]) to the first conductor (fig 4:422b[0053]), and wherein the second electrode of the first light-emitting diode (fig 4:440[0053]) is electrically connected (fig 4:430[0054]) to the second conductor (fig 4:450[0053]).
Yamazaki in view of Zhang does not teach using a conductive paste to form connections.
Rhee teaches wherein the first electrode (fig 4:156[0051]) of the first light-emitting diode (fig 4:150[0050]) is electrically connected to the first conductor (fig 3a:170[0049]) through a first conductive paste (fig 3a:130[0050]), and wherein the second electrode (fig 4:152[0051]) of the first light-emitting diode (fig 4:150[0051]) is electrically connected to the second conductor (fig 3a:140[0050]) through a second conductive paste (fig 3a:130[0051]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to bond the led electrodes to the conductor using a conductive paste in order to enable an anisotropic conductive bond which will facilitate electrical connection of the LED by eliminating the risk of shorts due to misplaced bonding material.
Claim(s) 10, 11, 12, 13, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Harada (US 2017/0338818) in view of Yamazaki (US 2017/0033226) in view of Zhang (US 2017/0179192)
Regarding claim 10.
Harada teaches a display device comprising: a first transistor (fig 11:12[0171]) comprising a semiconductor layer (fig 11:14[0171]) comprising silicon [0171]; a first insulating layer (fig 11:24[0168]) over the first transistor (fig 11:12[0171]): a second transistor (fig 11:32[0169]) and a third transistor [fig 11:32[0169]) over the first transistor (fig 11:12[0171]), each of the second transistor (fig 11:32[0169]) and the third transistor (fig 11:32[0169]) comprising: a first gate electrode fig 11:36[0169]) over the first insulating layer (fig 11:24[0168]);
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Harada does not teach the components of the transistors in the embodiment.
Harada teaches another embodiment comprising a display device comprising: a first transistor (fig 12a:500[0180]) comprising a semiconductor layer (fig 12a:301[0182]) comprising silicon (paragraph 0182); a first insulating layer (fig 12a:322[0188]) over the first transistor (12a:500[0180]): a second transistor (fig 12a:400[0173])
over the first transistor (fig 12a:500[0180]), each of the second transistor (fig 12a:400[0173]) comprising: a first gate electrode (fig 12b:405[0198]) over the first insulating layer (fig 12a:322[0188]); a metal oxide layer (fig 12b:230b[0210]) over the first gate electrode (fig 12b:405[0198]), and a second gate electrode (fig 12b:260[0218]) over the metal oxide layer (fig 12b:230b[0210]); a second insulating layer (fig 12b:280[0231]) having a top surface.
Harada does not teach the top surface of the top gate electrode is substantially level with the second insulating layer.
Yamazaki teaches a second insulating layer (fig 15a:410[0132]) having a top surface substantially level with a top surface of the second gate electrode (fig 15a:404[0278]) of the second gate transistor (fig 15a:2100[0278]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the gate electrode to be level with the surrounding dielectric in order to provide a gate contact area for subsequent connection with minimal variation in surface topography. The result of the combination is the second insulating layer has a top surface that is substantially level with a top surface of the second gate electrode of the second transistor and a top surface of the second gate electrode of the third transistor.
Harada does not teaches connecting a plurality of light emitting diodes.
Zhang teaches a display device (fig 5b:560[0056]) comprising:
a second transistor (fig 4:422[0053]) and a third transistor (fig 4:422[0053]);
each of the second transistor (fig 4:422[0053]) and the third transistor (fig 4:422[0053]) comprising a first gate electrode (fig 4:422c[0053])
a metal oxide layer (fig 4:422[0054]) over the first gate electrode (fig 4:422c[0053]) and a third insulating layer (annotated fig 4)
a first conductor (fig 4:422b[0053]), a second conductor (fig 4:450[0053]), a third conductor, and a fourth conductor which are on a top surface of the third insulating layer (annotated fig4); a plurality of light-emitting diodes (fig 4:440:[0053]) comprising a first light-emitting diode (fig 4:440[0053]) overlapping with the second transistor (fig 4:422[0053]) and a second light-emitting diode (fig 4:440[0053]) overlapping with the third transistor (fig 4:422[0054]); a substrate (fig 5b:575[0056]) over the plurality of light-emitting diodes (fig 5b:522,524[0056]); and a protective layer (annotated fig 4) comprising a region between the first light emitting diode (fig 4:440[0053]) and the second transistor (fig 4:422[0053]) and a region between the second light-emitting diode (fig 4:440[0053]) and the third transistor (fig 4:422[0053]), wherein the plurality of light-emitting diodes (fig 3:344[0047]) is arranged in a matrix (fig 3), wherein the plurality of light-emitting diodes (fig 5b:522,524,526[0056]) is configured to emit light toward the substrate (fig 5b:575[0056]), wherein each of the plurality of light-emitting diodes (fig 4:440[0053]) comprises a first electrode (fig 4:446[0053]), a first semiconductor layer (fig 4:440a[0053]), a light-emitting layer (fig 4:440c[0053]), a second semiconductor layer (fig 4:440b[0053]), and a second electrode (annotated fig 4), wherein the first electrode (fig 4:446[0053]) of the first light-emitting diode (fig 4:440[0053]) is electrically connected to the first conductor (fig 4:422b[0053]), wherein the second transistor (fig 4:422[0053]) is electrically connected to the first conductor (fig 4:422b[0053]), wherein the second electrode of the first light-emitting diode (fig 4:440[0053]) is electrically connected to the second conductor (fig 4:450[0053]) (annotated fig 4), wherein the first electrode of the second light-emitting diode (fig 4:440[0053]) is electrically connected to the third conductor (annotated fig 4), wherein the third transistor (fig 4:422[0053]) is electrically connected to the third conductor (annotated fig 4), wherein the second electrode of the second light-emitting diode (fig 4:440[0053]) is electrically connected to the fourth conductor (annotated fig 4), and wherein the protective layer is in contact with a side surface of the first electrode, a side surface of the first semiconductor layer, a side surface of the light-emitting layer (fig 4:440c[0053]), a side surface of the second semiconductor layer (fig 4:440b[0053]), and a side surface of the second electrode in each of the plurality of light-emitting diodes (fig 4:440[0053])and is not in contact with the third insulating layer (annotated fig 4,5b).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to attach light emitting diodes to the transistors of a display in order that the transistors can supply the LED with voltage and thereby generate light by the recombination of carriers.
Regarding claim 11.
Harada in view of Yamazaki in view of Zhang teaches the structure of claim 10.
Zhang teaches at least one of the plurality of light-emitting diodes is a micro light-emitting diode (paragraph 51).
Regarding claim 12.
Harada in view of Yamazaki in view of Zhang teaches the structure of claim 10.
Harada teaches a display (fig 14:501[0235]) module comprising the display device (fig 14:540[0235]), and a connector (fig 14:520[0238]) or an integrated circuit electrically connected to the display device (fig 14:540[0235]).
Regarding claim 13.
Harada in view of Yamazaki in view of Zhang teaches the structure of 10.
Harada teaches at least one of an antenna (wireless signal reception portion) (fig 14:511[0236]), a battery, a housing, a camera, a speaker, a microphone, and an operation button.
Regarding claim 18.
Harada in view of Yamazaki in view of Zhang teaches the structure of claim 10.
Zhang teaches wherein in a cross-sectional view in a channel length direction of the second transistor (fig 4:440[0053]), a width of the first conductor is larger than a width of the first electrode of the first light- emitting diode and a width of the second conductor is larger than a width of the second electrode of the first light-emitting diode (see annotated fig 4) (paragraph 53).
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Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Harada (US 2017/0338818) in view of Yamazaki (US 2017/0033226) in view of Zhang (US 2017/0179192) as applied to claim 10 and further in view of Rhee (US 2017/0207249).
Regarding claim 19.
Harada in view of Yamazaki in view of Zhang teaches the structure of claim 10.
Zhang teaches wherein the first electrode of the first light-emitting diode (fig 4:440[0053]) is electrically connected (fig 4:430[0054]) to the first conductor (fig 4:422b[0053]), and wherein the second electrode of the first light-emitting diode (fig 4:440[0053]) is electrically connected (fig 4:430[0054]) to the second conductor (fig 4:450[0053]).
Yamazaki in view of Zhang does not teach using a conductive paste to form connections.
Rhee teaches wherein the first electrode (fig 4:156[0051]) of the first light-emitting diode (fig 4:150[0050]) is electrically connected to the first conductor (fig 3a:170[0049]) through a first conductive paste (fig 3a:130[0050]), and wherein the second electrode (fig 4:152[0051]) of the first light-emitting diode (fig 4:150[0051]) is electrically connected to the second conductor (fig 3a:140[0050]) through a second conductive paste (fig 3a:130[0051]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to bond the led electrodes to the conductor using a conductive paste in order to enable an anisotropic conductive bond which will facilitate electrical connection of the LED by eliminating the risk of shorts due to misplaced bonding material.
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The applicant argues that Rhee (US 2017/0207249) in view of Yamazaki (US 2017/0033226) does not anticipate the claims.
However, in response to the amendments the claims are rejected over Yamazaki (US 2017/0033226) in view of Zhang (US 2017/0179192) (see above).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 December 29, 2025
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