DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I (claims 1-8, and new claims 21-32) in the reply filed on 6/15/26 is acknowledged. The traversal is on the ground(s) that “the Office has failed to demonstrate that a serious search or examination burden would be placed upon the Office if not so restricted.” This is not found persuasive because examination of Groups I-III would require a search and examination in different classifications and/or different fields of search, thereby imposing a serious search and examination burden on the Office. See MPEP §§ 803 and 808.02. Group I requires a search directed to a source/drain dopant profile. Group II requires a search directed to fabrication processes and steps for forming a dopant profile. Group III requires a search directed to a different device architecture and corresponding structural features. Since these searches encompass different search queries and prior art classes a serious search and examination burden would be imposed if conducted together. Accordingly, the traversal is not persuasive.
The requirement is still deemed proper and is therefore made FINAL.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, “a fourth doped region, between a fifth portion of the third doped region and a sixth portion of the third doped region” of claim 8 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 8 is/are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The specification provides the following support:
paragraph [0063] first, second, and fourth doped regions 106, 108, 110,
paragraph [0074] third doped region 401,
paragraph [0076] fifth portion 402e and sixth portion 402f.
There is no support for fourth doped region 110, between a fifth portion 402e of the third doped region 401 and a sixth portion 402f of the third doped region.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8, 21-32 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being ambiguous regarding essential structural cooperative relationships of elements, such ambiguity amounting to confusion between the necessary structural connections. See MPEP §§ 2172.01 and 2173.05. The ambiguous structural cooperative relationships are: the independent claims recite the semiconductor body as one element of the semiconductor device, and then separately recites a transistor whose drain, source, etc., are formed in that same semiconductor body. A transistor is not ordinarily a separate component that exists apart from the semiconductor body. Rather, the semiconductor body is part of the transistor’s structure. Structurally, the transistor already includes the semiconductor body or at least portions of it. This creates uncertainty regarding the relationship between the two recited elements. The claims fails to recite whether: 1. the semiconductor body is distinct from the transistor, or 2. the semiconductor body is the substrate in which the transistor is formed. Accordingly, the claim is awkward, inconsistent, and unclear as to the relationship among the elements of the claim.
The other claims are rejected as being dependent on one of claims 1, 21, 30.
Claims 1-8, 21-32 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The independent claims do not define what constitutes a “portion”. The claims do not specify whether these portions are: contiguous, discrete regions, sampling locations, equal-sized regions, or arbitrary locations.
The other claims are rejected as being dependent on one of claims 1, 21, 30.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4-6 is/are, to the extent taught and understood, rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Application Publication No. 2014/0103430 (Yoshino), cited by Applicant.
Yoshino discloses (Figs. 2, 8-15)
1. (Original) A semiconductor device, comprising:
a semiconductor body 3; and
a transistor 100 comprising:
a drain region 10 in the semiconductor body 3;
a first doped region 5 in the drain region 10;
a source region 11 in the semiconductor body 3;
a second doped region 6 adjacent the source region 11; and
a third doped region 13, between the first doped region 5 and the second doped region 6, comprising (Fig. 9) a first portion having a first concentration of dopants (left side of first concentration “lobe”, i.e., lower concentration), a second portion adjacent the first portion and having a second concentration of dopants (first concentration peak under the left slit 12a), a third portion adjacent the second portion and having a third concentration of dopants (valley overlap region or intermediate region), and a fourth portion adjacent the third portion and having a fourth concentration of dopants (second concentration peak under the right slit 12a),
wherein the third doped region has a gradient such that, along a first line extending through the first portion, the second portion, the third portion, and the fourth portion:
the first concentration is less than the second concentration;
the second concentration is greater than the third concentration; and
the third concentration is less than the fourth concentration (inherent based on Fig. 9 annotated below).
[AltContent: textbox (Impurity
concentration
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(horizontal
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drift region))][AltContent: ][AltContent: oval][AltContent: oval][AltContent: oval][AltContent: oval][AltContent: arrow][AltContent: connector][AltContent: connector][AltContent: connector][AltContent: connector][AltContent: connector]
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[AltContent: textbox (First portion Second portion Third portion Fourth portion
(C1) (C2) (C3) (C4)
Lower conc Higher conc Lower conc Higher conc)]
[AltContent: textbox (C1 < C2 C2 > C3 C3 < C4)]
Yoshino discloses (Figs. 9, 11 inherent based on mapping)
2. (Original) The semiconductor device of claim 1, wherein:
a first distance between the first portion (left shoulder) and the second portion (first peak) is less than a second distance between the first portion (left shoulder) and the fourth portion (second peak).
Yoshino discloses
4. (Original) The semiconductor device of claim 1, wherein the transistor comprises:
a gate structure 8 overlying the third doped region 13.
Yoshino discloses
5. (Original) The semiconductor device of claim 1, wherein:
dopants of the first doped region 5 are of a first conductivity type (P); and
dopants of the third doped region 13 are of the first conductivity type (P).
Yoshino discloses
6. (Original) The semiconductor device of claim 1, wherein:
the third doped region 13 is in the drain region 5.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshino as applied to claim 1 above, and further in view of TW Publication No. 201801154 (Liu), cited by Applicant.
Yoshino fails to disclose
3. (Original) The semiconductor device of claim 1, wherein:
the first doped region comprises a shallow well; and
the second doped region comprises a high voltage body region.
Liu teaches
A semiconductor device comprising:
the first doped region 112 comprises a shallow well; and
the second doped region 108 comprises a high voltage body region.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a shallow well and a high voltage body region in Yoshino. The motivation would be to reduce resistances optimize semiconductor trade-offs as taught by Liu (Background). It is well-known that a shallow well controls surface channel properties and prevents short-channel effects, while a deeper high-voltage body region spreads high electric fields to prevent premature breakdown. See MPEP 2144.03.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshino as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2019/0237571 (Saxena).
Yoshino fails to disclose
7. (Original) The semiconductor device of claim 1, wherein:
dopants of the first doped region are of a first conductivity type;
dopants of the second doped region are of a second conductivity type different than the first conductivity type; and
dopants of the third doped region are of the second conductivity type.
Saxena teaches
A semiconductor device comprising:
dopants of the first doped region 114 are of a first conductivity type (N);
dopants of the second doped region 115 are of a second conductivity type (P) different than the first conductivity type (N); and
dopants of the third doped region 116 are of the second conductivity type (P).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to select a suitable conductivity type of the regions in Yoshino. The motivation would be to addresses parasitic bipolar behavior. The doped region can be used irrespective of other enhancements in a field effect device structure to further improves a device's energy capability as taught by Saxena ([0017]). See MPEP 2144.07.
Claim(s) 8 is/are, to the extent taught and understood, rejected under 35 U.S.C. 103 as being obvious over Yoshino as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2011/0121437 (Weber).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Yoshino fails to disclose
8. (Original) The semiconductor device of claim 1, comprising:
a fourth doped region, between a fifth portion of the third doped region and a sixth portion of the third doped region, and having dopants of a first conductivity type, wherein dopants of the third doped region are of a second conductivity type different than the first conductivity type.
Weber teaches
A semiconductor device comprising:
a fourth doped region 118a, between a fifth portion 116a of the third doped region and a sixth portion 116a of the third doped region 108a, and having dopants of a first conductivity type (N), wherein dopants of the third doped region 108a are of a second conductivity type (P) different than the first conductivity type (N).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to select a suitable conductivity type of the portions in Yoshino. The motivation would be to achieve charge compensation and shape the electric field as taught by Weber ([0025]).
Claim(s) 21-23, 26 is/are, to the extent taught and understood, rejected under 35 U.S.C. 103 as being unpatentable over Yoshino in view of JP Publication No. 2827905 (Takeuchi).
Yoshino discloses (Figs. 2, 8-15)
21. (New) A semiconductor device, comprising:
a semiconductor body 3; and
a transistor 100 comprising:
a drain region 10 in the semiconductor body 3;
a first doped region 5 in the drain region 10;
a source region 11 in the semiconductor body 3;
a second doped region 6 adjacent the source region 11; and
a third doped region 13, between the first doped region 5 and the second doped region 6.
Yoshino fails to specifically disclose
wherein a concentration of dopants in the third doped region 13 comprises at least two peaks in a direction extending from the drain region 10 to the source region 11.
Takeuchi teaches (at least Figs. 4, 5, 9)
A semiconductor device comprising:
forming an impurity region using a two-stage ion implantation process ([0008]) wherein a concentration of dopants in the third doped region 2A comprises at least two peaks in a direction extending from the drain region 3A to the source region 3A.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a two-stage implantation technique in Yoshino. The motivation would be to reduce threshold voltage variation while simultaneously maintaining suppression of short-channel effects as taught by Takeuchi.
Yoshino discloses
22. (New) The semiconductor device of claim 21, wherein:
the third doped region 13 comprises:
a first portion having a first concentration of dopants (left side of first concentration “lobe”, i.e., lower concentration);
a second portion adjacent the first portion and having a second concentration of dopants (first concentration peak under the left slit 12a); and
a third portion adjacent the second portion and having a third concentration of dopants (valley overlap region or intermediate region), the first concentration is less than the second concentration, and the second concentration is greater than the third concentration (inherent based on Fig. 9 annotated).
Yoshino discloses
23. (New) The semiconductor device of claim 22, wherein:
the third doped region 13 comprises a fourth portion adjacent the third portion and having a fourth concentration of dopants (second concentration peak under the right slit 12a), wherein the third concentration is less than the fourth concentration (inherent based on Fig. 9 annotated).
Yoshino discloses
26. (New) The semiconductor device of claim 21, wherein:
the third doped region 13 is in the drain region.
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshino in view of Takeuchi as applied to claim 21 above, and further in view of Liu, cited by Applicant.
The combination of references fails to teach
24. (New) The semiconductor device of claim 21, wherein:
the first doped region comprises a shallow well; and
the second doped region comprises a high voltage body region.
Liu teaches
A semiconductor device comprising:
the first doped region 112 comprises a shallow well; and
the second doped region 108 comprises a high voltage body region.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a shallow well and a high voltage body region in the modified device of Yoshino. The motivation would be to reduce resistances optimize semiconductor trade-offs as taught by Liu (Background). It is well-known that a shallow well controls surface channel properties and prevents short-channel effects, while a deeper high-voltage body region spreads high electric fields to prevent premature breakdown. See MPEP 2144.03.
Claim(s) 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshino in view of Takeuchi as applied to claim 21 above, and further in view of Saxena.
The combination of references fails to teach
25. (New) The semiconductor device of claim 21, wherein:
dopants of the first doped region are of a first conductivity type; and
dopants of the third doped region are of the first conductivity type.
Saxena teaches
A semiconductor device comprising:
dopants of the first doped region 115 are of a first conductivity type (P); and
dopants of the third doped region 116 are of the first conductivity type (P).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to select a suitable conductivity type of the regions in the modified device of Yoshino. The motivation would be to addresses parasitic bipolar behavior. The doped region can be used irrespective of other enhancements in a field effect device structure to further improves a device's energy capability as taught by Saxena ([0017]). See MPEP 2144.07.
Claim(s) 27-29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshino Takeuchi as applied to claim 21 above, and further in view of U.S. Patent Application Publication No. 2008/0311720 (Hoffman).
The combination of references fails to teach
27. (New) The semiconductor device of claim 21, wherein the third doped region has a sidewall that is non-linear such that a first portion of the sidewall is separated from a second portion of the sidewall by a portion of the semiconductor body.
Hoffman teaches
A semiconductor device comprising:
wherein the third doped region 26 has a sidewall that is non-linear such that a first portion of the sidewall is separated from a second portion of the sidewall by a portion of the semiconductor body 14.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a non-linear sidewall in the modified device of Yoshino. The motivation would be to suppress the diffusion of the dopant as taught by Hoffman ([0023]).
Hoffman teaches
28. (New) The semiconductor device of claim 27, wherein:
at least one of the first portion of the sidewall or the second portion of the sidewall is curved.
Hoffman teaches
29. (New) The semiconductor device of claim 27, wherein the third doped region 26 has a second sidewall that is non-linear such that a first portion of the second sidewall is separated from a second portion of the second sidewall by a second portion of the semiconductor body 14.
Claim(s) 30-32 is/are, to the extent taught and understood, rejected under 35 U.S.C. 103 as being obvious over Yoshino in view of Weber.
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Yoshino discloses (Figs. 2, 8-15)
30. (New) A semiconductor device, comprising:
a semiconductor body 3; and
a transistor 100 comprising:
a drain region 10 in the semiconductor body 3;
a first doped region 5 in the drain region 10;
a source region 11 in the semiconductor body 3;
a second doped region 6 adjacent the source region 11; and
a third doped region 13 between the first doped region 5 and the second doped region 6, comprising a first portion (left side of first concentration “lobe”, i.e., lower concentration) and a second portion (first concentration peak under the left slit 12a).
Yoshino fails to specifically disclose
wherein:
a portion of the semiconductor body separates the first portion of the third doped region from the second portion of the third doped region;
dopants of the portion of the semiconductor body are of a first conductivity type; and
dopants of the third doped region are of a second conductivity type different than the first conductivity type.
Weber teaches
A semiconductor device comprising:
wherein:
a portion of the semiconductor body 118b separates the first portion 116c of the third doped region 108b from the second portion 116d of the third doped region 108b;
dopants of the portion of the semiconductor body 118b are of a first conductivity type (N); and
dopants of the third doped region 108b are of a second conductivity type (P) different than the first conductivity type (N).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to select a suitable conductivity type of the portions in Yoshino. The motivation would be to achieve charge compensation and shape the electric field as taught by Weber ([0025]).
Weber teaches
31. (New) The semiconductor device of claim 30, wherein:
the first portion 116c of the third doped region 108b comprises a first distribution (left peak) of dopants of the second conductivity type (P), and the second portion 116d of the third doped region 108b comprises a second distribution (right peak) of dopants of the second conductivity type (P).
Weber teaches
32. (New) The semiconductor device of claim 30, wherein:
the transistor 100 comprises a gate structure 126 over the semiconductor body 104, and the gate structure 126 overlies the first portion 116c of the third doped region 108b and the second portion 116d of the third doped region 108b.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Patent Application Publication Nos. 2016/0118493 (Liao), 2017/0278963 (Liu), U.S. Patent No. 9,362,266 (Lee) teach a semiconductor device having a doped region as multiple spaced portions with a controlled dopant distribution.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA M ARROYO whose telephone number is (703)756-1576. The examiner can normally be reached Monday - Friday (8:30 A.M. E.T. - 5:00 P.M. E.T.).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571.272.1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TERESA M. ARROYO/Primary Examiner, Art Unit 2893
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