DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/14/2025 is being considered by the examiner.
Response to Arguments
Applicant’s arguments, see pages 7-11, filed 07/01/2026, with respect to the rejection(s) of claim(s) 1-20 under 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of deVilliers et al. (US 20180068859 A1).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-4, 8-13, 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over deVilliers et al. (US 20180068859 A1).
Regarding claim 1, deVilliers discloses a method, comprising:
providing a wafer (105); ([0070], Fig. 12)
forming a shape control layer (173) on at least one of the wafer (105); ([0072], Fig. 13)
obtaining a bow measurement of the at least one of the wafer (105), the bow measurement including a plurality of z-height deviation values at different locations of the at least one of the wafer ([0060], Fig. 15)
activating the shape control layer (173) according to the bow measurement by applying a location-specific activation pattern to different regions of the shape control layer corresponding to the z-height deviation values to modify internal stresses of the different regions of the shape control layer; ([0045], [0063], [0064]) and
the wafer (105), at least one of which has the shape control layer (173) formed thereon that is activated according to the bow measurement of the at least one of the wafer. ([0070], [0072], Fig. 12-14)
deVilliers does not explicitly disclose:
a chiplet and
bonding the wafer and the chiplet
However, deVilliers discloses:
“In one embodiment, a substrate is received having a working surface and having a backside surface opposite to the working surface. The substrate has an initial overlay error resulting from one or more micro fabrication processing steps that have been executed to create at least part of a semiconductor device on the working surface of the substrate. FIG. 11 is a side cross-sectional view of an example substrate segment prior to processing. FIG. 12 illustrates devices 171 having been formed thereon” and “The substrate may include any material portion or structure of a device, particularly a semiconductor or other electronics device,” ([0079]) therefore leads the examiner to believe the devices 171 can be chiplets and therefore will be mapped as such throughout the rejection below.
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of deVilliers to have a chiplet and bonding the wafer and the chiplet in order “to create at least part of a semiconductor device on the working surface of the substrate.” [0059] which has “a modified bow which reduces overlay errors.” ([0034])
Regarding claim 2, deVilliers discloses the method of claim 1, further comprising:
receiving the bow measurement of the at least one of the wafer (105) and the chiplet. ([0040], [0059], [0060])
Regarding claim 3, deVilliers discloses the method of claim 1, further comprising:
measuring the at least one of the wafer (105) and the chiplet to identify the bow measurement of the at least one of the wafer and the chiplet. ([0038])
Regarding claim 4, deVilliers discloses the method of claim 3, wherein measuring the at least one of the wafer (105) and the chiplet to identify the bow measurement of the at least one of the wafer and the chiplet includes measuring the at least one of the wafer and the chiplet with the shape control layer (173) formed thereon to identify the bow measurement of the at least one of the wafer and the chiplet with the shape control layer formed thereon. ([0070])
Regarding claim 8, deVilliers discloses the method of claim 1, wherein the shape control layer (173) is formed on at least one of a frontside surface and a backside surface of the at least one of the wafer (105) and the chiplet. (Fig. 13)
Regarding claim 9, deVilliers discloses the method of claim 8, wherein the shape control layer (173) is formed on the backside surface of the at least one of the wafer (105) and the chiplet. ([0072],Fig. 13)
Regarding claim 10, deVilliers discloses the method of claim 1, wherein the shape control layer (173) includes an any combination of oxide and nitride. ([0072])
Regarding claim 11, deVilliers discloses the method claim 1. deVilliers does not explicitly disclose wherein the shape control layer includes an organic spin-on material.
However, deVilliers discloses:
“Deposition module 132 can be configured to deposit two or more films of opposing stresses. Alternatively, separate deposition modules are used for each film of opposing stress. Deposition module 132 can be configured to hold substrate 105 at a perimeter with backside surface facing upwardly, or downwardly. The backside surface can face upwardly for flowable or spin-on materials.” [0047] which leads the examiner to believe the first film (173) which is formed on the backside of the substrate (105) per [0072] and Fig. 13 can be a spin-on material.
Therefore, it would have been obvious to one skilled in the art before the effective filing date to use the teachings of deVilliers for the shape control layer includes an organic spin-on material because “the benefit of a common platform is increased efficiency.” ([0035])
Regarding claim 12, deVilliers discloses the method of claim 1, wherein the shape control layer (173) includes a heat sensitive material and is activated by a pattern of heat that corresponds to the bow measurement of the at least one of the wafer (105) and the chiplet. ([0072])
Regarding claim 13, deVilliers discloses the method of claim 12, wherein the pattern of heat is generated via direct laser write. ([0073])
Regarding claim 15, deVilliers discloses the method of claim 1, wherein the shape control layer (173) includes a photosensitive material and is activated by actinic radiation, patterning and etching, the patterning corresponding to the bow measurement of the at least one of the wafer (105) and the chiplet. ([0072] - [0074])
Regarding claim 16, deVilliers discloses the method of claim 15, wherein the actinic radiation provides localized heating that corresponds to the bow measurement of the at least one of the wafer (105) and the chiplet. ([0052])
Regarding claim 17, deVilliers discloses a method, comprising:
providing a wafer (105), at least one of which has an integrated layer (173) comprising one or more materials and structural formations of a semiconductor device formed thereon, the integrated layer (173) having a thermal characteristic that is sufficient to execute shape manipulation on the at least one of the wafer (105) when employing a temperature type activation;
obtaining a bow measurement of the at least one of the wafer, the bow measurement including a plurality of z-height deviation values at different locations of the at least one of the wafer and the chiplet;
applying the temperature type activation according to the bow measurement by applying a location-specific temperature activation pattern corresponding to the z-height deviation values to different regions of the integrated layer to execute the shape manipulation on the at least one of the wafer (105); and
deVilliers does not explicitly disclose:
a chiplet; and
bonding the wafer and the chiplet.
However, deVilliers discloses:
“In one embodiment, a substrate is received having a working surface and having a backside surface opposite to the working surface. The substrate has an initial overlay error resulting from one or more micro fabrication processing steps that have been executed to create at least part of a semiconductor device on the working surface of the substrate. FIG. 11 is a side cross-sectional view of an example substrate segment prior to processing. FIG. 12 illustrates devices 171 having been formed thereon” and “The substrate may include any material portion or structure of a device, particularly a semiconductor or other electronics device,” ([0079]) therefore leads the examiner to believe the devices 171 can be chiplets and therefore will be mapped as such throughout the rejection below.
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of deVilliers to have a chiplet and bonding the wafer and the chiplet in order “to create at least part of a semiconductor device on the working surface of the substrate.” [0059] which has “a modified bow which reduces overlay errors.” ([0034])
Regarding claim 18, deVilliers discloses The method of claim 17, further comprising:
receiving the bow measurement of the at least one of the wafer (105) and the chiplet. ([0059], [0060])
Regarding claim 19, deVilliers discloses The method of claim 18, further comprising:
measuring the at least one of the wafer (105) and the chiplet to identify the bow measurement of the at least one of the wafer and the chiplet. ([0038])
Regarding claim 20, deVilliers discloses the method of claim 19, wherein measuring the at least one of the wafer (105) and the chiplet to identify the bow measurement of the at least one of the wafer and the chiplet includes measuring the at least one of the wafer and the chiplet having the integrated layer (173) formed thereon to identify the bow measurement of the at least one of the wafer and the chiplet having the integrated layer formed thereon. ([0070])
Claims 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over deVilliers et al. (US 20180068859 A1) as applied to claim 1, and further in view of Garant et al. (US 20150235891 A1).
Regarding claim 5, deVilliers discloses the method of claim 1, wherein forming the shape control layer (173) on at least one of the wafer (105) and the chiplet includes forming a wafer shape control layer (173) on the wafer (105) and activating the shape control layer according to a bow measurement of the at least one of the wafer and the chiplet to modify an internal stress of the shape control layer includes activating the wafer shape control layer according to a bow measurement of the wafer to modify an internal stress of the wafer shape control layer.
deVilliers does not disclose:
forming a chiplet shape control layer on the chiplet, and
activating the chiplet shape control layer according to a bow measurement of the chiplet to modify an internal stress of the chiplet shape control layer.
However, Garant discloses:
forming a chiplet shape control layer (14) on the chiplet (18), and
activating the chiplet shape control layer ([0033]) according to a bow measurement of the chiplet (Fig. 6) to modify an internal stress of the chiplet shape control layer. ([0022], Fig 4)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of deVilliers and Garant for forming a chiplet shape control layer on the chiplet, and activating the chiplet shape control layer according to a bow measurement of the chiplet to modify an internal stress of the chiplet shape control layer in order to decrease “an overall bow of the wafer handler.” (Garant, [0007])
Regarding claim 6, deVilliers discloses the method of claim 1. deVilliers does not disclose further comprising: singulating another wafer to obtain the chiplet.
However, Garant discloses:
singulating another wafer (18) to obtain the chiplet (18). ([0037])
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of deVilliers and Garant for forming a chiplet shape control layer on the chiplet, and activating the chiplet shape control layer according to a bow measurement of the chiplet to modify an internal stress of the chiplet shape control layer in order to decrease “an overall bow of the wafer handler.” (Garant, [0007])
Regarding claim 7,Garant discloses the method of claim 6, wherein forming the shape control layer (14) on at least one of the wafer (10) and the chiplet includes forming another shape control layer (16) on the another wafer (18), and singulating the another wafer (18) to obtain the chiplet (18) includes singulating another wafer (18) with the another shape control layer (16) formed thereon to obtain the chiplet (18) with the shape control layer (16) formed thereon, the shape control layer (16) being singulated from the another shape control layer (14). ([0037])
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Garant for similar reasons mentioned beforehand.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over deVilliers et al. (US 20180068859 A1) as applied to claim 12 above, and further in view of Chen et al. (US 20220319818 A1).
Regarding claim 14, deVilliers discloses the method of claim 12. deVilliers does not disclose wherein the pattern of heat is generated by a plurality of heating units that have an arrangement corresponding to the pattern of heat and generate different temperature ranges.
However, Chen discloses:
the pattern of heat (101) is generated by a plurality of heating units (per [0033]) that have an arrangement corresponding to the pattern of heat and generate different temperature ranges. (per [0034]). (Fig. 2)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of deVilliers and Chen for the pattern of heat is generated by a plurality of heating units that have an arrangement corresponding to the pattern of heat and generate different temperature ranges in order to “individually control the temperature profile of the different portions of the substrate and thereby create and maintain desired spatial and temporal temperature profile, and to compensate for factors that affect CD uniformity.” (Chen, [0034])
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ASHLEY BLACKWELL whose telephone number is (703)756-1508. The examiner can normally be reached Mon-Fri 8:00-1600.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ASHLEY NICOLE BLACKWELL/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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