DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 2/13/2024, 10/11/2024, 2/26/2025, 9/24/2025 and 5/13/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 and 10-20 are rejected under 35 U.S.C. 103 as being unpatentable over Shen et. al. (US-20220037268A1, hereinafter Shen), and further in view of Polomoff et.al. (US-20210356514A1, hereinafter Polomoff)
Regarding Claim 1.
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Shen teaches in Fig.15, Fig. 16 and in related text A semiconductor structure, comprising:
a first substrate (#122) comprising a device region (#118) and a ring region (#132) surrounding the device region;
a first interconnect structure (#126) over the first substrate (#122), the first interconnect structure comprising a first via tower (#134 in #132A) and a second via tower (#134 in #132B) extending through the first interconnect structure (#126) and disposed directly over the ring region (#132);
a first bonding layer (#152) over the first interconnect structure (#126) and comprising a first metal bonding feature (#152); a second bonding layer (#252) over the first bonding layer (#152) and comprising a second metal bonding feature (#252) in contact with the first metal bonding feature; (Fig.16a [0046]) and
a second interconnect structure (#226) over the second bonding layer (#252), the second interconnect structure (#226) comprising a third via tower (#232A) extending through the second interconnect structure (#226) and disposed directly over the ring region,
wherein the first via tower (#132A) is electrically coupled to the third via tower (#232A) by way of the first metal bonding feature (#152) and the second metal bonding feature (#252). ([0046-0052])
Shen does not explicitly disclose wherein the first via tower is electrically coupled to the second via tower by way of a first metal line in the first interconnect structure,
Polomoff teaches in Fig.5 wherein the first via tower is electrically coupled to the second via tower by way of a first metal line in the first interconnect structure, (Fig.5 metal sections #250 connected by lower connector #252) It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify Shen’s semiconductor device with the teachings of Polomoff, as identified above, in order to electrically monitor the peripheral seal-ring bonding region for crack, non-bond, or delamination-related damage before the damage reaches the active device region.
Regarding Claim 2.
Shen modified by Polomoff teaches The semiconductor structure of claim 1,
Polomoff teaches in Fig.8 wherein the first metal line (#352) is adjacent the first substrate (#358) and away from the first bonding layer (#354). It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify the combination of Shen and Polomoff with the teachings of Polomoff, as identified above, in order to implement a lower-level daisy-chain crack-detection conductor.
Regarding Claim 3.
Shen modified by Polomoff teaches The semiconductor structure of claim 1, further comprising:
Shen further teaches in Fig.15 a second substrate (#222) disposed over the second interconnect structure (#226). ([0046])
Regarding Claim 4.
Shen modified by Polomoff teaches The semiconductor structure of claim 3, Shen further teaches in Fig.15-Fig,16 wherein the second interconnect structure (#226) further comprises a fourth via tower (#232B) extending through the second interconnect structure. ([0046-0052])
Regarding Claim 5.
Shen modified by Polomoff teaches The semiconductor structure of claim 4,
Polomoff teaches in Fig.5 wherein the third via tower is electrically coupled to the fourth via tower by way of a first metal line in the first interconnect structure, (Fig.5 metal sections #250 connected by lower connector #252) It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify Shen’s semiconductor device with the teachings of Polomoff, as identified above, in order to electrically monitor the peripheral seal-ring bonding region for crack, non-bond, or delamination-related damage before the damage reaches the active device region.
Regarding Claim 6.
Shen modified by Polomoff teaches The semiconductor structure of claim 5,
Polomoff teaches in Fig.8 wherein the second metal line (#352) is adjacent the second substrate (#358) and away from the second bonding layer (#354). It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify the combination of Shen and Polomoff with the teachings of Polomoff, as identified above, in order to implement a daisy-chain crack-detection conductor.
Regarding Claim 7.
Shen modified by Polomoff teaches The semiconductor structure of claim 5,
As discussed for claim 1, Shen teaches electrical coupling between first-die and second-die seal-ring/via-tower structures through bonded metal seal-ring extensions, and Polomoff teaches daisy-chaining adjacent vertical conductive metal sections using metal connectors. As discussed for claim 5, the same daisy-chain connector teaching is applied to couple the third and fourth via towers in the second interconnect structure. Accordingly, the fourth via tower would be electrically coupled to the second via tower by way of the second metal line, third via tower, bonded first/second via-tower path, and first metal line, forming the known monitored daisy-chain path taught by Polomoff as shown in Fig.5.
Therefore the combination of Shen and Polomoff teaches wherein the fourth via tower is electrically coupled to the second via tower by way of the second metal line, the third via tower, the first via tower, and the first metal line.
Regarding Claim 10.
Shen teaches in Fig.41 A device structure, comprising:
a first die (#712) comprising a first device region (#718) and a first seal ring region (#732) surrounding the first device region;
a first bonding layer disposed over the first die; (bonding layer between the interface within #700)
a second bonding layer disposed over the first bonding layer; (bonding layer between the interface within #800)
a second die (#812) disposed over the second bonding layer and comprising a second device region(#818) and a second seal ring region (#832) surrounding the second device region; ([0087-0089])
Shen does not explicitly disclose
a crack sensor disposed in the first seal ring region, the first bonding layer, the second bonding layer, and the second sealing region.
However Polomoff teaches a crack detecting and monitoring system formed in an inactive region surrounding an active region of an integrated circuit, including electrically conductive perimeter lines configured to detect and monitor cracks before the cracks propagate into the active region, Polomoff further teaches that the conductive crack-detection lines may be formed from conductive metal sections interconnected by vias and daisy-chained by lower and upper metal connectors, and that a crack may be sensed as a resistance increase or open circuit. It would have been obvious to a person of ordinary skill in the art to configure Shen’s conductive seal-ring/bonding-layer structures as a Polomoff-style electrical crack sensor disposed in the first seal ring region, first bonding layer, second bonding layer, and second seal-ring region, in order to electrically monitor the peripheral bonded seal-ring region for cracks, non-bonding, or delamination before such defects affect the active device region. Therefore, Shen in view of Polomoff teaches or renders obvious the device structure of claim 10.
Regarding Claim 11.
Shen modified by Polomoff teaches The device structure of claim 10,
Shen further teaches wherein the second seal ring region (#832) vertically overlaps with the first seal ring region (#732).
Regarding Claim 12.
Shen modified by Polomoff teaches The device structure of claim 10,
Shen further teaches wherein the first die (#712) comprises:
a first semiconductor substrate (#722), and
a first interconnect structure (#726/#126) over the first semiconductor substrate,
wherein the second die (#812) comprises:
a second interconnect structure (#826/#126) disposed over the second bonding layer (bonding layer between #800 and #700), and
a second semiconductor substrate (#822) disposed over the second interconnect structure.
Regarding Claim 13.
Shen modified by Polomoff teaches The device structure of claim 12,
Shen further teaches wherein the first interconnect structure (#726) comprises a first plurality of via towers (#732A) extending through an entire thickness of the first interconnect structure,
wherein the second interconnect structure (#826) comprises a second plurality of via towers (#832A) extending through an entire thickness of the second interconnect structure,
Polomoff further teaches in Fig.5 wherein the crack sensor comprises a daisy chain structure that includes more than one of the first plurality of via towers and more than one of the second plurality of via towers. It would have been obvious to use the multiple seal-ring/via-tower structures in Shen’s first and second interconnect structures as the vertical conductive sections of a Polomoff-style daisy-chain crack sensor, so that the crack sensor includes more than one of the first plurality of vias towers and more than one of the second plurality of via towers. Therefore, Shen in view of Polomoff teaches or renders obvious the limitation of claim 13.
Regarding Claim 14.
Shen modified by Polomoff teaches The device structure of claim 13,
Shen further teaches wherein the first plurality of via towers (#732A) are disposed in the first seal ring region (#732),
wherein the second plurality of via towers (#832A) are disposed in the second seal ring region (#832).
Regarding Claim 15.
Shen modified by Polomoff teaches The device structure of claim 13,
Shen further teaches wherein the first bonding layer comprises a first plurality of bonding features (#752),
wherein the second bonding layer comprises a second plurality of bonding features (#852),
wherein each of the first plurality of bonding features is vertically aligned and in contact with one of the second plurality of bonding features. (as shown in Fig. 41)
Regarding Claim 16.
Shen modified by Polomoff teaches The device structure of claim 15,
Polomoff further teaches a daisy-chain crack sensor in which multiple conductive sections are stitched together so that the electrical continuity/resistance of the sensor path may be monitored. It would have been obvious to include more than one of Shen’s first-die bonding features and more than one of Shen’s second-die boding features in the daisy-chain sensor path, as taught by Polomoff, so that the electrical crack/delamination detection path extends through the bonded metal feature at the hybrid-bond interface. Therefore, Shen in view of Polomoff teaches wherein the daisy chain structure further includes more than one of the first plurality of bonding features and more than one of the second plurality of bonding features.
Regarding Claim 17.
Shen teaches in Fig.41 and related text A method, comprising:
forming a first die (#712) that comprises:
a first semiconductor substrate (#722), and
a first interconnect structure (#7126/#126) over the first semiconductor substrate (#722);
forming a first bonding layer (layer including #752) over the first interconnect structure;
forming a second die (#812) that comprises:
a second semiconductor substrate (#822), and
a second interconnect structure (#826) over the second semiconductor substrate (#822);
forming a second bonding layer (layer including #852) over the second interconnect structure; and
bonding the second die to the first die by bonding the second bonding layer to the first bonding layer,
wherein the first interconnect structure comprises a first device region (#718) and a first seal ring region (#732) surrounding the first device region,
wherein the second interconnect structure comprises a second device region (#818) and a second seal ring region (#832) surrounding the second device region,
wherein, after the bonding, the first seal ring region (#732) is vertically aligned with the second seal ring region (832),
wherein the first interconnect structure comprises a first via tower (#732A) and a second via tower (#732B) in the first seal ring region (#732),
wherein the second interconnect structure comprises a third via tower (#832A) and a fourth via tower (#832B) in the second seal ring region (#832), ([0087-0089])
Shen does not explicitly disclose
wherein the first via tower and the second via tower are connected by a first metal line in the first interconnect structure,
wherein the third via tower and the fourth via tower are connected by a second metal line in the second interconnect structure.
However, Polomoff teaches in Fig.5 wherein via towers are connected by metal lines in an interconnect structure, in order to construct a crack-detection structure in an inactive region surrounding an active region, where vertical conductive metal sections are daisy-chained together by lower and upper metal connetors. It would have been obvious to a person of ordinary skill in the art to configure Shen’s first-die and second-die seal-ring/via structures with Polomoff’s daisy-chain metal-line connections, so that the seal-ring regions of the bonded dies may be electrically monitored for cracks, non-bonding, or delamination before such defects reach the active device region.
Regarding Claim 18.
Shen modified by Polomoff teaches The method of claim 17,
Polomoff teaches that the crack-detection perimeter lines includes discrete conductive metal sections daisy-chained together by metal connectors, and that the detection circuit senses changes in electrical characteristics, such as resistance increase or open circuit, caused by damage to the perimeter lines. In order for Polomoff’s daisy-chain sensing structure to operate as intended, adjacent conductive metal sections must be electrically coupled through the intended metal connector path and not through unintended parallel conductive paths that would bypass the monitored path. It would therefore have been obvious, when applying Polomoff’s daisy-chain connection scheme to Shen’s first and second die seal-ring/via-tower structures, to electrically isolate the first and second via towers from each other except through the first metal line and to electrically isolate the third and fourth via towers from each other except through the second metal line, so that the electrical continuity/resistance of the sensor path can be reliably monitored. Therefore Shen in view of Polomoff teaches wherein, but for the first metal line, the first via tower and the second via tower are electrically isolated from each other, wherein, but for the second metal line, the third via tower and the fourth via tower are electrically isolated from each other.
Regarding Claim 19.
Shen modified by Polomoff teaches The method of claim 17,
Polomoff teaches in Fig.8 that lower metal connectors #252 used to daisy-chain adjacent conductive metal sections may be formed in lower BEOL metallization layer, such as the M1 metallization layer.([0040]) Applying this teaching to Shen’s first interconnect structure would place the first metal line adjacent the first semiconductor substrate and away from the first bonding layer. It would have been obvious to use lower-level BEOL metal connectors in both dies to implement the Polomoff-style daisy-chain sensor path in Shen’s aligned first and second seal-ring regions. Therefore Shen modified by Polomoff teaches wherein the first metal line is adjacent the first semiconductor substrate and away from the first bonding layer, wherein the second metal line is adjacent the second semiconductor substrate and away from the second bonding layer.
Regarding Claim 20.
Shen modified by Polomoff teaches The method of claim 17,
Polomoff teaches that adjacent vertical conductive metal sections of a perimeter line may be daisy-chained by an alternating sequence of lower metal connectors #252 and upper metal connectors #254, where lower connectors are formed in a lower BEOL layer and upper connectors are formed in an upper metallization layer. It would have been obvious to implement Shen’s first-die seal-ring/via-tower connection using an upper metal connector corresponding to Polomoff’s upper connector #254, thereby placing the first metal line adjacent the first bonding layer and away from the first semiconductor substrate, It would also have been obvious to implement Shen’s second-die seal-ring/via-tower connection using a lower metal connector corresponding to Polomoff’s own connector #252, thereby placing the second metal line adjacent the second semiconductor substrate and away from the second bonding layer. Using upper and lower connector levels in the daisy-chain sensor path is directly suggested by Polomoff’s alternating connector arrangement and is a predictable layout choice for routing a crack/delamination detection path multiplayer BEOL structures. Therefore Shen modified by Polomoff teaches wherein the first metal line is adjacent the first bonding layer and away from the first semiconductor substrate, wherein the second metal line is adjacent the second semiconductor substrate and away from the second bonding layer.
Allowable Subject Matter
Claims 8-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 8 contains allowable subject matter, because the prior art, either singly or in combination, fails to anticipate or render obvious, the device, …wherein the fifth via tower is electrically coupled to the fourth via tower by way of the third metal bonding feature and the fourth metal bonding feature. These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
Claim 9 contains allowable subject matter because they depend from claim 8 .
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SOPHIA W KAO whose telephone number is (703)756-4797. The examiner can normally be reached Monday-Friday 9am-5pm Pacific Time.
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/SOPHIA W KAO/Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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