Prosecution Insights
Last updated: October 02, 2026
Application No. 18/441,335

DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

Non-Final OA §102§103
Filed
Feb 14, 2024
Priority
Feb 15, 2023 — RE 10-2023-0019850
Examiner
XU, ZHIJUN
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Display Co., Ltd.
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
1y 0m
Est. Remaining
89%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
56 granted / 73 resolved
+8.7% vs TC avg
Moderate +12% lift
Without
With
+11.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
31 currently pending
Career history
109
Total Applications
across all art units

Statute-Specific Performance

§103
70.2%
+30.2% vs TC avg
§102
16.6%
-23.4% vs TC avg
§112
11.5%
-28.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 73 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Group I and Species 1 in the reply filed on Jul. 22nd 2026 is acknowledged. Claims 1-16 are examined in this office action. Claims 17-21 are withdrawn from further consideration. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-6, 9-11 and 15-16 are rejected under 35 U.S.C. 102 (a)(2) as being anticipated by Takayama et al. (US 20230292555), hereinafter Takayama. Regarding claim 1, Takayama teaches a display device (Abstract) comprising: a first light emitting element (fig. 6, red subpixel SP1; para. 0033); a second light emitting element (green subpixel SP3; para. 0033); and a barrier wall conductive layer (partition 6 with upper electrode second portions UE1b, UE3b above, lower portions 61 of the partitions 6 are conductive; para. 0042, 0072, 0077) disposed between the first light emitting element (SP1) and the second light emitting element (SP3) and electrically connected (electrically connected by UE1, UE3; para. 0077) to the first light emitting element (SP1) and the second light emitting element (SP3), wherein a barrier wall opening (open for upper surface 62A; para. 0099) is formed through the barrier wall conductive layer (6), and the barrier wall opening (open for 62A) is disposed between the first light emitting element (SP1) and the second light emitting element (SP3). Regarding claim 2, Takayama further teaches the display device of claim 1, wherein the first light emitting element (fig. 6, SP1) is electrically connected (electrically connected by UE1) to a side surface of the barrier wall conductive layer (left side surface of 6) adjacent to the first light emitting element (SP1), and the second light emitting element (SP3) is electrically connected (electrically connected by UE3) to another side surface of the barrier wall conductive layer (right side surface of 6) adjacent to the second light emitting element (SP3). Regarding claim 3, Takayama further teaches the display device of claim 1, wherein the barrier wall conductive layer (fig. 6, in an alternative consideration, left 6 with UE1b, UE3b above) is divided into a plurality of portions (second portion UE1b and second portion UE3b; para. 0054, 0060) by the barrier wall opening (open for 62A on the left), and the first light emitting element (SP1) is electrically insulated (61 may not be in contact; para. 0097) from the second light emitting element (left SP3) by the plurality of portions (UE1b, UE3b) of the barrier wall conductive layer (left 6). Regarding claim 4, Takayama further teaches the display device of claim 1, wherein the barrier wall conductive layer (fig. 6, 6) comprises: a first barrier wall conductive layer (upper electrode UE1 second portion UE1b; para. 0054) adjacent to the first light emitting element (SP1) and electrically connected (electrically connected by UE1) to the first light emitting element (SP1); and a second barrier wall conductive layer (upper electrode UE3 second portion UE3b; para. 0060) adjacent to the second light emitting element (SP3), electrically connected (electrically connected by UE3) to the second light emitting element (SP3), and electrically insulated (by open for 62A) from the first barrier wall conductive layer (UE1b) by the barrier wall opening (open for 62A). Regarding claim 5, Takayama further teaches the display device of claim 4, wherein the first barrier wall conductive layer (fig. 2, UE1 of 6) has a closed-loop shape (rectangle shape) and surrounds the first light emitting element (SP1), and the second barrier wall conductive layer (UE3 of 6) has a closed-loop shape (rectangle shape) and surrounds the second light emitting element (SP3). Regarding claim 6, Takayama further teaches the display device of claim 5, wherein the first light emitting element (fig. 2, SP1) is in contact with a first inner side surface of the first barrier wall conductive layer (inner side surface of 61 by UE1) surrounding the first light emitting element (SP1), and the second light emitting element (SP3) is in contact with a second inner side surface of the second barrier wall conductive layer (inner side surface of 61 by UE3) surrounding the second light emitting element (SP3). Regarding claim 9, Takayama further teaches the display device of claim 1, further comprising: a pixel definition layer (fig. 6, rib 5; para. 0042) in which light emitting openings (apertures AP1, AP3 of 5 for SP1 and SP3; para. 0042) are formed, wherein the first and second light emitting elements (SP1, SP3) are disposed in the light emitting openings (AP1, AP3), and the barrier wall conductive layer (6) is disposed on the pixel definition layer (5). Regarding claim 10, Takayama further teaches the display device of claim 9, wherein the pixel definition layer (fig. 6, 5) comprises an inorganic layer (inorganic insulating layer; para. 0073). Regarding claim 11, Takayama further teaches the display device of claim 9, wherein openings (fig. 6, openings between 6) in which the first and second light emitting elements (SP1, SP3) are disposed are formed through the barrier wall conductive layer (6), and the openings (openings between 6) overlap the light emitting openings (AP1, AP3) and have a size (openings between 6 are wider) greater than those of the light emitting openings (AP1, AP3). Regarding claim 15, Takayama further teaches the display device of claim 1, further comprising: a thin film encapsulation layer (fig. 6, sealing layers SE1, SE3; para. 0066) disposed on the first and second light emitting elements (SP1, SP3) and the barrier wall conductive layer (6), wherein the barrier wall opening (open for 62A) is consecutively formed through the barrier wall conductive layer (6) and the thin film encapsulation layer (SE1, SE3). Regarding claim 16, Takayama further teaches the display device of claim 15, further comprising: a cover insulating layer (fig. 3, 6, protective layer 13; para. 0070) disposed on the thin film encapsulation layer (SE1, SE3), wherein the cover insulating layer (13) is disposed in the barrier wall opening (open for 62A). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 7-8 and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Takayama in view of Kwak et al. (US 20220173352 from IDS). Regarding claim 7, Takayama teaches the display device of claim 4 including the first barrier wall conductive layer (fig. 6, UE1 of 6). Takayama fails to explicitly teach a transistor disposed below the first barrier wall conductive layer and electrically connected to the first barrier wall conductive layer. However, Kwak teaches a transistor (Kwak: fig. 3, thin film transistor T; para. 0080) disposed below the first barrier wall conductive layer (Kwak: second electrode 190 on second bank 174; para. 0112-0113, similar to UE1 of 6 of Takayama) and electrically connected to the first barrier wall conductive layer (Kwak: 190 on 174). Kwak and Takayama are considered to be analogous to the claimed invention because they are in the same field of display devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a transistor as taught by Kwak. Doing so would realize a thin film transistor essential to and below the LED for wider emission area (Kwak: para. 0040). Regarding claim 8, Takayama in view of Kwak further teaches the display device of claim 7, further comprising: an insulating layer (Kwak: fig. 3, overcoat layer 155; para. 0086) disposed between the first barrier wall conductive layer (Kwak: 190 on 174) and the transistor (Kwak: T); and a light emitting connection portion (Kwak: first electrode 160; para. 0087) disposed in a contact hole (Kwak: contact hole through 155) formed through a portion of the insulating layer (Kwak: 155), the light emitting connection portion (Kwak: 160) overlapping the first barrier wall conductive layer (Kwak: 190 on 174) in plan view, wherein the light emitting connection portion (Kwak: 160) extends from the first barrier wall conductive layer (Kwak: 190 on 174) and is electrically connected to the transistor (Kwak: T) via the contact hole (Kwak: contact hole through 155). Regarding claim 12, Takayama further teaches the display device of claim 9, wherein the barrier wall conductive layer (fig. 6, 6) comprises: a second conductive layer (61); and a third conductive layer (62) disposed on the second conductive layer (61), and side surfaces of the first and third conductive layers (62) adjacent to each of the first and second light emitting elements (SP1, SP3) protrude outward more than a side surface of the second conductive layer (61) adjacent to each of the first and second light emitting elements (SP1, SP3). Takayama fails to explicitly teach a first conductive layer disposed on the pixel definition layer; the second conductive layer disposed on the first conductive layer; and side surfaces of the first conductive layers protrude outward more than a side surface of the second conductive layer. However, Kwak teaches a first conductive layer (Kwak: fig. 3, third layer 160c; para. 0091) disposed on the pixel definition layer (first bank 172 second bank 174; para. 0047, similar to 5 of Takayama); the second conductive layer (Takayama: 61 on 5, similar to 172/174 above 160c) disposed on the first conductive layer (Kwak: 160c); and side surfaces of the first conductive layers (Kwak: 160c) protrude outward more than a side surface of the second conductive layer (Takayama: 61, which protrude smaller than 174). Kwak and Takayama are considered to be analogous to the claimed invention because they are in the same field of display devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a first conductive layer for a transistor as taught by Kwak. Doing so would realize a thin film transistor essential to and below the LED for wider emission area (Kwak: para. 0040). Regarding claim 13, Takayama in view of Kwak further teaches the display device of claim 12, wherein the first light emitting element (Takayama: fig. 6, SP1) comprises: a first electrode (Takayama: lower electrode LE1; para. 0090) disposed under the pixel definition layer (Takayama: 5) and partially exposed via a corresponding light emitting opening (Takayama: opening of 5 for SP1) among the light emitting openings (Takayama: APT1 for SP1); a second electrode (Takayama: upper electrode UE1; para. 0090) disposed on the first electrode (Takayama: LE1); a functional layer (Takayama: fig. 4, functional layers of carrier adjustment layers CA1 and CA2 of organic layer OR; para. 0091) disposed between the first electrode (Takayama: LE1) and the second electrode (Takayama: UE1); and a light emitting layer (Takayama: light emitting layer EM; para. 0091) disposed in the functional layer (Takayama: CA1, CA2), and the functional layer (Takayama: CA1, CA2 of OR) and the second electrode (Takayama: UE1) are in contact with the side surface of the second conductive layer (Takayama: 61) of the barrier wall conductive layer (Takayama: 6). Regarding claim 14, Takayama in view of Kwak further teaches the display device of claim 13, wherein the functional layer (Takayama: fig. 6, CA1, CA2 of second portion OR1b of OR; para. 0053) and the second electrode (Takayama: second portion UE1b of UE1; para. 0054) are further disposed on the barrier wall conductive layer (Takayama: 6), and the barrier wall conductive layer (Takayama: 6) and the second electrode (Takayama: UE1b) are electrically insulated from each other by the functional layer (Takayama: OR1b). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHIJUN XU whose telephone number is (571)270-3447. The examiner can normally be reached Monday-Thursday 9am-5pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ZHIJUN XU/Examiner, Art Unit 2818 /BRIAN TURNER/Primary Examiner, Art Unit 2818
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Prosecution Timeline

Feb 14, 2024
Application Filed
Sep 08, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
89%
With Interview (+11.9%)
3y 7m (~1y 0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 73 resolved cases by this examiner. Grant probability derived from career allowance rate.

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