CTNF 18/441,352 CTNF 97639 Detailed Action Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statements (IDS) submitted on April 8 th , 2024, and July 1 st , 2024, were filed prior to the mailing date of the first office action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner. Claim Rejections - 35 USC § 112 07-30-01 AIA The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. 07-31-01 Claim 3 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. In this instance, Claim 3 recites the limitation “etching the seed layer reduces an area number density of the particles in producing the etched particles”. Applicant has already defined that “etching the seed layer produces etched particles” in line 4 of Claim 1 . Applicant is seemingly claiming that the process that produces the etched particles also reduces their average size. However, applicant’s filed specification states ([0050]) that the etching operation reduces an averages size of the particles to produce the etched particles. In other words, the operation changes the particles into etched particles, but does not support reducing the size of the etched particles. 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claim 3 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 3 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being incomplete for omitting essential steps, such omission amounting to a gap between the steps. See MPEP § 2172.01. The omitted steps are the connection or transition between the particles and the etched particles. These steps are critical in defining if the particles and etched particles are the same particles and how they exist in relation to the overall substrate processing method. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-2, 7-9, 12-15, and 17-19 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Makala et al. (2020/0279868 A1; hereinafter Makala ) . Regarding Claim 1, Makala (figs. 7-12) teaches a substrate processing method ([0004], method of forming a memory device) , comprising: depositing a seed layer ([0135], 602, see fig. 10C) of particles ([0127], includes silicon) onto a floor and a sidewall of a memory hole ([0125], bottom and sidewalls of 49, see fig. 7A) extending through a memory stack ([0101], stack of 32L and 42L, see fig. 7A) ; etching the seed layer ([0137], 602 is etched to form gap 469, see fig. 11B) to produce etched particles (remainder of 602, see fig. 11B) ; and growing crystals ([0170], 603 may be polysilicon) on the floor and on the sidewall of the memory hole (bottom and sidewalls of 49, see fig. 12A) , wherein the etched particles (remainder of 602) act as nuclei for growing the crystals ([0139], remainder of 602 functions as a growth template or seed) . Regarding Claim 2, Makala (figs. 7-12) teaches the method of claim 1, wherein etching the seed layer (602) reduces an area number density of the particles (area of 602 decreases in the etching process, see figs. 10D and 11B) in producing the etched particles. Regarding Claim 7, Makala (figs. 7-12) teaches the method of claim 1, wherein the crystals in the memory hole form a layer (603) surrounding a void ([0137], region where 62 is formed, see fig. 11A) . Regarding Claim 8, Makala (figs. 7-12) teaches the method of claim 7, further comprising depositing a core material (62) in the void (region where 62 is formed) . Regarding Claim 9, Makala (figs. 7-12) teaches the method of claim 8, wherein the crystals are silicon (603 may be polysilicon) , and the core material is a silicon oxide ([0128], 62 may be silicate glass which includes silicon oxide) . Regarding Claim 12, Makala (figs. 7-12) teaches a substrate processing method ([0004], method of forming a memory device) , comprising: depositing a seed layer ([0135], 602, see fig. 10C) of particles ([0127], includes silicon) onto a dielectric material ([0122], 56 may be silicon oxide, see fig. 10C) lining a memory hole ([0125], bottom and sidewalls of 49, see fig. 7A) extending through a memory stack ([0101], stack of 32L and 42L, see fig. 7A) disposed on a front side of a substrate ([0096], top of 10, see fig. 10C) ; etching the seed layer ([0137], 602 is etched to form gap 469, see fig. 11B) to produce etched particles (remainder of 602, see fig. 11B) ; and growing crystals ([0170], 603 may be polysilicon) on the floor and on the sidewall of the memory hole (bottom and sidewalls of 49, see fig. 12A) , wherein the etched particles (remainder of 602) act as nuclei for growing the crystals ([0139], remainder of 602 functions as a growth template or seed) . Regarding Claim 13, Makala (figs. 7-12) teaches the method of claim 12, wherein the memory hole (49) includes a lower portion ([0117], portion of 49 that extends into 10) extending into the substrate (10) . Regarding Claim 14, Makala (figs. 7-12) teaches the method of claim 13, wherein a portion of the seed layer (602) is deposited in the lower portion (602 fills the bottom of 49, see fig. 10C) of the memory hole (49) . Regarding Claim 15, Makala (figs. 7-12) teaches the method of claim 14, wherein a crystal of the plurality of crystals (603 may be polysilicon) is grown in the lower portion (603 fills the bottom of 49, see fig. 12A) of the memory hole (49) . Regarding Claim 17, Makala (figs. 7-12) teaches the method of claim 12, wherein the crystals in the memory hole form a layer (603) surrounding a void ([0137], region where 62 is formed, see fig. 11A) . Regarding Claim 18, Makala (figs. 7-12) teaches the method of claim 16, further comprising depositing a core material (62) in the void (region where 62 is formed) . Regarding Claim 19, Makala (figs. 5-12) teaches a method of manufacturing a memory device ([0004], method of forming a memory device) , comprising: forming a memory stack ([0101], stack of 32L and 42L, see fig. 7A) on a front side of a substrate ([0096], top of 10, see fig. 10C) ; forming a memory hole ([0115], 49, see fig. 5A) through the memory stack (stack of 32L and 42L) and into the substrate ([0117], portion of 49 that extends into 10) ; and placing a channel material ([0170], 603) in the memory hole (49) within the memory stack (stack of 32L and 42L) and within the substrate (10) by: depositing a seed layer ([0135], 602, see fig. 10C) of particles ([0127], includes silicon) onto a dielectric material ([0122], 56 may be silicon oxide, see fig. 10C) in the memory hole (49) ; etching the seed layer ([0137], 602 is etched to form gap 469, see fig. 11B) to produce etched particles (remainder of 602, see fig. 11B) ; and growing crystals ([0170], 603 may be polysilicon) in the memory hole (bottom and sidewalls of 49, see fig. 12A) , wherein the etched particles (remainder of 602) act as nuclei for growing the crystals ([0139], remainder of 602 functions as a growth template or seed) . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Rejection Note: Italicized claim limitations indicate that the corresponding limitations are addressed with a secondary reference/embodiment in an obviousness analysis. 07-22-aia AIA Claim s 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Makala as applied to Claim 1 above, and further in view of Ping (6235605 B1; hereinafter Ping ) . Regarding Claim 4, Makala doesn’t teach the method of claim 1, wherein etching the seed layer comprises exposing the seed layer to hydrochloric acid. However, Ping (fig. 2A) teaches etching the seed layer (Col. 4, Lines 30-31; 23) comprises exposing the seed layer (23) to hydrochloric acid (Col. 3, Lines 9-20; HCL may be used as a silicon-stripping agent) . Ping also teaches that HCL effectively strips silicon (Col. 3, Lines 9-20) Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Makala to include the hydrochloric acid of Ping to effectively strip silicon. Regarding Claim 5, Makala (figs. 7-12) teaches the method of claim 1, wherein: the seed layer (602) and the crystals (603) comprise silicon ([0170]) ; and depositing the seed layer comprises exposing the memory hole to a silicon precursor in a hydrogen environment at about 400 °C to about 1100 °C. Makala doesn’t teach depositing the seed layer comprises exposing the memory hole to a silicon precursor in a hydrogen environment at about 400 °C to about 1100 °C. However, Ping (fig. 2A) teaches depositing the seed layer (Col. 4, Lines 30-31; 23) comprises exposing the memory hole (hole where 23 is formed) to a silicon precursor (Col. 3, Lines 9-20; silane) in a hydrogen environment (Col. 4; Lines 62-63; H2 gas) at about 400 °C to about 1100 °C (Col. 4, Lines 59-61; 560 to 650 C) . Ping also teaches that this forms a quality hemispherical grain silicon (Col. 4, Lines 52-55). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Makala to include the method of forming a silicon layer of Ping to form a quality hemispherical grain silicon. Regarding Claim 6, Ping (figs. 2A) teaches the method of claim 5, wherein the silicon precursor includes at least one of silane (Col. 3, Lines 9-20; silane) , dichlorosilane (DCS), trichlorosilane (TCS), or a silene . 07-22-aia AIA Claim s 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Makala as applied to Claim 1 above, and further in view of Kim (2017/0330752 A1; hereinafter Kim ) . Regarding Claim 10, Makala doesn’t teach the method of claim 1, further comprising performing an annealing operation on the memory stack at about 500 °C to about 1200 °C for a duration ranging from about 1 minute to about 3 hours. However, Kim (fig. 7E) teaches performing an annealing operation ([0063]) on the memory stack ([0059], stack of 71 and 72) at about 500 °C to about 1200 °C ([0063], ranges from 350 to 650 C) for a duration ranging from about 1 minute to about 3 hours ([0063], may range from two to four hours) . Kim also teaches that this controls the channel layer crystallization and increasing grain size ([0063]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Makala to include the annealing of Ping to control channel crystallization and increase grain size. Regarding Claim 11, Kim (fig. 7E) teaches the method of claim 10, wherein the annealing operation is performed: between depositing the seed layer and growing the crystals; or after growing the crystals ([0063], annealing occurs after channel layer 76 is formed) . 07-22-aia AIA Claim s 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Makala as applied to Claim s 15 and 19 above, and further in view of Oh et al. (2022/0359564 A1; hereinafter Oh ) . Regarding Claim 16, Makala doesn’t teach the method of claim 15, further comprising removing a portion of the substrate from a back side of the substrate opposite the front side, thereby exposing the crystal grown in the lower portion of the memory hole. However, Oh (figs. 10-11) teaches removing a portion of the substrate ([0117], portion of 101L is removed, see fig. 10 and 11A) from a back side (top of 101L, see fig. 10) of the substrate (101L) opposite the front side (bottom side of PMCA, see fig. 10) , thereby exposing the crystal ([0116], 123) grown in the lower portion of the memory hole (123 in portion AR2, see figs. 10 and 11A) . Oh also teaches that this process may be used to form a common source layer ([0060]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Makala to include the removing of the substrate of Oh to form a common source layer. Regarding Claim 20, Makala doesn’t teach the method of claim 19, further comprising removing a portion of the substrate from a back side of the substrate opposite the front side, thereby exposing a portion of the channel material within the substrate. However, Oh (figs. 10-11) teaches removing a portion of the substrate ([0117], portion of 101L is removed, see fig. 10 and 11A) from a back side (top of 101L, see fig. 10) of the substrate (101L) opposite the front side (bottom side of PMCA, see fig. 10) , thereby exposing the a portion of the channel material ([0116], 123) within the substrate (123 in portion AR2, see figs. 10 and 11A) . Oh also teaches that this process may be used to form a common source layer ([0060]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Makala to include the removing of the substrate of Oh to form a common source layer. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADIN HRNJIC whose telephone number is (571)270-1794. The examiner can normally be reached Monday-Friday 8:00 AM - 4:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /A.H./Examiner, Art Unit 2817 /Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 Application/Control Number: 18/441,352 Page 2 Art Unit: 2817 Application/Control Number: 18/441,352 Page 3 Art Unit: 2817
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