DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites “the tensile stressed metal fill is characterized by a compressive stress of greater than or about 350 MPa.” It is unclear what, if any, weight is to be given the term “tensile stress metal” if the material is characterized by having a compressive stress instead of a tensile stress.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhou et al. (U.S. Publication No. 2020/0126867) in view of Li (CN 113964037).
Regarding claim 1, Zhou teaches a semiconductor device, comprising:
a substrate (Fig. 2, substrate 22);
a source region (23P);
a drain region (23P);
a channel region (not labeled, but below gate 36 and between S/D 23P) comprising at least one channel located between the source region and the drain region (Fig. 2);
a first gate region (upper level including gate 36) comprising a self-aligned single diffusion break (SDB 44/38’; see paragraph [0040], can be single) in a p-MOS region (PFET, Fig. 2), wherein the self-aligned single diffusion break comprises a dielectric material liner (liner 25/38’) and a stressed metal fill (stressed metal fill 44), and wherein the stressed metal fill is characterized by a compressive stress of greater than or about 350 MPa (paragraph [0044]); and
a second gate region in a n-MOS region (NFET region in Fig. 2) comprising at least a first gate (gate 36) enclosing the channel between the source region and the drain region (Fig. 2).
Zhou teaches that the SDB is formed by fin cut, but does not teach sufficient detail about the initial formation steps of the SDB to determine if it is a self aligned process or not. However, Li teaches that a fin cut SDB can be done in a self-aligned process (Li translation page 1, Abstract). It would have been obvious to a person of skill in the art at the time of the effective filing date that a self-aligned process could have been used because Li teaches that this allows for greater control over process changes (Abstract).
Regarding claim 3, Zhou in view of Li teaches the semiconductor device of claim 1, further comprising a third gate region (see Fig. 1, several adjacent gate regions at 28/30 separate by gate cuts CT), wherein the second gate region is disposed between the first gate region and the third gate region (there is at least one gate region between a PFET gate region 30 and and NFET gate region 28), and wherein the third gate region comprises a second self-aligned single diffusion break (see Fig. 2, NFET and PFET both contain diffusion breaks).
Regarding claim 4, Zhou in view of Li teaches the semiconductor device of claim 1, wherein the stressed metal fill material is selected from aluminum and aluminum-containing materials, tungsten and tungsten- containing materials, copper and copper-containing materials, titanium and titanium-containing materials, tantalum and tantalum-containing materials, nickel and nickel-containing materials, cobalt and cobalt-containing materials, ruthenium and ruthenium-containing materials, molybdenum and molybdenum-containing materials, an oxide of a metal having a Pilling- Bedworth ratio of about 1.5 or greater, or combinations thereof (see paragraph [0044]).
Regarding claim 5, Zhou in view of Li teaches the semiconductor device of claim 3, wherein the channel region comprises a plurality of horizontally extending channels (Fig. 1-2, channels are on fins 22).
Regarding claim 6, Zhou in view of Li teaches the semiconductor device of claim 5, wherein the semiconductor device is a nanosheet field-effect transistor or a complementary field-effect transistor (CMOS, see paragraph [0027]) and/or wherein the semiconductor device is a gate-all-around complementary metal-oxide- semiconductor.
Regarding claim 7, Zhou in view of Li teaches the semiconductor device of claim 1, wherein the dielectric material liner is characterized by a thickness of about 1 nm to less than or about 6 nm (paragraph [0035] and [0044], 39 and 38 are approximately same thickness, and around 2-10 nm) .
Regarding claim 8, Zhou in view of Li teaches the semiconductor device of claim 3, wherein the third gate region comprises a third self-aligned diffusion break, the third self-aligned diffusion break comprising a compressive stressed metal fill characterized by a compressive stress of greater than or about 350 MPa (third gate region can be another PFET).
Regarding claim 10, Zhou in view of Li teaches the semiconductor device of claim 1, wherein the self-aligned diffusion break defines a volume, and wherein the stressed metal fill and the dielectric liner occupy greater than or about 95 vol.% of the volume (100%, Fig. 2).
Regarding claim 11, Zhou in view of Li teaches the semiconductor device of claim 10, wherein the stressed metal fill is generally free of voids or seams (Fig. 2).
Regarding claim 12, Zhou in view of Li teaches the semiconductor device of claim 11, wherein the stressed metal fill and dielectric liner occupy greater than or about 99 vol% of the volume (100%, Fig. 2).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Zhou in view of Li, further in view of Liu et al. (WO 2023/108398).
Regarding claim 2, Zhou in view of Li teaches the semiconductor device of claim 1, but does not specifically teach wherein the channel region is characterized by a compressive stress of greater than or about 250 MPA.
However, Liu teaches a similar device in which the channel stress caused by a SDB structure is above 250 MPa (see Liu translation page 9, stress in channel is held approximately 2/3 the level of stress in SDB). It would have been obvious to a person of skill in the art at the time of the effective filing date that the SDB of Zhou would have also imparted stress on the channel region in a similar range, and because the stress of the SDB is up to 10 GPa, the stress in the channel would also be at least 250 MPa.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Evan G Clinton whose telephone number is (571)270-0525. The examiner can normally be reached Monday-Friday at 8:30am to 5:30pm.
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/EVAN G CLINTON/Primary Examiner, Art Unit 2899
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