DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-10 and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou et al. (U.S. Publication No. 2020/0126867) in view of Li (CN113964037).
Regarding claim 1, Zhou teaches a semiconductor device, comprising:
a substrate (Fig. 2, substrate 22);
a source region (23P);
a drain region (23P);
a channel region (not labeled, but below gate 36 and between S/D 23P) comprising at least one channel located between the source region and the drain region (Fig. 2);
a first gate region (NFET region) comprising a first self-aligned single diffusion break (24) in a n-MOS region (NFET), wherein the first self-aligned single diffusion break comprises a first liner (liner 38) and a first fill material (40); and
a second gate region (PFET region) comprising a second self-aligned single diffusion break (also labeled 24) in a p-MOS region (PFET), wherein the second self-aligned single diffusion break comprises a compressive stressed fill material , and wherein compressive stressed fill material (compressive stress material 44) is characterized by a compressive stress of greater than or about 350 MPa (paragraph [0044]).
Zhou teaches that the SDB is formed by fin cut, but does not teach sufficient detail about the initial formation steps of the SDB to determine if it is a self aligned process or not. However, Li teaches that a fin cut SDB can be done in a self-aligned process (Li translation page 1, Abstract). It would have been obvious to a person of skill in the art at the time of the effective filing date that a self-aligned process could have been used because Li teaches that this allows for greater control over process changes (Abstract).
Regarding claim 2, Zhou in view of Li teaches the semiconductor device of claim 1, where the first fill material is a neutral stressed material or a tensile stressed material (paragraph [0040]).
Regarding claim 3, Zhou in view of Li teaches the semiconductor device of claim 2, wherein the first fill material, the compressive stressed fill material, or both the first fill material and the compressive stressed fill material comprises a dielectric fill material (first material is dielectric, paragraph [0039]).
Regarding claim 5, Zhou in view of Li teaches the semiconductor device of claim 3, wherein the dielectric fill material comprises silicon nitride, a silicon oxynitride, silicon dioxide, or a combination thereof (paragraph [0039], SiO2).
Regarding claim 6, Zhou in view of Li teaches the semiconductor device of claim 1, wherein the second self-aligned single diffusion break comprises a second liner (Fig. 2, liner 38’).
Regarding claim 7, Zhou in view of Li teaches the semiconductor device of claim 6, wherein the first liner, the second liner, or both the first liner and the second liner comprise a dielectric liner material (paragraph [0035]).
Regarding claim 8, Zhou in view of Li teaches the semiconductor device of claim 7, wherein the dielectric liner material comprises silicon nitride, a silicon oxynitride, silicon dioxide, or a combination thereof (paragraph [0035]).
Regarding claim 9, Zhou in view of Li teaches the semiconductor device of claim 7, wherein the dielectric liner material of the first liner has an etch rate that is different than an etch rate of the first fill material (paragraph [0043]).
Regarding claim 10, Zhou in view of Li teaches the semiconductor device of claim 7, wherein the dielectric liner material of the second liner is selected from a same material or a different material from the compressive stressed fill material (it is inherent that it is either a same material or a different material because these are the only two options).
Regarding claim 12, Zhou in view of Li teaches the semiconductor device of claim 11, wherein the first fill material comprises silicon nitride, silicon dioxide, or a combination thereof (paragraph [0039]), wherein the compressive stressed fill material is different than the first fill material (paragraph [0044]).
Regarding claim 13, Zhou in view of Li teaches the semiconductor device of claim 1, wherein the semiconductor device is a nanosheet field-effect transistor or a complementary field-effect transistor (paragraph [0027] and Fig. 2, CMOS) and/or wherein the semiconductor device is a gate-all-around complementary metal-oxide- semiconductor.
Claims 4 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou in view of Li, further in view of Hong et al. (U.S. Publication No. 2022/0302172).
Regarding claim 4, Zhou in view of Li teaches the semiconductor device of claim 3, wherein the first fill material and the compressive stressed fill material both comprise dielectric fill materials, wherein the first fill material is different from the compressive stressed fill material.
Zhou teaches that the first fill material is SiO2 (paragraph [0039]), but does not teach that the second fill is a dielectric different than SiO2. However, Hong teaches a compressive diffusion break can be SiN (paragraph [0070]). It would have been obvious to a person of skill in the art at the time of the effective filing date that the compressive fill 44 of Zhou could have been SiN because it would have been a simple substitution of one known compressive diffusion break fill material for another with predictable results.
Regarding claim 11, Zhou in view of Li teaches the semiconductor device of claim 7, wherein the second liner comprises silicon nitride, silicon dioxide, or a combination thereof (paragraph [0044]), but does not teach the compressive stressed fill material comprises silicon dioxide, silicon nitride, or a combination thereof. However, Hong teaches a compressive diffusion break can be SiN (paragraph [0070]). It would have been obvious to a person of skill in the art at the time of the effective filing date that the compressive fill 44 of Zhou could have been SiN because it would have been a simple substitution of one known compressive diffusion break fill material for another with predictable results.
Conclusion
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/EVAN G CLINTON/Primary Examiner, Art Unit 2899
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