Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
Replacement drawing sheets for figure 1 have been filed by applicant and are only correcting a defect in the originally filed drawings. The replacement drawings were received on 7/8/2026. These drawings are acceptable.
Claim Objections
Claim 2 is objected to because of the following informalities: “thickness” in line 6. For the sake of compact prosecution, claim 7 is interpreted in the instant Office action as follows: “thickness” is found to be a typographical error and is believed to be equivalent to “a thickness”; however, no actual change to the claim language has been applied during examination of the instant set of claims. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference (or combination of references), but are disclosed or rendered obvious by secondary references or remarks.
Claims 1-9, 12-17, and 20-22 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 20210118827 A1) in view of Chiang (US 20230008792 A1).
Regarding claim 1, Chen discloses a semiconductor device (Fig. 3K) comprising:
a first semiconductor layer (110; [0043]: “semiconductor substrate”);
a second semiconductor layer (210; [0026]: “semiconductor substrate”);
an inductor structure (140/160/240/260; [0032]: “inductor patterns”) vertically between (See annotated figure for “vertically” direction designation) the first semiconductor layer and the second semiconductor layer,
the inductor structure having a first metal level (160) and a second metal level (260) above the first metal level (See annotated figure for “above” direction designation), the first metal level and the second metal level each comprises at least one turn (See Fig. 4B which is an exploded perspective view, and shows levels 140/160 and 240/260 each have multiple turns) about a vertical axis (See annotated Fig. 4B for “vertical” direction designation, which is consistent with annotated Fig. 3K);
a dielectric region (180/150/280/250) vertically between (sandwiched between) the first and second metal levels of the inductor structure;
a first interconnect via (194/192) in the dielectric region,
the first interconnect via has a height defined as a vertical distance between an uppermost surface of the first interconnect via and a lowermost surface of the first interconnect via (See annotated Fig. 3K for height measurement endpoints), and
the first interconnect via electrically contacts the first metal level of the inductor structure (Fig. 4B: via 194/192 electrically contacts level 160); and
a second interconnect via (294/292) in the dielectric region,
the second interconnect via directly contacts the first interconnect via (direct contact at 292/192),
the second interconnect via has a height defined as a vertical distance between an uppermost surface of the second interconnect via and a lowermost surface of the second interconnect via (See annotated Fig. 3K for height measurement endpoints),
the height of the second interconnect via is different from the height of the first interconnect via, and
the second interconnect via electrically contacts the second metal level of the inductor structure (Fig. 4B: via 294/292 electrically contacts level 260).
Illustrated below is a marked and annotated figures of Figs. 3K and 4B of Chen.
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Chen fails to teach “the height of the second interconnect via is different from the height of the first interconnect via” because Chen fails to teach any specific height ranges for either of the vias, and fails to teach any required relation among these via heights.
Chiang teaches the height of the second interconnect via (Fig. 6: height T2 of via 126) is different from ([0022]: “The thickness T3 is larger than the thickness T2”) the height of the first interconnect via (height T3 of via 226). Modifying the via height configuration (of Chen) by incorporating the configuration of Chiang would arrive at the claimed height configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the vias are directly bonded connectors (Chen: [0039]: “hybrid bonded”; Chiang: [0026]: “bonding process”). Chiang provides a teaching to incorporate the claimed height configuration in that it would enable enhanced bonding characteristics ([0026]: “improved bonding quality between the first bonding pads 126 of the first device wafer 100 and the second bonding pads 226 of the second device wafer 200 may be achieved”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed height configuration because it would enable enhanced bonding characteristics. MPEP 2143 (I)(G).
Illustrated below is Fig. 6 of Chiang.
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Regarding claim 2, Chen in view of Chiang discloses the semiconductor device of claim 1 (Chen: Fig. 3K),
wherein the dielectric region includes a first interlayer dielectric level (180 with 150) and a second interlayer dielectric level (280 with 250) directly on the first interlayer dielectric level,
the first interlayer dielectric level has a thickness defined as a vertical distance between an uppermost surface of the first interlayer dielectric level and a lowermost surface of the first interlayer dielectric level (Chen: Fig. 3K: “vertical distance” of level 180/150 matches the via height of 194/192. This distance corresponds to Chiang: Fig. 6: level 122 which matches the via height of 126),
the second interlayer dielectric level has thickness defined as a vertical distance between an uppermost surface of the second interlayer dielectric level and a lowermost surface of the second interlayer dielectric level (Chen: Fig. 3K: “vertical distance” of level 280/250 matches the via height of 294/292. This distance corresponds to Chiang: Fig. 6: level 222/224/124 which matches the via height of 226),
wherein the second interlayer dielectric level has a different thickness from the first interlayer dielectric level (“different thickness” is reasoned here because these thicknesses correspond to the via height difference rendered obvious in the claim 1 rejection.).
Regarding claim 3, Chen in view of Chiang discloses the semiconductor device of claim 2 (Chen: Fig. 3K), wherein the first interconnect via is in the first interlayer dielectric level (completely in) and the second interconnect via is in the second interlayer dielectric level (completely in).
Regarding claim 4, Chen in view of Chiang discloses the semiconductor device of claim 3 (Chen: Fig. 3K), wherein the first interconnect via has sidewalls (vertical sidewalls of 194), the second interconnect via has sidewalls (vertical sidewalls of 292), and the sidewalls of the first interconnect via are horizontally offset (See annotated figure for direction designation) relative to the sidewalls of the second interconnect via.
Regarding claim 5, Chen in view of Chiang discloses the semiconductor device of claim 3 (Chen: Fig. 3K), wherein the first interconnect via has sidewalls (vertical sidewalls of 194), the second interconnect via has sidewalls (vertical sidewalls of 294), and the sidewalls of the first interconnect via are aligned vertically (perfectly aligned) with the sidewalls of the second interconnect via.
Regarding claim 6, Chen in view of Chang discloses the semiconductor device of claim 3 (Chen: Fig. 3K), further comprising: a first transistor (D1; [0020]: “transistors or the like”) on the first semiconductor layer, wherein the first metal level of the inductor structure is electrically connected to the first transistor ([0056]: “connected to the devices D1”); and a second transistor (D2; [0026]: “devices D2” reasonably includes the same definition as D1 because Chen describes the feature in the same way as D1; [0020]: “transistors or the like”) on the second semiconductor layer, wherein the second metal level of the inductor structure is electrically connected to the second transistor ([0058]: “connected to the devices D2”).
Regarding claim 7, Chen in view of Chang discloses the semiconductor device of claim 6 (Chen: Fig. 3K), further comprising: a first semiconductor die (100) including the first interlayer dielectric level, the first transistor, the first semiconductor layer, the first metal level of the inductor structure, and the first interconnect via (these features are all cited above and are within 100); and a second semiconductor die (200) including the second interlayer dielectric level, the second transistor, the second semiconductor layer, the second metal level of the inductor structure, and the second interconnect via (these features are all cited above and are within 200).
Regarding claim 8, Chen in view of Chiang discloses the semiconductor device of claim 7 (Chen: Fig. 3K), wherein the first interlayer dielectric level is bonded (directly bonded; [0039]: “hybrid bonded”) to the second interlayer dielectric level and the first interconnect via is bonded (directly bonded; [0039]: “hybrid bonded”) to the second interconnect via.
Regarding claim 9, Chen in view of Chiang discloses the semiconductor device of claim 6 (Chen: Fig. 3K), wherein the first transistor has a gate structure ([0020]: “transistors or the like”. Note: “a gate structure” of some generic kind is a necessary structure that is encompassed within the classical definition of a transistor.), the second transistor has a gate structure ([0020]: “transistors or the like”. Note: “a gate structure” of some generic kind is a necessary structure that is encompassed within the classical definition of a transistor.), and the gate structure of the first transistor is vertically aligned above the gate structure of the second transistor (D1 and D2 are fully overlapping in the vertical direction, thus their respective components are vertically aligned within the breadth of the claim).
Regarding claim 21, Chen in view of Chiang discloses the semiconductor device of claim 1 (Chen: Fig. 4B), wherein the first metal level of the inductor structure includes an innermost end (1621) and an outermost end (1622), and the first interconnect via contacts (at least indirectly “contacts”) the innermost end of the first metal level.
Regarding claim 22, Chen in view of Chiang discloses the semiconductor device of claim 21, further comprising
a first transistor (D1; [0020]: “transistors or the like”) on the first semiconductor layer, wherein the first metal level of the inductor structure is electrically connected to the first transistor ([0056]: “connected to the devices D1”);
a second transistor (D2; [0020]: “transistors or the like” reasonably interpreted in the same way as D1 because these devices are similarly described in [0026] and similarly illustrated in Fig. 3K) on the second semiconductor layer, wherein the second metal level of the inductor structure is electrically connected to the second transistor ([0058]: “connected to the devices D2”); and
a via structure ([0056]: “inductor via”) that contacts (at least indirectly “contacts”) the outermost end of the first metal level of the inductor structure, the via structure electrically connects ([0056]: “may be connected to the devices”) the first metal level of the inductor structure to the first transistor.
Regarding independent claim 12, Chen discloses a semiconductor device (Fig. 3K) comprising:
a first semiconductor die (100) having a first interlayer dielectric level (180 with 150),
the first interlayer dielectric level having a thickness defined as a vertical distance between an uppermost surface of the first interlayer dielectric level and a lowermost surface of the first interlayer dielectric level (Chen: Fig. 3K: “vertical distance” of level 180/150 matches the via height of 194/192. This distance corresponds to Chiang: Fig. 6: level 122 which matches the via height of 126, cited below.);
a first integrated circuit (IC) component (D1; [0020]: “transistors or the like”) in the first semiconductor die;
a second semiconductor die (200) vertically above the first semiconductor die (See annotated figure for direction designation), the second semiconductor die having a second interlayer dielectric level (280 with 250),
the second interlayer dielectric level having a thickness defined as a vertical distance between an uppermost surface of the second interlayer dielectric level and a lowermost surface of the second interlayer dielectric level (Chen: Fig. 3K: “vertical distance” of level 280/250 matches the via height of 294/292. This distance corresponds to Chiang: Fig. 6: level 222/224/124 which matches the via height of 226, cited below.),
the second interlayer dielectric level directly contacts the first interlayer dielectric level (direct contact is illustrated), and
the second interlayer dielectric level has a different thickness from the first interlayer dielectric level;
a second IC component (D2; [0026]: “devices D2” reasonably includes the same definition as D1 because Chen describes the feature in the same way as D1; [0020]: “transistors or the like”) in the second semiconductor die;
an inductor structure (140/160/240/260; [0032]: “inductor patterns”) vertically between (sandwiched between) the first IC component and the second IC component,
the inductor structure having a first metal level (160) in the first semiconductor die and a second metal level (260) in the second semiconductor die,
the first metal level is electrically connected to the first IC component ([0056]: “connected to the devices D1”), and
the second metal level is electrically connected to the second IC component ([0058]: “connected to the devices D2”),
the first metal level and the second metal level each comprises at least one turn (See Fig. 4B which is an exploded perspective view, and shows levels 140/160 and 240/260 each have multiple turns) about a vertical axis (See annotated Fig. 4B for direction designation, which is consistent with annotated Fig. 3K);
a first interconnect via (194/192) in the first interlayer dielectric level, the first interconnect via electrically contacts the first metal level of the inductor structure (Fig. 4B: via 194/192 electrically contacts level 160); and
a second interconnect via (294/292) in the second interlayer dielectric level, the second interconnect via directly contacts the first interconnect via (direct contact at 292/192), and the second interconnect via electrically contacts the second metal level of the inductor structure (Fig. 4B: via 294/292 electrically contacts level 260).
Chen fails to teach “the second interlayer dielectric level has a different thickness from the first interlayer dielectric level” because Chen fails to teach any specific thickness ranges for either of the dielectric levels, and fails to teach any required relation among these level thicknesses.
Chiang teaches the second interlayer dielectric level (Fig. 6: thickness of level 122 matches the height T2 of via 126) has a different thickness from ([0022]: “The thickness T3 is larger than the thickness T2”) the first interlayer dielectric level (thickness of level 222/224/124 matches the height T3 of via 226). Modifying the level thickness configuration (of Chen) by incorporating the configuration of Chiang would arrive at the claimed thickness configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the levels are incorporated with directly bonded connectors (Chen: [0039]: “hybrid bonded”; Chiang: [0026]: “bonding process”). Chiang provides a teaching to incorporate the claimed thickness configuration in that it would enable enhanced bonding characteristics ([0026]: “improved bonding quality between the first bonding pads 126 of the first device wafer 100 and the second bonding pads 226 of the second device wafer 200 may be achieved”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed thickness configuration because it would enable enhanced bonding characteristics. MPEP 2143 (I)(G).
Regarding claim 13, Chen in view of Chiang discloses the semiconductor device of claim 12 (Chen: Fig. 3K), wherein the first interconnect via, the second interconnect via, the first interlayer dielectric level, and the second interlayer dielectric level are vertically between (sandwiched between) the first metal level of the inductor structure and the second metal level of the inductor structure.
Regarding claim 14, Chen in view of Chiang discloses the semiconductor device of claim 13 (Chen: Fig. 3K), wherein the first interconnect via has sidewalls (vertical sidewalls of 194), the second interconnect via has sidewalls (vertical sidewalls of 292), and the sidewalls of the first interconnect via are horizontally offset (See annotated figure for direction designation) relative to the sidewalls of the second interconnect via.
Regarding claim 15, Chen in view of Chiang discloses the semiconductor device of claim 13 (Chen: Fig. 3K), wherein the first interconnect via has sidewalls (vertical sidewalls), the second interconnect via has sidewalls (vertical sidewalls), and the sidewalls of the first interconnect via are aligned vertically (perfectly aligned) with the sidewalls of the second interconnect via.
Regarding claim 16, Chen in view of Chiang discloses the semiconductor device of claim 12 (Chen: Fig. 3K), wherein the inductor structure has a center region (See annotated Fig. 4B for region designation), and wherein the at least one turn in the first metal level and the at least one turn in the second metal level spiral about the center region of the inductor structure.
Regarding claim 17, Chen in view of Chiang discloses the semiconductor device of claim 12 (Chen: Fig. 3K), wherein the first IC component includes a first transistor ([0020]: “transistors or the like”) connected to the first metal level of the inductor structure ([0056]: “connected to the devices D1”), and the second IC component includes a second transistor ([0026]: “devices D2” reasonably includes the same definition as D1 because Chen describes the feature in the same way as D1; [0020]: “transistors or the like”) connected to the second metal level of the inductor structure ([0058]: “connected to the devices D2”).
Regarding claim 20, Chen in view of Chiang discloses the semiconductor device of claim 12 (Chen: Fig. 3K), wherein the first interconnect via has a height (See annotated Fig. 3K for height measurement endpoints), and the second interconnect via has a height (See annotated Fig. 3K for height measurement endpoints) different from the height of the first interconnect via (“different from the first height” is reasoned here because these heights correspond to the thickness difference rendered obvious in the claim 12 rejection.).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Chiang as applied to claims 9, 6, 3, 2, and 1 above, and further in view of Zhang (US 20120187530 A1).
Regarding claim 10, Chen in view of Chiang discloses the semiconductor device of claim 9 (Chen: Fig. 3K), wherein the inductor structure has a center region (See annotated Fig. 4B for region designation), and wherein the gate structure of the first transistor and the gate structure of the second transistor are vertically aligned with the center region of the inductor structure.
Chen fails to teach the transistor arrangement “wherein the gate structure of the first transistor and the gate structure of the second transistor are vertically aligned with the center region of the inductor structure” because Chen teaches an arrangement with these transistors horizontally offset from the center region.
Zhang discloses a transistor arrangement (Fig. 5E), wherein the gate structure of the first transistor (See annotated figure; [0060]: “transistors 56”) and the gate structure of the second transistor (See annotated figure; [0060]: “transistors 56”) are vertically aligned (See annotated figure for direction designation) with the center region of the inductor structure. Modifying the transistor arrangement of Chen by incorporating the alternative arrangement disclosed by Zhang would arrive at the claimed arrangement. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the transistors are vertically sandwiching the inductor. Therefore, it would have been obvious to have the claimed arrangement because it is a rearrangement of parts using an arrangement disclosed elsewhere in the prior art. MPEP 2144.04 (VI)(C).
Illustrated below is a marked and annotated figure of Fig. 5E of Zhang.
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Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Chiang as applied to claim 12 above, and further in view of Zhang.
Regarding claim 19, Chen in view of Chiang discloses the semiconductor device of claim 12 (Chen: Fig. 3K), but fails to teach the IC component arrangement “wherein the first IC component, the second IC component, the first metal level of the inductor structure, and the second metal level of the inductor structure are aligned vertically along the vertical axis” because Chen teaches an arrangement with these IC components horizontally offset from the vertical axis.
Zhang discloses an IC component arrangement (Fig. 5E), wherein the first IC component (See annotated figure; [0060]: “transistors 56”), the second IC component (See annotated figure; [0060]: “transistors 56”), the first metal level of the inductor structure (74), and the second metal level of the inductor structure (74) are aligned vertically along the vertical axis (annotated as Center Region, See annotated figure for direction designation). Modifying the IC component arrangement of Chen by incorporating the alternative arrangement disclosed by Zhang would arrive at the claimed arrangement. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the IC components are vertically sandwiching the inductor. Therefore, it would have been obvious to have the claimed arrangement because it is a rearrangement of parts using an arrangement disclosed elsewhere in the prior art. MPEP 2144.04 (VI)(C).
Response to Arguments
Applicant's arguments filed 7/8/2026 have been fully considered but they are not persuasive.
Applicant argues:
Applicant argues with respect to amended claims 1 and 12 that “”. Remarks at pg. 12.
Examiner’s reply:
Applicant’s arguments with respect to claim(s) 1 and 12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The examiner finds Applicant’s amendments describing the height measurements in a way overcoming the prior rejections (Chen). However, the instant Office action relies upon a new reference (Chiang) to render obvious the contended height configuration. The examiner has relied upon MPEP 2143 (I)(G) for guidance rendering the limitation obvious. However, the examiner has also considered guidance from MPEP 2141 (II)(A)(2): “solves a problem which is different from that which the inventor was trying to solve, may also be considered for the purposes of 35 U.S.C. 103” and MPEP 2144.04 (IV)(A): “Changes in Size/Proportion”.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
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