Prosecution Insights
Last updated: October 01, 2026
Application No. 18/442,381

HIGH VOLTAGE DEVICE WITH BOOSTED BREAKDOWN VOLTAGE

Non-Final OA §102§103
Filed
Feb 15, 2024
Priority
Jun 21, 2021 — provisional 63/212,955 +1 more
Examiner
GUPTA, RAJ R
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
69%
Grant Probability
Favorable
1-2
OA Rounds
4m
Est. Remaining
82%
With Interview

Examiner Intelligence

Grants 69% — above average
69%
Career Allowance Rate
432 granted / 629 resolved
+0.7% vs TC avg
Moderate +13% lift
Without
With
+13.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 0m
Avg Prosecution
28 currently pending
Career history
646
Total Applications
across all art units

Statute-Specific Performance

§101
1.6%
-38.4% vs TC avg
§103
55.1%
+15.1% vs TC avg
§102
22.3%
-17.7% vs TC avg
§112
16.9%
-23.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 629 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 16 and 18-20 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Hook et al. (US 9761525). With regard to claim 16, Hook teaches, in Figs 2 and 4, an integrated circuit (IC) device, comprising: a semiconductor body (14) comprising a front side (top in Fig 2) and a backside (bottom in Fig 2); a high voltage semiconductor device (HVSD) (50, 22, 20) formed in the front side; and an electrode (30) under the back side; wherein the electrode is beneath the HVSD (see figures); the electrode has internal sidewalls that surround a hole through the electrode (regions between elements 30 in Figure 4); and two of the internal sidewalls on opposite sides of the hole are directly beneath the HVSD (see Figure 4). With regard to claim 18, Hook teaches, in Figs 2 and 4, that the electrode has second internal sidewalls that are directly beneath the HVSD and define a second hole through the electrode (see figure 4). With regard to claim 19, Hook teaches, in Figs 2 and 4, that the hole is positioned so as to increase a breakdown voltage of the HVSD. (column 5, lines 1-35). With regard to claim 20, Hook teaches, in Figs 2 and 4, a dielectric layer (12) disposed between the electrode and the back side. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 11-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hook et al. (US 9761525). With regard to claim 11, Hook teaches, in Figs 2 and 4, an integrated circuit (IC) device comprising: a semiconductor body (14); a high voltage device (50, 20, 22) formed in the semiconductor body; an insulating layer (12) under the semiconductor body; and one or more electrodes (30) in a layer beneath the insulating layer; wherein each of the plurality of high voltage devices has a footprint beneath the semiconductor body (see figure 4); and the pattern includes internal sidewall that define a gap within each footprint (see figure 4). Hook does not explicitly teach that the high voltage devices are a plurality of devices and that the pattern is repeated for each of the plurality of high voltage devices. It has been held that mere duplication of the essential working parts of a device involves only routine skill in the art, and has no patentable significance unless a new and unexpected result is produced. See St. Regis Paper Co. v. Bemis Co., 193 USPQ 8 and In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). Therefore, it would have been obvious to the ordinary artisan to duplicate the essential working parts of Hook as no new or unexpected result is produced from such a replication. With regard to claim 12, Hook teaches, in Figs 2 and 4, that each of the gaps is surrounded by one of the one or more electrodes (see figure 4). With regard to claim 13, Hook teaches, in Figs 2 and 4, that each of the plurality of high voltage devices is surrounded by a distinct deep trench isolation structure (18); and each of the one or more electrodes is entirely within an outer perimeter of one of the deep trench isolation structures (see figure 2). With regard to claim 14, Hook teaches, in Figs 2 and 4, that each of the one or more electrodes has a pair of sidewalls separated by a dielectric (12) and within one of the footprints (see figure 4). With regard to claim 15, Hook teaches, in Figs 2 and 4, that the electrodes are longer than the high voltage devices (see figure 4, in the vertical direction in the figure). Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hook et al. (US 9761525) in view of Goktepeli (US 2017/0373026). With regard to claim 17, Hook teaches most of the limitations of the claim as set forth above with regard to claim 16. Hook does not explicitly teach that the HVSD and the electrode each have mirror symmetry. Goktepeli teaches, in Fig 5A, that the HVSD (510) and the electrode (530) each have mirror symmetry for, “reducing the electromagnetic coupling between components, which may be achieved through an arrangement of the geometry and direction of the components,” ([0003]). Therefore, it would have been obvious to the ordinary artisan at the effective date of filing to combine the device of Hook with the disposition of Goktepeli to reduce the electromagnetic coupling between components. Allowable Subject Matter Claims 1-10 are allowed. The following is a statement of reasons for the indication of allowable subject matter: the prior art of record fails to anticipate or render obvious claimed limitations of wherein the conductive layer forms a contiguous electrode directly beneath the HVSD; the contiguous electrode has a gap directly beneath the HVSD; a first portion of the contiguous electrode is on a first side of the gap; and a second portion of the contiguous electrode is on a second side of the gap, opposite the first side of the gap, as set forth in independent claim 1, when taken in concert with all the other limitations of the claim. All other allowed claims depend from claim 1. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to RAJ R GUPTA whose telephone number is (571)270-5707. The examiner can normally be reached 9:30AM-4PM, 8PM-10PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on 21236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /RAJ R GUPTA/Primary Examiner, Art Unit 2829
Read full office action

Prosecution Timeline

Feb 15, 2024
Application Filed
Aug 24, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
69%
Grant Probability
82%
With Interview (+13.4%)
3y 0m (~4m remaining)
Median Time to Grant
Low
PTA Risk
Based on 629 resolved cases by this examiner. Grant probability derived from career allowance rate.

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