DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Election/Restrictions
Claim 20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 02-09-26.
Applicant’s election without traverse of Group I (claims 1-19) in the reply filed on 02-09-26 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 2 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Kao et al. (US 2015/0140827 A1) in view of Lee et al. (US 2021/0143175 A1).
Regarding claim 1, Kao teaches a semiconductor processing method comprising providing a substrate to a processing region of a semiconductor processing chamber, as shown in Fig. 5, where a substrate is disposed within processing chamber 500 for processing (Kao paragraph [0055], Fig. 5). Kao further teaches that the substrate comprises an alternating stack of materials, including layers such as dielectric barrier layers, dielectric layers, and mask layers formed over one another (paragraph [0043]). Kao continues to teach that a feature extends through the alternating stack of materials, such as open features 460 (e.g., vias or trenches) formed through the patterned film stack (paragraph [0046], Fig. 4A). Kao further teaches that one material of the alternating stack comprises a silicon-containing material, such as silicon nitride, silicon carbide, silicon carbon nitride, or related materials (paragraph [0043]). Kao further teaches providing a fluorine-containing precursor and contacting the substrate therewith, such as a hydrofluoric acid solution used in a wet chemical etch process (paragraph [0047]).
Kao does not teach that a native oxide material is disposed on at least a portion of exposed surfaces of the silicon-containing material, nor does Kao explicitly teach performing a pre-clean treatment on the substrate prior to contacting the substrate with the fluorine-containing precursor.
Lee teaches that a native oxide material may be present on exposed surfaces of silicon-containing materials during semiconductor processing, and further teaches that a cleaning process may be performed to remove the native oxide layer prior to subsequent processing (paragraph [0073]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Lee to the method of Kao by recognizing the presence of native oxide on silicon-containing materials and performing a cleaning step prior to etching, because hydrofluoric-acid-based chemistries, such as those taught by Kao, were well known for removing silicon oxide, including native oxide, from semiconductor surfaces prior to subsequent processing steps. The combination represents the use of known cleaning and oxide-removal techniques in a known semiconductor processing environment to achieve the predictable result of removing native oxide from silicon-containing materials. See MPEP § 2143(I)(B).
Regarding claim 2, Kao teaches the semiconductor processing method of claim 1 including a substrate having stacked semiconductor layers forming a patterned film stack (paragraphs [0043]–[0044]).
Kao does not teach that the alternating stack comprises a first nitrogen-containing material, a silicon-containing material overlying the first nitrogen-containing material, a second nitrogen-containing material overlying the silicon-containing material, and an oxygen-containing material overlying the second nitrogen-containing material.
Lee teaches semiconductor structures including alternating layers comprising nitrogen-containing materials such as silicon nitride and oxygen-containing materials such as silicon oxide arranged in sequence within a stack (paragraph [0030]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the stacked layers of Kao to include the specific arrangement of nitrogen-containing and oxygen-containing materials as taught by Lee because such layer arrangements are commonly used in semiconductor device fabrication to provide etch selectivity, barrier properties, and dielectric isolation between device structures. See MPEP § 2143(I)(B).
Regarding claim 10, Kao teaches that the fluorine-containing precursor comprises hydrofluoric acid (paragraph [0047]). Kao further teaches that the concentration of the hydrofluoric acid solution may range between 1-5 percent, which constitutes a dilute hydrofluoric acid.
Claims 3, 4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Kao in view of Lee as applied to claim 1 above, and further in view of Xi et al. (US 2023/0022624 A1).
Regarding claim 3, Kao teaches the semiconductor processing method of claim 1 including features such as vias, trenches, or openings extending through stacked semiconductor layers during fabrication (paragraph [0046]).
Kao does not teach that the feature has an aspect ratio greater than or about 10:1.
Xi teaches semiconductor device structures having high-aspect-ratio features, wherein the aspect ratio of the structure is greater than 10:1 (paragraph [0018]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the feature of Kao with the high-aspect-ratio configuration taught by Xi because high-aspect-ratio features are commonly employed in semiconductor fabrication to enable advanced structures and increase device density. Selecting an aspect ratio within known ranges used in semiconductor processing represents the routine application of known design parameters. See MPEP § 2144.05.
Regarding claims 4 and 6, Lee teaches the semiconductor processing method of claim 1 including performing cleaning or surface preparation processes on a substrate during semiconductor fabrication (paragraph [0073]).
Lee does not teach that the pre-clean treatment comprises introducing water or steam to the substrate and filling the feature extending through the alternating stack of materials, nor condensing steam at a lower portion of the feature such that the feature is filled from a bottom of the feature to a top of the feature, as recited in claims 4 and 6.
Xi teaches performing cleaning treatments on semiconductor substrates by introducing water vapor into features formed in the substrate, where the vapor condenses on feature surfaces during cleaning processes (paragraphs [0057]–[0058]). The condensation of water vapor results in liquid formation within the feature, which accumulates along feature surfaces and would inherently fill the feature from lower portions toward upper portions.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the vapor-based cleaning process of Xi into the pre-clean treatment of the method of Lee because condensation of water vapor within recessed features results in liquid accumulation along feature surfaces, which would predictably fill the feature from lower portions toward upper portions. This represents the predictable use of known cleaning processes according to their established functions. See MPEP § 2143(I)(B).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kao in view of Lee as applied to claim 4 above, and further in view of Chen (US 6,162,738).
Kao teaches the semiconductor processing method of claim 4 including introducing water vapor to the substrate and filling features during a pre-clean treatment.
Kao does not teach agitating the substrate to remove an air bubble from the feature.
Chen teaches that agitation techniques such as megasonic or ultrasonic energy may be used during wet cleaning processes to enhance cleaning of semiconductor structures (col. 8, lines 42–48).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the agitation techniques taught by Chen during the pre-clean treatment of the method of Kao and Lee because agitation improves penetration of cleaning liquids into recessed structures and assists in removing trapped air bubbles, thereby improving cleaning effectiveness. Applying known cleaning enhancement techniques represents the predictable use of prior art elements according to their established functions. See MPEP § 2143(I)(B).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kao in view of Lee as applied to claim 1 above, and further in view of Xi as applied to claim 4 above, and further in view of Kunze-Concewitz (US 5,964,952).
Lee teaches the semiconductor processing method of claim 1 including performing cleaning or surface preparation processes on a substrate during semiconductor fabrication (paragraph [0073]).
Xi does not explicitly teach filling the feature without formation of an air bubble.
Kunze-Concewitz teaches precision cleaning processes using water and steam in which vapor bubbles collapse or burst during treatment, improving fluid interaction with the substrate and reducing trapped bubbles (col. 6, lines 45–60). Kunze-Concewitz further teaches applicability to microfabrication cleaning processes (col. 2, lines 59–67).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the cleaning process of Xi in view of Kunze-Concewitz to reduce or eliminate bubble formation within the feature because Kunze-Concewitz teaches that bubble collapse improves fluid contact and contaminant removal. Applying known bubble-reduction techniques to known vapor-cleaning processes represents the predictable use of prior art elements according to their established functions. See MPEP § 2143(I)(B).
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Kao in view of Lee as applied to claim 1 above, and further in view of Zhang (US 2012/0211462 A1).
Kao teaches the semiconductor processing method of claim 1 including contacting a substrate with a fluorine-containing precursor during semiconductor processing (paragraph [0047]).
Kao does not teach providing a surfactant to the processing region during the pre-clean treatment, with the fluorine-containing precursor, or both, as recited in claim 8, nor does Kao teach that the surfactant comprises a hydrophilic hydrocarbon as recited in claim 9.
Zhang teaches introducing alcohol additives into a substrate processing region during fluorine-based oxide etching processes, including alcohols such as methanol, ethanol, or isopropyl alcohol introduced together with water vapor (paragraphs [0025], [0045]). Zhang further teaches that such additives improve interaction of process fluids with patterned structures and reduce deformation forces (paragraph [0025]).
The instant specification identifies alcohol compounds such as ethanol, acetone, and isopropyl alcohol as examples of the claimed surfactant (paragraph [0048]), which are hydrophilic hydrocarbons.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the alcohol additives taught by Zhang into the oxide removal process of Kao because such additives improve wetting and interaction of process fluids with patterned structures, thereby improving contact between the etching chemistry and recessed features. Combining known additive chemistries with known oxide-removal processes represents the predictable use of prior art elements according to their established functions. See MPEP § 2143(I)(B).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Kao et al. and further in view of Kunze-Concewitz (US 5,964,952).
Regarding claim 11, Kao teaches a semiconductor processing method comprising providing a substrate to a processing region of a semiconductor processing chamber, wherein the substrate comprises a stacked film structure including multiple layers, wherein at least one of the layers comprises a silicon-containing material such as silicon nitride (SiN), silicon carbide (SiC), silicon carbon nitride (SiCN), or silicon oxide (SiO₂) (paragraph [0043]), and wherein at least one of the layers forming the feature sidewalls comprises a silicon-containing material, with features extending therethrough (paragraphs [0043]–[0046]). Kao further teaches contacting the substrate with a fluorine-containing precursor to remove oxide (paragraph [0047]).
Kao does not teach contacting the substrate with fluorine-containing precursor such that a bubble is not formed at a lower portion of the feature.
Kunze-Concewitz teaches cleaning processes using water and steam in which vapor bubbles collapse or are eliminated within a liquid film, thereby improving fluid contact with substrate surfaces and reducing trapped bubbles (col. 6, lines 45–60). Kunze-Concewitz further teaches applicability to microfabrication processes requiring highly clean surfaces (col. 2, lines 59–67).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the contacting step of Kao to reduce or eliminate bubble formation within recessed features in view of Kunze-Concewitz because reducing trapped bubbles improve fluid contact and enhances uniform processing within features. Applying known fluid behavior control techniques to known wet etching processes represent the predictable use of prior art elements according to their established functions. See MPEP § 2143(I)(B).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Kao in view of Kunze-Concewitz, as applied to claim 11 above and in further view of Lee et al. (US 2021/0143175 A1).
Regarding claim 12, Kao teaches the semiconductor processing method of claim 11 including a substrate having stacked layers (paragraphs [0043]–[0044]).
Kao does not teach that the alternating stack comprises a first nitrogen-containing material, a silicon-containing material overlying the first nitrogen-containing material, a second nitrogen-containing material overlying the silicon-containing material, and an oxygen-containing material overlying the second nitrogen-containing material.
Lee teaches semiconductor structures including alternating layers comprising nitrogen-containing materials such as silicon nitride and oxygen-containing materials such as silicon oxide arranged in sequence within a stack (paragraph [0030]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the stacked layers of Kao to include the specific arrangement of nitrogen-containing and oxygen-containing materials as taught by Lee because such layer arrangements are commonly used in semiconductor device fabrication to provide etch selectivity, barrier properties, and dielectric isolation between device structures. See MPEP § 2143(I)(B).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Kao in view of Kunze-Concewitz as applied to claim 11 above, and further in view of Takahashi et al. (US 2023/0127597 A1).
Kao teaches the semiconductor processing method of claim 11 including features such as vias, trenches, or openings extending through stacked semiconductor layers during device fabrication (paragraph [0046]).
Kao does not teach that the feature has a height greater than or about 2 μm.
Takahashi teaches forming recessed features in semiconductor substrates having depths of at least about 4000 nm (4 μm) during semiconductor etching processes (paragraph [0010]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the feature of Kao with the feature dimensions taught by Takahashi because semiconductor fabrication commonly utilizes deep recessed structures to achieve desired device architectures and device scaling. Selecting a feature height greater than about 2 μm represents the routine application of known feature dimensions within the ranges commonly used in semiconductor processing. See MPEP § 2144.05.
Claims 14, 16, 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kao in view of Kunze-Concewitz as applied to claim 11 above, and further in view of Xi et al. (US 2023/0022624 A1).
Regarding claim 14, Kao teaches the semiconductor processing method of claim 11.
Kao does not teach that a pressure in the processing region is less than or about 1,000 Torr.
Xi teaches semiconductor cleaning processes performed in controlled processing environments, wherein the pressure of the reaction environment ranges from 0 mTorr to 10000 mTorr (paragraph [0048]). This disclosed range includes pressures less than or about 1,000 Torr.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to operate the cleaning process of Kao at a pressure within the disclosed range of Xi because Xi teaches that chamber pressure is a process parameter affecting vapor-based cleaning. Selecting a pressure within a disclosed range represents routine optimization of a result-effective variable. See MPEP § 2144.05(I).
Regarding claims 16 and 17, Kao teaches the semiconductor processing method of claim 11.
Kao does not teach performing a pre-clean treatment on the substrate prior to contacting the substrate with the fluorine-containing precursor, nor does Kao teach filling the feature with water from a bottom of the feature with water to a top of the feature during such a pre-clean treatment.
Xi teaches performing cleaning treatments on semiconductor substrates prior to subsequent processing steps, including introducing water vapor into features formed in a substrate and condensing the vapor on feature surfaces (paragraphs [0057]–[0058]). The condensation of water vapor produces liquid water that accumulates along the surfaces of the features and would collect from lower portion of the feature toward upper portions, thereby filling the feature from the bottom to the top.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to perform the pre-clean treatment of Xi prior to the oxide removal process of Kao because pre-clean treatments are commonly used in semiconductor fabrication to remove contaminants and improve the effectiveness of subsequent etching processes. Further, condensation of water vapor within recessed features would result in liquid accumulation from lower portions upward, thereby filling the feature from the bottom to the top. This represents the predictable use of known cleaning processes according to their established functions. See MPEP § 2143(I)(B).
Regarding claim 18, Kao teaches the semiconductor processing method of claim 16.
Kao does not teach cooling the substrate prior to performing the pre-clean treatment or contacting the substrate with the fluorine-containing precursor.
Xi teaches performing an active cooling treatment during semiconductor cleaning in which water vapor introduced into features is cooled so that the vapor condenses into liquid on feature surfaces (paragraphs [0057]–[0059]). Xi further teaches that the condensed liquid accumulates along the feature surfaces and flows downward, carrying impurities, and provides specific temperature ranges for cooling treatment (paragraph [0059]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to cool the substrate prior to performing the pre-clean treatment or contacting the substrate with the fluorine-containing precursor in the process of Kao in view of Xi because Xi teaches that active cooling of the substrate promotes condensation of water vapor within features. Thereby improving cleaning effectiveness and facilitating removal of contaminants. A person of ordinary skill in the art would have recognized that controlling substrate temperature to achieve desired condensation behavior represents the use of a known process parameter to improve cleaning performance, and selecting an appropriate cooling step would have been within the routine skill in the art. See MPEP § 2144.05.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Kao in view of Kunze-Concewitz as applied to claim 11 above, and further in view of Zhang (US 2012/0211462 A1).
Kao teaches the semiconductor processing method of claim 11 including oxide removal from silicon surfaces during semiconductor processing.
Kao does not teach providing a surfactant to the processing region with the fluorine-containing precursor wherein the surfactant comprises a hydrophilic hydrocarbon.
Zhang teaches introducing alcohol additives into a substrate processing region during fluorine-based oxide etching processes. Specifically, Zhang teaches that alcohols such as methanol, ethanol, and isopropyl alcohol may be introduced into the substrate processing region together with water vapor during fluorine-based oxide etching processes (paragraphs [0025], [0045]). Zhang further teaches that such alcohol additives reduce deformation forces and improve interaction of process fluids with patterned structures (paragraph [0025]).
The instant specification identifies alcohol compounds such as ethanol, acetone, and isopropyl alcohol as examples of the claimed surfactant (paragraph [0048]), which are hydrophilic hydrocarbons.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the alcohol additives taught by Zhang into the oxide removal process of Kao because alcohol additives improve wetting and interaction of process fluids with patterned structures during semiconductor processing, thereby improving contact between the etching chemistry and surfaces within recessed features and improving process uniformity. Combining known additive chemistries with known oxide-etching processes represents the predictable use of prior art elements according to their established functions. See MPEP § 2143(I)(B).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Kao in view of Kunze-Concewitz and in further view of Xi applied to claim 16 above, and further in view of Xu (US 2018/0138055 A1).
Kao teaches the semiconductor processing method of claim 16 including performing cleaning or surface preparation on semiconductor substrates during processing.
Kao does not teach maintaining a relative humidity in the processing region greater than or about 70%.
Xu teaches semiconductor oxide removal processes in which the relative humidity within the processing region is controlled and increased to greater than or about 50% during oxide removal to improve removal effectiveness (paragraphs [006], [0050], [0075], and [0081]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to adjust the relative humidity within the processing region of Kao to a value greater than about 70% in view of Xu because Xu teaches that increasing relative humidity during oxide removal improves removal effeteness and enables additional oxide removal. A person of ordinary skill in the art would have recognized that selecting a relative humidity value at or above a known effective threshold (e.g., greater than about 50%) to further enhance oxide removal represents routine optimization of a result-effective variable. See MPEP § 2144.05(I).
Conclusion
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/JONATHAN L CARTER/Examiner, Art Unit 1713
/JOSHUA L ALLEN/Supervisory Patent Examiner, Art Unit 1713