Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Attorney Docket Number: TSMP20231956US02
Filling Date: 02/15/24
Priority Date: 12/04/23
Inventor: Huang et al
Examiner: Bilkis Jahan
DETAILED ACTION
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election of Group II, claims 1-10, 21-30 in the reply filed on 05/20/26 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 28-29 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al (US 2015/0279840 A1) in view of Ko et al (US 2020/0058793 A1).
Regarding claim 28, Huang discloses a method (Figures 1-13) comprising: forming a dielectric isolation region 22 (Para. 16) in a semiconductor substrate 20; forming a semiconductor fin 30 (Para. 17) adjacent to and higher than a top surface of the dielectric isolation region 22 (Fig. 12); forming a gate stack 29 (Para. 13) on the semiconductor fin 30; forming a source/drain region 30 joined to the semiconductor fin 30, wherein the source/drain region 30 is on a side of the gate stack 29; forming a source/drain silicide region 44 (Para. 24) on the source/drain region 30; performing a deposition process to form a contact etch stop layer (Para. 19) on the source/drain region 30 and spaced apart from the dielectric isolation region 22; forming an inter-layer dielectric (Para. 19) on and contacting the contact etch stop layer (contact through other layer like 42), wherein the inter-layer dielectric is further in contact with the dielectric isolation region (Para. 19); and forming a source/drain contact plug 42 (Para. 29) over and contacting the source/drain silicide region 44.
Huang does not explicitly disclose performing a selective deposition process to form a contact etch stop layer on the source/drain region.
However, Ko discloses a selective deposition process to form a contact etch stop layer on the source/drain region (Claim 7). Ko teaches the above modification is used to avoid oxidation during processes (Para. 99). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to substitute Huang etch stop layer process with Ko etch stop layer process as suggested above to avoid oxidation during processes (Para. 99).
Regarding claim 29, Huang further discloses the method of claim 28, wherein the inter-layer dielectric is further in physical contact (Para. 19, consider sequence as described) with the source/drain region 30.
Regarding claim 30, Huang further discloses the method of claim 28, wherein the inter-layer dielectric (Para. 19) is in physical contact with a downward-facing surface of the source/drain region, and is spaced apart from an upward-facing surface of the source/drain region 30.
Allowable Subject Matter
5. Claims 1-10 and 21-27 are allowed.
6. The following is an examiner’s statement of reasons for allowance:
7. The applied prior arts neither anticipate nor render the claimed subject matter obvious because they fail to teach the claimed method comprising: the conductive feature is selected from the group consisting of the source/drain region, the source/drain contact plug, and the gate contact plug; selectively depositing a first etch stop layer on the conductive feature, wherein the first inhibitor film prevents the first etch stop layer from being deposited thereon; and removing the first inhibitor film in combination with all other limitations as recited in claim 1.
8. The applied prior arts neither anticipate nor render the claimed subject matter obvious because they fail to teach the claimed method comprising: depositing an inter-layer dielectric over the first contact etch stop layer, wherein the inter-layer dielectric is in physical contact with both of the first contact etch stop layer and the shallow trench isolation region in combination with all other limitations as recited in claim 21.
9. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BILKIS JAHAN whose telephone number is (571)270-5022. The examiner can normally be reached Monday-Friday, 8:00 am-5 Pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon T Fletcher can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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BILKIS . JAHAN
Primary Examiner
Art Unit 2817
/BILKIS JAHAN/Primary Examiner, Art Unit 2817
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