DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-12 in the reply filed on 06/02/2026 is acknowledged.
Status of the Application
Claims 1-12 and 21-28 remain pending in this application. Acknowledgement is made of the amendment received 06/02/2026. Claims 13-20 are canceled, and claims 21-28 are added for consideration.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 9 and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al (US 20210407887 A1, hereafter Yu).
Regarding claim 9, Yu, in at least one embodiment, discloses: A semiconductor package (Yu 1C, fig 4, ¶0010-0020, 0036-0037) comprising:
a substrate (Yu 10, ¶0011);
a semiconductor package component (Yu 11, 15, ¶0012) bonded to the substrate (Yu fig 4, ¶0015, 0018), the semiconductor package component comprising:
a semiconductor die (Yu 110, ¶0012, 0014)(Yu fi 4);
a molding compound (Yu 117, ¶0017) on sidewalls of the semiconductor die (Yu fig 4, ¶0017); and
a first metal layer (Yu 15, ¶0022) on surfaces of the semiconductor die and the molding compound (Yu fig 4, ¶0022);
a lid (Yu 13C, ¶0020, 0036) attached to the substrate (Yu fig 4, ¶0027); and
a first composite metal feature (Yu 12, P, ¶0019, 0036-0037) between the first metal layer and the lid (Yu fig 4, ¶0022), the first composite metal feature comprising:
a first metal feature (Yu 12, ¶0019), wherein the first metal feature comprises a first material (Yu 12, ¶0019, “phase change metal alloy may include … alloy of tin (Sn), silver (Ag) and copper (Cu)”); and
a second metal feature (Yu P, ¶0036), wherein the second metal feature comprises a second material (Yu ¶0020, 0037, “metals or metal alloys, such as copper, aluminum, their alloys”) different from the first material (Yu ¶0019-0020), wherein first portions of the second metal feature (Yu P) protrude from a second portion of the second metal feature (Yu S130B, ¶0037, under a broadest reasonable interpretation of a “feature”) into the first metal feature (Yu fig 4, ¶0037).
Regarding claim 11, Yu discloses: The semiconductor package of claim 9, further comprising a barrier (Yu 18, 180, under a broadest reasonable interpretation of “barrier”, 18/180 form a structural barrier) on the second portion of the second metal feature (Yu S130B), wherein the barrier encircles the first portions of the second metal feature (Yu P) in a top-down view (Yu ¶0039, fig 28D-F).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 21-23, and 25-28 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al (US 20210407887 A1, hereafter Yu) in view of Deram et al (US 20070172381 A1, hereafter Deram).
Regarding claim 1, Yu, in at least one embodiment, teaches: A semiconductor package (Yu 1C, fig 4, ¶0010-0020, 0036-0037) comprising:
a substrate (Yu 10, ¶0011);
a semiconductor package component (Yu 11, 15, ¶0012) bonded to the substrate (Yu fig 4, ¶0015, 0018), wherein the semiconductor package component comprises a semiconductor die (Yu 110, ¶0012, 0014)(Yu fi 4);
a lid (Yu 13C, ¶0020, 0036) attached to the substrate (Yu fig 4, ¶0027); and
a first composite metal feature (Yu 12, P, ¶0019, 0036-0037) between the semiconductor package component and the lid (Yu fig 4, ¶0037), the first composite metal feature comprising:
a first metal feature (Yu 12, ¶0019), wherein the first metal feature comprises a first material (Yu 12, ¶0019, “phase change metal alloy may include … alloy of tin (Sn), silver (Ag) and copper (Cu)”); and
a second metal feature (Yu P, ¶0036), wherein the second metal feature comprises a second material (Yu ¶0020, 0037, “metals or metal alloys, such as copper, aluminum, their alloys”), and wherein the second material is different from the first material (Yu ¶0019-0020).
Yu does not explicitly teach: wherein the first material is an intermetallic compound.
Deram, in the same field of endeavor of semiconductor device manufacturing, teaches: a tin-silver-copper solder comprises an intermetallic compound (Deram ¶0013, 0014, 0068).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Yu such that the first material is an intermetallic compound, as taught by Deram, in order to utilize a lead-free solder composition, thereby providing a higher mechanical strength (Deram ¶0013).
Regarding claim 2, Yu in view of Deram teaches: The semiconductor package of claim 1, wherein the intermetallic compound (Yu 12 as modified by Deram) has a melting point higher than 217°C (Deram ¶0013, 0014, “melting temperature (217 to 221 °C)”).
Regarding claim 3, Yu in view of Deram teaches: The semiconductor package of claim 1, wherein the semiconductor package component (Yu 11, 15) further comprises a first metal layer (Yu 15, ¶0022), wherein the first metal layer is in contact with the semiconductor die (Yu 110) and the first composite metal feature (Yu 12, P as modified by Deram)(Yu fig 4, ¶0022).
Regarding claim 4, Yu in view of Deram teaches: The semiconductor package of claim 3, wherein the first metal feature (Yu 12 as modified by Deram) is in contact with the first metal layer (Yu 15)(Yu fig 4).
Regarding claim 5, Yu in view of Deram teaches: The semiconductor package of claim 4, wherein the second metal feature (Yu P) is in contact with the lid (Yu 13C)(Yu fig 4).
Regarding claim 6, Yu in view of Deram teaches: The semiconductor package of claim 4, wherein the second metal feature (Yu P) is embedded in the first metal feature (Yu 12 as modified by Deram)(Yu fig 4).
Regarding claim 7, Yu in view of Deram teaches: The semiconductor package of claim 1, wherein the first composite metal feature (Yu 12, P, 18 as modified by Deram) further comprises a third metal feature (Yu 18, ¶0026, “bonding layer 18 includes a metallic layer”) in contact with the lid, wherein the first metal feature (Yu 12 as modified by Deram) is between the second metal feature (Yu P) and the third metal feature (Yu fig 4, at least horizontally).
Regarding claim 8, Yu in view of Deram teaches: The semiconductor package of claim 1, wherein the first metal feature (Yu 12 as modified by Deram) and the second metal feature (Yu P) contacts each other (Yu fig 4, ¶0037) and have an interdigitating pattern (Yu fig 4, 28D-F, ¶0038).
Regarding claim 21, Yu, in at least one embodiment, teaches: A semiconductor package (Yu 1C, fig 4, ¶0010-0020, 0036-0037) comprising:
a substrate (Yu 10, ¶0011);
a semiconductor package component (Yu 11, 15, ¶0012) bonded to the substrate (Yu fig 4, ¶0015, 0018), wherein the semiconductor package component comprises:
a semiconductor die (Yu 110, ¶0012, 0014)(Yu fi 4); and
a first metal layer (Yu 15, ¶0022) on the semiconductor die (Yu fig 4, ¶0022)
a lid (Yu 13C, ¶0020, 0036) attached to the substrate (Yu fig 4, ¶0027); and
a first composite metal feature (Yu 12, P, ¶0019, 0036-0037) between the first metal layer of the semiconductor package and the lid (Yu fig 4, ¶0022), the first composite metal feature comprising:
a first metal feature (Yu 12, ¶0019), wherein the first metal feature comprises a first material (Yu 12, ¶0019, “phase change metal alloy may include … alloy of tin (Sn), silver (Ag) and copper (Cu)”); and
a first metal feature (Yu 12, ¶0019), wherein the first metal feature comprises a first material (Yu 12, ¶0019, “phase change metal alloy may include … alloy of tin (Sn), silver (Ag) and copper (Cu)”); and
a second metal feature (Yu P, ¶0036), wherein the second metal feature comprises a second material (Yu ¶0020, 0037, “metals or metal alloys, such as copper, aluminum, their alloys”) different from the first material (Yu ¶0019-0020).
Yu does not explicitly teach: wherein the first material is an intermetallic compound with a melting point higher than 217°C.
Deram, in the same field of endeavor of semiconductor device manufacturing, teaches: a tin-silver-copper solder comprises an intermetallic compound (Deram ¶0013, 0014, 0068) with a melting point higher than 217°C (Deram ¶0013, 0014, “melting temperature (217 to 221 °C)”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Yu such that the first material is an intermetallic compound with a melting point higher than 217°C, as taught by Deram, in order to utilize a lead-free solder composition, thereby providing a higher mechanical strength (Deram ¶0013).
Regarding claim 22, Yu in view of Deram teaches: The semiconductor package of claim 21, wherein first portions of the second metal feature (Yu P) extend into the first metal feature (Yu 12 as modified by Deram)(Yu fig 4).
Regarding claim 23, Yu in view of Deram teaches: The semiconductor package of claim 22, wherein the first portions of the second metal feature (Yu P) are an array of pillars (Yu ¶0037) in a bottom-up view (Yu fig 4, 28D-F, ¶0038).
Regarding claim 25, Yu in view of Deram, in at least one embodiment, teaches: The semiconductor package of claim 22, wherein the first portions of the second metal feature (Yu P) are interconnected strips in a bottom-up view (Yu fig 28D, ¶0038, under a broadest reasonable interpretation of “interconnected strips”, the pillars P are aligned in strips along a long axis forming an interconnected strip).
Regarding claim 26, Yu in view of Deram teaches: The semiconductor package of claim 21, wherein the first metal feature (Yu 12 as modified by Deram) is in contact with the first metal layer (Yu 15)(Yu fig 4).
Regarding claim 27, Yu in view of Deram teaches: The semiconductor package of claim 21, wherein the second metal feature (Yu P) is in contact with the first metal layer (Yu 15)(Yu 13C, at least in thermal contact).
Regarding claim 28, Yu in view of Deram teaches: The semiconductor package of claim 21, wherein the first metal layer (Yu 15) comprises three sub-layers having different metallic materials (Yu ¶0022, “a stacked layer of titanium (Ti), copper (Cu) and nickel (Ni), or a stacked layer of titanium (Ti), copper (Cu) and vanadium (V)”).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et al (US 20210407887 A1, hereafter Yu), as applied to claim 9 above, and further in view of Deram et al (US 20070172381 A1, hereafter Deram).
Regarding claim 10, Yu discloses: The semiconductor package of claim 9, wherein the first material comprising tin and copper (Yu 12, ¶0019, “phase change metal alloy may include … alloy of tin (Sn), silver (Ag) and copper (Cu)”).
Yu does not explicitly teach: wherein the first material is a first intermetallic compound comprising indium and copper, a second intermetallic compound comprising indium and gold, a third intermetallic compound comprising tin and copper, or a fourth intermetallic compound comprising tin and gold.
Deram, in the same field of endeavor of semiconductor device manufacturing, teaches: a tin-silver-copper solder comprises an intermetallic compound (Deram ¶0013, 0014, 0068), and include other materials including gold and indium (Deram ¶0019, 0021, 0050).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Yu such that the first material is an intermetallic compound, as taught by Deram, and such that “the first material is a first intermetallic compound comprising indium and copper, a second intermetallic compound comprising indium and gold, a third intermetallic compound comprising tin and copper, or a fourth intermetallic compound comprising tin and gold”, in order to utilize a lead-free solder composition, thereby providing a higher mechanical strength (Deram ¶0013) and/or improving wetting ability (Deram ¶0019).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et al (US 20210407887 A1, hereafter Yu), as applied to claim 9 above, and further in view of Ho et al (US 20150187679 A1, hereafter Ho).
Regarding claim 12, Yu teaches: The semiconductor package of claim 9.
Yu does not explicitly teach: wherein the first metal feature has a first volume and the first portions of the second metal feature has a second volume, and wherein a ratio of the second volume to the first volume is in a range between 0.2 and 0.3.
Ho, in the same field of endeavor of semiconductor device manufacturing, teaches: adjusting a volume of a thermal interface feature (Ho 28, ¶0022) to a second volume of first portions of a second metal feature (Ho 25, ¶0022, 0033-0034), wherein a ratio of the second volume to the first volume is about 0.5 (Ho ¶0030-0032).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to adjust a first volume of the first metal feature and/or a second volume of the first portions of the second metal feature of Yu as taught by Ho, such that “a ratio of the second volume to the first volume is in a range between 0.2 and 0.3”, in order to reduce the absolute thermal resistance of the interface between the first metal feature and the first portions of the second metal feature, thereby improving heat dissipation efficiency while reducing a usage of the first metal feature (Ho ¶0030-0032).
Further, the adjustment of a volume ratio is a matter of routine optimization. It has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art (MPEP 2144.05). In the instant case, the general conditions of adjusting a ratio of volumes is disclosed by Ho, and therefore discovering the optimum or working range of a ratio of the second volume to the first volume involves only routine skill in the art.
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et al (US 20210407887 A1, hereafter Yu) in view of Deram et al (US 20070172381 A1, hereafter Deram), as applied to claim 22, and further in view of Ho et al (US 20150187679 A1, hereafter Ho).
Regarding claim 24, Yu in view of Deram teaches: The semiconductor package of claim 22.
Yu in view of Deram does not explicitly teach: wherein the first portions of the second metal feature are concentric rings in a bottom-up view.
Yu further teaches: adjusting the arrangement of the first portions of the second metal feature (Yu P)(Yu ¶0038).
Ho, in the same field of endeavor of semiconductor device manufacturing, teaches: first portions of a second metal feature (Ho protrusions formed by 25, ¶0022) are concentric rings in a bottom-up view (Ho fig 4I, ¶0036).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Yu in view of Deram, such that “the first portions of the second metal feature are concentric rings in a bottom-up view”, as taught by Ho, in order to match a heat dissipation pattern of the semiconductor die (Ho ¶0036).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20070117270 A1 is cited as an example of an analogous device further disclosing a lidded package with a solder interface converted to an intermetallic compound between the lid and die.
US 20200388554 A1 is cited as an example of an analogous device further disclosing a solder thermal interface material forming an intermetallic compound with a metal layer of a package lid.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS B. MICHAUD whose telephone number is (703)756-1796. The examiner can normally be reached Monday-Friday, 0800-1700 Eastern Time.
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/NICHOLAS B. MICHAUD/
EXAMINER
Art Unit 2818
/BRIAN TURNER/Primary Examiner, Art Unit 2818
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