DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1,4-5,9,15,18,34,38,42,45-46,55-56,63 and 69,77,80,84,86,88 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kirby (USPGPUB DOCUMENT: 2015/0093892, hereinafter Kirby) in view of Sengupta(USPGPUB DOCUMENT: 2002/0030275, hereinafter Sengupta) and Schneegans (USPGPUB DOCUMENT: 2008/0081157, hereinafter Schneegans).
Re claim 1 Kirby discloses a semiconductor die, comprising: a multilayer metallization structure(128a/128b/128c)[0036,0047] the multilayer metallization structure[0036,0047] comprising a first metallization layer(128a) and a second metallization layer(128b) on the first metallization layer(128a),
Kirby does not discloses a semiconductor die, comprising: a semiconductor structure;
the second metallization layer(128b) having a different grain microstructure[0011 of Sengupta] than the first metallization layer(128a), wherein the first metallization layer(128a) and the second metallization layer(128b) include at least one common chemical element(Al)[0011 of Sengupta].
Sengupta discloses the second layer(21-1/21-2/22) having a different grain microstructure[0011 of Sengupta] than the first layer(21-1/21-2/22), wherein the first layer(21-1/21-2/22) and the second layer(21-1/21-2/22) include at least one common chemical element(Al)[0011 of Sengupta].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Sengupta to the teachings of Kirby in order to have improve metallization performance [0009, Sengupta]. In doing so, the second metallization layer(128b) having a different grain microstructure[0011 of Sengupta] than the first metallization layer(128a), wherein the first metallization layer(128a) and the second metallization layer(128b) include at least one common chemical element(Al)[0011 of Sengupta].
Kirby and Sengupta does not disclose a semiconductor die, comprising: a semiconductor structure;
Schneegans disclose a semiconductor die, comprising: a semiconductor structure[0018];
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Schneegans to the teachings of Kirby in order to have high performance and/or be simple to produce [0003, Schneegans].
Re claim 4 Kirby, Sengupta and Schneegans disclose the semiconductor die of claim 1, wherein the at least one common chemical element(Al)[0011 of Sengupta] is aluminum[0011 of Sengupta].
Re claim 5 Kirby, Sengupta and Schneegans disclose the semiconductor die of claim 1, wherein the first metallization layer(128a) comprises aluminum[0011 of Sengupta] and the second metallization layer(128b) comprises an aluminum alloy[0011 of Sengupta], and wherein the aluminum alloy[0011 of Sengupta] is one of an aluminum[0011 of Sengupta]-copper alloy, an aluminum[0011 of Sengupta]-magnesium alloy, or an aluminum[0011 of Sengupta]-beryllium alloy.
Re claim 9 Kirby, Sengupta and Schneegans disclose the semiconductor die of claim 1, wherein the first metallization layer(128a) comprises a first aluminum alloy[0011 of Sengupta], and the second metallization layer(128b) comprises a second aluminum alloy[0011 of Sengupta] that is different from the first aluminum alloy[0011 of Sengupta].
Re claim 15 Kirby, Sengupta and Schneegans disclose the semiconductor die of claim 1, wherein the multilayer metallization structure[0016] is a multilayer metallization stack comprising a plurality of first metallization layer(128a)s and a plurality of second metallization layer(128b)s, and wherein each first metallization layer(128a) and each second metallization layer(128b) is alternately arranged in a stacked arrangement.
Re claim 18 Kirby, Sengupta and Schneegans disclose the semiconductor die of claim 1, wherein the multilayer metallization structure[0016] has a combined thickness(claim 20/22 of Schneegans) greater than about 1 micron.
Re claim 34 Kirby discloses a semiconductor die, comprising: and a multilayer metallization structure(128a/128b/128c)[0036,0047] on the semiconductor structure, the multilayer metallization structure comprising a first metallization layer(128a) and a second metallization layer(128b) on the first metallization layer;
Kirby does not disclose a semiconductor die, comprising: a semiconductor structure; wherein a smallest grain size of the first metallization layer(128a) is greater than about 100 nanometers and a largest grain size of the second metallization layer(128b) is less than about 100 nanometers.
Sengupta discloses the second layer(21-1/21-2/22) having a different grain microstructure[0011 of Sengupta] than the first layer(21-1/21-2/22),
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Sengupta to the teachings of Kirby in order to have improve metallization performance [0009, Sengupta]. In doing so, the second metallization layer(128b) having a different grain microstructure[0011 of Sengupta] than the first metallization layer(128a),
Kirby and Sengupta does not disclose a semiconductor die, comprising: a semiconductor structure; wherein a smallest grain size of the first metallization layer(128a) is greater than about 100 nanometers and a largest grain size of the second metallization layer(128b) is less than about 100 nanometers.
Schneegans disclose a semiconductor die, comprising: a semiconductor structure[0070 of Schneegans]; wherein a smallest grain size of the first metallization layer[0070,0075 of Schneegans] is greater than about 100 nanometers(claim 20/22 of Schneegans) and a largest grain size of the second metallization layer[0070,0075 of Schneegans] is less than about 100 nanometers(claim 20/22 of Schneegans).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Schneegans to the teachings of Kirby in order to have high performance and/or be simple to produce [0003, Schneegans]. In doing so, a semiconductor die, comprising: a semiconductor structure[0070 of Schneegans]; wherein a smallest grain size of the first metallization layer(128a) is greater than about 100 nanometers(claim 20/22 of Schneegans) and a largest grain size of the second metallization layer(128b) is less than about 100 nanometers(claim 20/22 of Schneegans).
Re claim 38 Kirby, Sengupta and Schneegans disclose the semiconductor die of claim 34, wherein the multilayer metallization structure[0016] comprises at least two first metallization layer(128a)s alternately arranged between at least two second metallization layer(128b)s.
Re claim 42 Kirby, Sengupta and Schneegans disclose the semiconductor die of claim 34, wherein the first metallization layer(128a) comprises aluminum[0011 of Sengupta], and the second metallization layer(128b) comprises a copper alloy, the copper alloy being one of acopper-beryllium alloy or a copper-magnesium alloy.
Re claim 45 Kirby, Sengupta and Schneegans disclose the semiconductor die of claim 34, wherein a difference between the smallest grain size of the first metallization layer(128a) and the largest grain size of the second metallization layer(128b) is about 100 nanometers.
Re claim 46 Kirby, Sengupta and Schneegans disclose the semiconductor die of claim 34, wherein the smallest grain size of the first metallization layer(128a) is in a range of about 100 nanometers to about 500 nanometers, and wherein the largest grain size of the second metallization layer(128b) is in a range of about 20 nanometers to about 100 nanometers.
Re claim 55 Kirby, Sengupta and Schneegans disclose the semiconductor die of claim 54 claim 34,wherein the a thickness(claim 20/22 of Schneegans) of the first metallization layer(128a) is substantially equal to the a thickness(claim 20/22 of Schneegans) of the second metallization layer(128b).
Re claim 56 Kirby, Sengupta and Schneegans disclose the semiconductor die of claim 54 claim 34,wherein the a thickness(claim 20/22 of Schneegans) of the first metallization layer(128a) is different than thea thickness(claim 20/22 of Schneegans) of the second metallization layer(128b).
Re claim 63 Kirby discloses a semiconductor device package, comprising: the semiconductor die comprising a multilayer metallization structure(128a/128b/128c)[0036,0047], the multilayer metallization structure comprising a first metallization layer(128a) and a second metallization layer(128b) on the first metallization layer,
Kirby does not disclose a semiconductor device package, comprising: a submount; and a semiconductor die on the submount, wherein the first metallization layer(128a) comprises aluminum[0011 of Sengupta] and the second metallization layer(128b) comprises an aluminum alloy[0011 of Sengupta]; the multilayer metallization structure[0016] comprising a first metallization layer(128a) having a thickness in a range of about 100 nanometers to about 2 microns and a second metallization layer(128b) on the first metallization layer(128a), the second metallization layer(128b) having a thickness in a range of about 100 nanometers to about 2 microns,
Sengupta discloses a semiconductor device package, comprising: wherein the first layer(21-1/21-2/22) comprises aluminum[0011 of Sengupta] and the second layer(21-1/21-2/22) comprises an aluminum alloy[0011 of Sengupta].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Sengupta to the teachings of Kirby in order to have improve metallization performance [0009, Sengupta]. In doing so, wherein the first metallization layer(128a) comprises aluminum[0011 of Sengupta] and the second metallization layer(128b) comprises an aluminum alloy[0011 of Sengupta].
Kirby and Sengupta does not discloses a semiconductor device package, comprising:a submount; the multilayer metallization structure[0016] comprising a first metallization layer(128a) having a thickness in a range of about 100 nanometers to about 2 microns and a second metallization layer(128b) on the first metallization layer(128a), the second metallization layer(128b) having a thickness in a range of about 100 nanometers to about 2 microns,
Schneegans discloses a semiconductor[0018 of Schneegans] device package, comprising:a submount(452 of Schneegans); the multilayer metallization structure[0075 of Schneegans] comprising a first metallization layer[0075 of Schneegans] having a thickness in a range of about 100 nanometers to about 2 microns[0062,0065,0068 of Schneegans] and a second metallization layer[0075 of Schneegans] on the first metallization layer, the second metallization layer having a thickness in a range of about 100 nanometers to about 2 microns[0062,0065,0068 of Schneegans],
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Schneegans to the teachings of Kirby in order to have high performance and/or be simple to produce [0003, Schneegans]. In doing so, a semiconductor[0018 of Schneegans] device package, comprising:a submount; the multilayer metallization structure[0016] comprising a first metallization layer(128a) having a thickness in a range of about 100 nanometers to about 2 microns[0065,0068 of Schneegans] and a second metallization layer(128b) on the first metallization layer(128a), the second metallization layer(128b) having a thickness in a range of about 100 nanometers to about 2 microns[0065,0068 of Schneegans],
Re claim 69 Kirby, Sengupta and Schneegans disclose the semiconductor device package of claim 63, wherein the aluminum alloy[0011 of Sengupta] is a ternary aluminum alloy[0011 of Sengupta] comprising a ternary element, and the ternary element is one of silicon or cobalt.
Re claim 77 Kirby, Sengupta and Schneegans disclose the semiconductor device package of claim 63, further comprising an encapsulating portion directly contacting the multilayer metallization structure[0016], wherein the encapsulating portion comprises an epoxy mold compound (EMC).
Re claim 80 Kirby, Sengupta and Schneegans disclose the semiconductor device package of claim 63, further comprising a passivation layer on the multilayer metallization structure[0016], wherein the passivation layer comprises one of silicon nitride or a polymer.
Re claim 84 Kirby, Sengupta and Schneegans disclose the semiconductor device package of claim 63, wherein the semiconductor device package is one of a discrete semiconductor device package or a power module[0002 of Schneegans].
Re claim 86 Kirby, Sengupta and Schneegans disclose the semiconductor device package of claim 63, wherein the multilayer metallization structure[0016] is one or more of an electrode, an interconnect, or a bonding pad for the semiconductor die[0002 of Schneegans].
Re claim 88 Kirby, Sengupta and Schneegans disclose the semiconductor device package of claim 63, wherein the semiconductor die comprises a wide bandgap semiconductor, the wide bandgap semiconductor comprising one of a silicon carbide-based metal-oxide-semiconductor field-effect transistor (MOSFET), a silicon carbide-based Schottky diode, or a Group-III nitride-based high electron mobility transistor (HEMT) device[0002 of Schneegans].
Response to Arguments
Applicant’s arguments with respect to claim(s) 1,4-5,9,15,18,34,38,42,45-46,55-56,63 and 69,77,80,84,86,88 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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