DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II, claims 11-30 in the reply filed on May 27, 2026 is acknowledged. Non-elected claims 1-10 have been canceled by Applicant.
Information Disclosure Statement
The information disclosure statement(s) submitted on February 15, 2024 and June 20, 2025 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Claim Objections
Claims 12 and 15 are objected to because of the following informalities:
“a semiconductor layer” should read “a first semiconductor layer” (claim 12, line 3);
“the semiconductor layer” should read “the first semiconductor layer” (claim 12, line 3);
“nanostructure layers” should read “semiconductor nanostructure layers” (claim 15, line 4).
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 15 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 15 recites the limitation "the first stack of semiconductor nanostructures" in lines 2-3. There is insufficient antecedent basis for this limitation in the claim. To overcome the rejection, it is suggested that Applicant amend independent claim 11 to recite “forming a first stack of semiconductor nanostructures” (claim 11, line 3) and “the first stack of semiconductor nanostructures” (claim 11, lines 9-10). It is further suggested that Applicant amend claim 14 to recite “the first stack of semiconductor nanostructures” (claim 14, line 3). Correction is respectfully requested.
Allowable Subject Matter
Claims 11, 13, 14 and 16-30 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: US 2020/0052107 A1 (hereinafter “Lie”) appears to be the closest prior art.
Regarding claim 11, Lie discloses a method, comprising:
forming a stack of semiconductor nanostructure layers (120, 130; Fig. 1; [0029]) over a substrate (110; Fig. 1; [0029]);
forming a stack of semiconductor nanostructures (132 (125, 135); Fig. 2; [0045]) by forming a source/drain opening (112; Figs. 2-3; [0047]) through the stack of semiconductor nanostructure layers;
forming a dielectric layer (180; Fig. 4; [0050] and [0052]) on surfaces exposed by the source/drain opening;
forming an isolation structure (185; Fig. 5; [0054]) by removing portions of the dielectric layer; and
forming a source/drain (230; Fig. 15; [0087]) abutting the stack of semiconductor nanostructures.
Lie does not disclose forming a first semiconductor layer on the dielectric layer in the source/drain opening, forming an isolation structure by removing portions of the dielectric layer exposed by the first semiconductor layer, and forming a source/drain on the first semiconductor layer and abutting the stack of semiconductor nanostructures.
Accordingly, claims 11, 13 and 14 are allowed because the prior art of record, individually or in combination, does not teach or suggest “forming a first semiconductor layer on the dielectric layer in the source/drain opening; forming an isolation structure by removing portions of the dielectric layer exposed by the first semiconductor layer; and forming a source/drain on the first semiconductor layer and abutting the stack of semiconductor nanostructures” as recited in independent claim 11.
Claim 12 would be allowable if amended to overcome the objections set forth in this Office action. Claim 15 would be allowable if amended to overcome the rejection under 35 U.S.C. 112(b) and the objection set forth in this Office action.
Claims 16-20 are allowed because the prior art of record, individually or in combination, does not teach or suggest “forming a first semiconductor layer in the source/drain opening; forming an isolating layer in the source/drain opening on the first semiconductor layer; forming an isolation layer by thinning the isolating layer, the forming an isolation layer exposing an upper surface of the first semiconductor layer; forming an implantation region including first dopants of a first type by directing the first dopants onto the upper surface of the first semiconductor layer; forming a second semiconductor layer on the implantation region; forming an isolation structure by removing portions of the isolation layer exposed by the second semiconductor layer; and forming a source/drain on the second semiconductor layer, the source/drain being of a second type different than the first type” as recited in independent claim 16.
Claims 21-30 are allowed because the prior art of record, individually or in combination, does not teach or suggest “forming a stack of semiconductor nanostructures over a fin of a substrate; forming an extended source/drain opening through the stack of semiconductor nanostructures, the extended source/drain opening extending to a first depth below an upper surface of the fin; forming a first material layer in the extended source/drain opening, the first material layer being a dielectric material; forming a first semiconductor layer on the first material layer in the extended source/drain opening; and forming an isolation structure by removing portions of the first material layer exposed by the first semiconductor layer, the isolation structure extending to a second depth below a bottom surface of a source/drain subsequently formed on the first semiconductor layer” as recited in independent claim 21.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER M ALBRECHT whose telephone number is (571)272-7813. The examiner can normally be reached M-F 9:30 AM - 6:30 PM (CT).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at (571) 272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PETER M ALBRECHT/Primary Examiner, Art Unit 2811
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