Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I.A, Species I.A.i and I.A.iii in the reply filed on 5/05/2026 is acknowledged. Claims 12-16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species I.B, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 5/05/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 4, 8, and 23 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
In Fig. 11 and 12, Applicant discloses what appears to be two identical circuit structures. Voltage is applied to the same connectors (161 and 162). However, Applicant claims that the current can flow through two separate paths. Examiner is unclear as to how this is possible.
Similarly, in Figs. 17 and 18, Applicant discloses a voltage applied to the same bottom connectors (321 and 322) and again, current takes different paths. Examiner is unclear as to how this si possible.
For these reasons, Claims 4, 8, and 23, which pertain to these configurations, are rejected under 112(a). Examiner is requesting clarification from Applicant regarding what was intended with these configurations.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over US20180358332A1 (Kim) in view of US20210066222A1 (Chen_1)
Regarding Claim 1, Kim discloses a method of manufacturing and testing a semiconductor package (Para. [0017]), the method comprising: receiving a first semiconductor structure (Fig. 3, el. 110, Para. [0029]) having a first side and a second side opposite to the first side (the bottom side can be taken as the first side and the top side can be taken as the second side), and including: a first die (Fig. 3, el. 116, Para. [0031]); a first bump disposed over the first die (Fig. 3, el. 118, Para. [0033] – see the part of 118 that is directly on 116); a first via adjacent to the first die (Fig. 3, el. 111, Para. [0031]); disposing a plurality of connectors on the first side (Fig. 3, el. 115 and 114, Para. [0031]), wherein each of the plurality of connectors is electrically connected to least one of the first bump and the first via (Para. [0031]); probing the plurality of connectors (Para. [0033]); and bonding the first semiconductor structure to a second semiconductor structure (Fig. 3, el. 120 is the second semiconductor structure, Paras. [0028] and [0029]), wherein the plurality of connectors are disposed between the first semiconductor structure and the second semiconductor structure after the bonding (see Fig. 3, where the connectors 114 and 115 are between the two semiconductor structures).
Kim does not disclose a first molding surrounding the fist die, the first bump and the first via.
Chen_1 discloses a first semiconductor package (Fig. 18A, el. 500, Para. [0046]) comprising a first semiconductor structure (Fig. 18A, el. 400, Para. [0046]) including a first die (Fig. 18A, el. 440, Para. [0046]), a first bump (Fig. 18A, el. 410, Para. [0046]), a first via adjacent to the first die (Fig. 18A, el. 408, Para. [0051]), a second semiconductor structure (Fig. 18A, el. 300, Para. [0046]), and a first molding surrounding the first die, the first bump, and the first via (see the shaded portion of the el. 400).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to add a first molding layer surrounding the first die, the first bump, and the first via, as disclosed by Chen_1. As is well-known, adding a molding layer provides structural support for the components in the package.
Regarding Claim 6, Kim in view of Chen_1 discloses the method of Claim 1, wherein the plurality of connectors includes a first bump connector (Kim, Fig. 3, el. 115, Para. [0031]) and a first via connector (Kim, Fig. 3, el. 114, Para [0031]), wherein the first bump connector and the first via connector are electrically connected to the first bump and the first via respectively (Kim, Fig. 3, Para. [0031]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Chen_1.
Regarding Claim 10, Kim in view of Chen_1 discloses the method of Claim 1, wherein the second semiconductor structure includes a second die (Kim, Fig. 3, el. 116 of 120).
Chen_1 discloses that the second die is surrounded by a molding (see Fig. 18A, where the shaded portion of el. 300).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to surround the second die and the plurality of connectors with molding. This has the well known benefit of protecting the die and the connectors.
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Chen_1 and US20140264337A1 (Chen_2).
Regarding Claims 7 and 8, Kim in view of Chen_1 discloses the method of claim 6.
Kim in view of Chen_1 does not disclose wherein the probing of the plurality of conductive bumps includes supplying a voltage between at least two of the plurality of conductive bumps.
Chen_2 discloses the idea of supplying voltage between connectors on a semiconductor package to perform various tests, such as testing connectivity and signals (Para. [0062] and [0063]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to apply a voltage to two of the conductive bumps. This would have the benefit of determining whether, for example, there is signal integrity in the first die. Further, it would have been obvious to supply the voltage such that the current flows through the first RDL and the first die, to test the signal integrity between the connectors and the first die (see 112a rejections above for more).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Chen_1.
Regarding Claim 2, Kim discloses the method of Claim 1.
Chen_1 further discloses a first RDL (Fig. 18A, el. 452, Para. [0051]), conductive bumps over the first RDL (Fig. 18A, el. 420, Para. [0055]), and probing the conductive bumps (Para. [0085]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to add the RDL as disclosed by Chen_1 and probe the connectors. Adding the RDL allows for more flexibility with connections, and probing the connectors allows tests to be performed on the first die to ensure integrity before further processing (Para. [0085]).
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Chen_1 and US20140264337A1 (Chen_2).
Regarding Claims 3 and 4, Kim in view of Chen_1 discloses the method of claim 2.
Kim in view of Chen_1 does not disclose wherein the probing of the plurality of conductive bumps includes supplying a voltage between at least two of the plurality of conductive bumps.
Chen_2 discloses the idea of supplying voltage between connectors on a semiconductor package to perform various tests, such as testing connectivity (Para. [0062] and [0063]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to apply a voltage to two of the conductive bumps. This would have the benefit of determining whether, for example, there is a short circuit. Further, it would have been obvious to supply the voltage such that the current flows through the first RDL and the second semiconductor structure, to test the connectivity of the path from the conductive bumps to the second semiconductor (see 112a rejections above for more).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Chen_1.
Regarding Claim 11, Kim in view of Chen_1 discloses the method of Claim 1.
Kim in view of Chen_1 does not disclose forming a second RDL between the plurality of connectors and the first bump.
However, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to form a second RDL between the plurality of connectors and the first bump. Forming a second RDL would have the benefit of allowing greater flexibility in connecting the first semiconductor to the second semiconductor and allow for more efficient routing and signal connections.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Chen_1.
Regarding Claim 21, Kim discloses a method of manufacturing and testing a semiconductor package (Para. [0017]), the method comprising: receiving a first semiconductor structure (Fig. 3, el. 110, Para. [0029]) having a first side and a second side opposite to the first side (the bottom side can be taken as the first side and the top side can be taken as the second side), and including: a first die (Fig. 3, el. 116, Para. [0031]); a first bump disposed over the first die (Fig. 3, el. 118, Para. [0033] – see the part of 118 that is directly on 116); a first via adjacent to the first die (Fig. 3, el. 111, Para. [0031]); disposing a a first bump connector and a first via connector at the first side (Fig. 3, el. 115 and 114, Para. [0031]), wherein the first bump connector is electrically connected to the first bump and the first via connector is electrically connected to the first via (Para. [0031]); probing the first bump connector and the first via connector (Para. [0033]); and bonding the first semiconductor structure to a second semiconductor structure (Fig. 3, el. 120 is the second semiconductor structure, Paras. [0028] and [0029]), wherein the first bump connector and the first via connector are disposed between the first semiconductor structure and the second semiconductor structure after the bonding (see Fig. 3, where the connectors 114 and 115 are between the two semiconductor structures).
Kim does not disclose a first molding surrounding the first die, the first bump and the first via, and does not disclose a first RDL on the first side, wherein the first RDL is electrically connected to the first bump and the first via.
Chen_1 discloses a first semiconductor package (Fig. 18A, el. 500, Para. [0046]) comprising a first semiconductor structure (Fig. 18A, el. 400, Para. [0046]) including a first die (Fig. 18A, el. 440, Para. [0046]), a first bump (Fig. 18A, el. 410, Para. [0046]), a first via adjacent to the first die (Fig. 18A, el. 408, Para. [0051]), a second semiconductor structure (Fig. 18A, el. 300, Para. [0046]), and a first molding surrounding the first die, the first bump, and the first via (see the shaded portion of the el. 400).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to add a first molding layer surrounding the first die, the first bump, and the first via, as disclosed by Chen_1. As is well-known, adding a molding layer provides structural support for the components in the package. Further, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to form a first RDL on the first side, where the first RDL is electrically connected to the first bump and the first via. This has the well-known benefit of allowing increased flexibility in connecting one package to another, allowing for efficient routing of signals.
Claims 22 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Chen_1 and Chen_2.
Regarding Claims 22 and 23, Kim in view of Chen_1 discloses the method of claim 21
Kim in view of Chen_1 does not disclose wherein the probing of the first bump connector and the first via connector comprises supplying a voltage between the first bump connector and the first via connector.
Chen_2 discloses the idea of supplying voltage between connectors on a semiconductor package to perform various tests, such as testing connectivity and signals (Para. [0062] and [0063]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to apply a voltage to two of the conductive bumps. This would have the benefit of determining whether, for example, there is signal integrity in the first die. Further, it would have been obvious to supply the voltage such that the current flows through the first RDL and the first die, to test the signal integrity between the connectors and the first die (see 112a rejections above for more).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Chen_1.
Regarding Claim 24, Kim in view of Chen_1 discloses the method of Claim 21, wherein the second semiconductor structure includes a second die (Kim, Fig. 3, el. 116 of 120).
Chen_1 discloses that the second die is surrounded by a molding (see Fig. 18A, where the shaded portion of el. 300).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to surround the second die and the plurality of connectors with molding. This has the well known benefit of protecting the die and the connectors.
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Chen_1.
Regarding Claim 25, Kim in view of Chen_1 discloses the method of Claim 1.
Chen_1 further discloses a second RDL (Fig. 18A, el. 452, Para. [0051]), conductive bumps over the first RDL (Fig. 18A, el. 420, Para. [0055]), and probing the conductive bumps (Para. [0085]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to add the RDL as disclosed by Chen_1 and probe the connectors. Adding the RDL allows for more flexibility with connections, and probing the connectors allows tests to be performed on the first die to ensure integrity before further processing (Para. [0085]).
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Chen_1.
Regarding Claim 26, Kim in view of Chen_1 discloses the method of Claim 21.
Kim in view of Chen_1 does not disclose that the first semiconductor structure is an interposer.
However, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify Kim in view of Chen_1 such that the first semiconductor structure is interposer. This would have the benefit of allowing high density routing and improved signal integrity for the second semiconductor structure.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROHIT PARTHASARATHY whose telephone number is (571)272-2572. The examiner can normally be reached Monday-Friday 8:30a-5p.
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/ROHIT PARTHASARATHY/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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