Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the application No. 18/443,343 filed on February 16, 2024.
Specification
3. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “Semiconductor Device Including Power Domains in Back Metal Structures of a Wafer and Method for Manufacturing The Same”.
Claim Objections
4. Claims 1-2, 4-7, 9 are objected to because of the following informalities: In the following, the claims should be recited to avoid indefiniteness due to lack of antecedent basis, and/or smooth flow of claim languages/phrases:
1. (Currently Amended) A semiconductor device formed on a wafer having a front side and a back side, comprising:
a first back metal structure formed on the back side of the wafer and extending in a first direction;
a second back metal structure formed on the back side of the wafer and extending in the first direction, wherein the second back metal structure is spaced apart from the first back metal structure along a second direction vertical to the first direction;
a first conductive structure formed on the front side of the wafer
a metal layer structure
2. (Currently Amended) The semiconductor device of claim 1, further comprising:
a second conductive structure formed on the front side of the wafer and extending in the first direction, wherein the second conductive structure is formed between the first back metal structure and the metal layer structure; and
a first via structure
4. (Currently Amended) The semiconductor device of claim 3, further comprising:
a first front metal structure
5. (Currently Amended) The semiconductor device of claim 1, further comprising:
a through via structure
6. (Currently Amended) The semiconductor device of claim 5, further comprising:
a second front metal structure
7. (Currently Amended) The semiconductor device of claim 6, further comprising:
a third conductive structure
9. (Currently Amended) A semiconductor device formed on a wafer, comprising:
a first back metal structure
a first conductive structure
a metal layer structure
a second metal structure
Appropriate corrections are needed.
Claim Rejections - 35 USC § 102
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
6. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
7. Claims 1-2, 5, 8, 18, 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by LIN et al. (US 2023/0420369 A1).
Regarding independent claim 1, LIN et al. teaches a semiconductor device (300, para [0040], see Fig. 3) formed on a wafer (310 substrate, para [0042] wherein the substrate is a part of a wafer) having a front side (upper side) and a back side (bottom side), comprising:
a first back metal structure (340: BM0 left portion) formed on the back side (bottom side) of the wafer (310) and extending in a first direction (Z-axis);
a second back metal structure (340: BM0 right portion) formed on the back side (bottom surface) of the wafer (310) and extending in the first direction (Z-axis), wherein the second back metal structure (340: BM0 right portion) is spaced apart (distance or gap) from the first back metal structure (340: BM0 left portion) along a second direction (X-axis) vertical to the first direction (Z-axis);
a first conductive structure (330: M0 metal-zero, para [0046]) formed on the front side (upper surface) of the wafer (310) extending in the first direction (Z-axis) and formed above the second back metal structure (340: BM0); and
a metal layer structure (330: M2, see para [0046]) extending in the second direction and formed above the first conductive structure (330: M0), wherein the first back metal structure (BM0 left portion) belongs to a first power domain (VVDD, para [0040]) and the second back metal structure (BM0 right portion) belongs to a second power domain (TVDD, para [0040]) different from the first power domain.
Regarding claim 2, LIN et al. teaches wherein (Fig. 3), further comprising:
a second conductive structure (M1, para [0046]) formed on the front side of the wafer (310) and extending in the first direction, wherein the second conductive structure (M1) is formed between the first back metal structure (BM0) and the metal layer structure (M2); and
a first via structure (V0) formed between the first back metal structure (BM0) and the second conductive structure (M1).
Regarding claim 5, LIN et al. teaches wherein (Fig. 3), further comprising:
a through via structure (VD) extending in the first direction, wherein the through via structure (VD) is formed above the first back metal structure (BM0).
Regarding claim 8, LIN et al. teaches wherein (see Fig. 3), the first power domain is configured to transmit power from a power supply to a switch cell (this is a functional limitation/an intended use), the second power domain is configured to transmit power from the switch cell to a standard cell (this is a functional limitation/an intended use), and the second power domain can be cut off by the switch cell.
Regarding independent claim 18, LIN et al. teaches a method for manufacturing a semiconductor device (300, para [0040], see Fig. 3) on a wafer (310 substrate, para [0042] wherein the substrate is a part of the wafer), comprising:
forming a first back metal structure (BM0 left portion), extending in a first direction and belonging to a first power domain (VVDD);
forming a second back metal structure (BM0 right portion), extending in the first direction and belonging to a second power domain (TVDD) different from the first power domain (VVDD), wherein the second back metal structure (BM0 right portion) is spaced apart from the first back metal structure (BM0 left portion) along a second direction vertical to the first direction;
forming a first conductive structure (M0), extending in the first direction and formed above the second back metal structure (BM0); and
forming a metal layer structure (M1), extending in the second direction and formed above the first back metal structure (BM0) and the first conductive structure (M0), wherein the first back metal structure (BM0 left portion) and the second back metal structure (BM0 right portion) are formed on a back side (bottom side) of the wafer (310).
Regarding claim 20, LIN et al. teaches wherein (see Fig. 3), further comprising:
forming a through via structure (VD), extending in the first direction, wherein the through via structure (VD) is formed above the first back metal structure (BM0).
Allowable Subject Matter
8. Claims 9-17 are allowed.
Claim 9: the prior art of record alone or in combination neither teaches nor makes obvious a semiconductor device formed on a wafer, comprising:
….a first conductive structure extending in a first direction and formed above the first back metal structure, wherein the first conductive structure is P-type;
9. Claims 3-4, 6-7, 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 3: the prior art of record alone or in combination neither teaches nor makes obvious the semiconductor device comprising:
Claim 3 recites …. wherein the first conductive structure is P-type, and the second conductive structure is N-type.
Claim 6: the prior art of record alone or in combination neither teaches nor makes obvious the semiconductor device comprising:
Claim 6 recites ….further comprising:
a second front metal structure extending in the first direction and belonging to the second power domain, wherein the second front metal structure is formed above the metal layer structure and the first conductive structure, and the second front metal structure is formed on a front side of the wafer.
Claim 19: the prior art of record alone or in combination neither teaches nor makes obvious the method for manufacturing the semiconductor device on a wafer, comprising:
Claim 19 recites ….further comprising:
forming a second conductive structure, extending in the first direction, wherein the second conductive structure is formed between the first back metal structure and the metal layer structure; and
forming a first via structure, formed between the first back metal structure and the second conductive structure.
The prior art, LIN et al. (US 2023/0420369 A1) does not disclose the first conductive structure made of P-type material and the second conductive structure made of N-type material.
Examiner’s Note
10. Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs and/or columns/lines in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
11. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIDARUL MAZUMDER whose telephone number is (571)272-8823. The examiner can normally be reached M-F 9-5.
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12. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DIDARUL A MAZUMDER/Primary Examiner, Art Unit 2812
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