Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the filing of the Applicant Arguments/Remarks Made in an Amendment on 08/20/2026. Currently, claims 1-20 are pending in the application. Claims 16-20 have been withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 and 13 are rejected under 35 U.S.C. 103 as being obvious over CHEN (US 20220149195 A1).
Regarding claim 1, Figure 9 of CHEN discloses a semiconductor device, comprising:
a substrate (101, [0067]);
a tunnel insulating layer (207, [0073]) disposed over the substrate;
a floating gate (211, [0073]) disposed over the tunnel insulating layer;
a laterally oxidized intervention layer (209, [0073]) disposed over the floating gate;
a control gate (501, [0067]) disposed over the laterally oxidized intervention layer; and
a selection unit (401, [0067]) disposed on the substrate, wherein the selection unit comprises a selection unit insulating layer (403, [0081]) and a selection unit conductive layer (405, [0081]);
wherein the laterally oxidized intervention layer (209) comprises a sidewall portion (209F) and a center portion (middle of 209), and the sidewall portion has an oxygen concentration greater than that of the center portion ([0005]).
Figure 9 of CHEN does not explicitly teach a doped region contact disposed on the substrate at a position between the tunnel insulating layer and the control gate, and wherein a top surface of the doped region contact is positioned above a top surface of the control gate.
However, CHEN teaches that with reference to FIGS. 15 and 34 to 36, at step S19, in the embodiment depicted, a passivation insulating layer 105J may be formed on the substrate 101J, and a plurality of control contacts 601J and a plurality of doped region contacts 603J may be formed in the passivation insulating layer 105J. The passivation insulating layer 105J may be formed to cover the memory unit 201 and the selection unit 401. The plurality of control contacts 601J may be formed on the control unit 501J and in the passivation insulating layer 105J ([0119]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to use a doped region contact disposed on the substrate at a position between the tunnel insulating layer and the control gate, and wherein a top surface of the doped region contact is positioned above a top surface of the control gate in the device of CHEN (Figure 9) according to the teaching of CHEN from Figure 35/36 in order to have electrodes for driving the device in a variety of electronic applications ([0003] of CHEN).
Regarding claim 2, Figure 9 of CHEN in view of Figure 35/36 teaches that the semiconductor device of claim 1, wherein the selection unit (401) is separated from the floating gate (211) by the doped region contact (please see Figure 35/36 of CHEN).
Regarding claim 3, Figure 9 of CHEN in view of Figure 35/36 teaches that the semiconductor device of claim 2, further comprising a plurality of doped regions (301/303/305, [0084]) disposed in the substrate, and a first well region (107, [0085]) in the substrate, wherein the plurality of doped regions are disposed in the first well region, wherein the doped region contact is disposed on one of the doped regions (please see Figures 35/36 of CHEN).
Regarding claim 4, Figure 9 of CHEN discloses that the semiconductor device of claim 3, further comprising a plurality of selection unit spacers (409, [0081]) disposed on sidewalls of the selection unit (401), wherein the selection unit spacers (409) are disposed on the doped regions respectively, wherein the selection unit (401) does not contact any one of the doped regions.
Regarding claim 5, Figure 9 of CHEN discloses that the semiconductor device of claim 4, further comprising a selection unit capping layer (407, [0083]) disposed over the selection unit (401), wherein the selection unit insulating layer (403) has a thickness between about 5 angstroms and about 50 angstrom ([0082]), and wherein the selection unit conductive layer (405) has a thickness between about 150 nm and about 300 nm ([0082]).
Regarding claim 6, Figure 9 of CHEN in view of Figure 35/36 teaches that the semiconductor device of claim 5, further comprising a passivation insulating layer (105, [0067]) disposed on the substrate, wherein the passivation insulating layer covers the selection unit capping layer (407) and the selection unit spacers (409), wherein a top surface of the passivation insulating layer (105) is coplanar with the top surface of the doped region contact (please see Figures 35/36 of CHEN).
Regarding claim 13, Figure 9 of CHEN in view of Figure 35/36 teaches that the semiconductor device of claim 6, wherein the doped region contact is extended from the top surface of the passivation insulating layer (105) to a top surface of the substrate (101), wherein the doped region contact is the electrically coupled to the doped region (please see Figures 35/36 of CHEN).
Claims 7-9 are rejected under 35 U.S.C. 103 as being obvious over CHEN (US 20220149195 A1) in view of Cheng et al (US 20170373162 A1).
Regarding claims 7-9, Figure 9 of CHEN does not teach that the semiconductor device of claim 6, wherein the doped region contact is extended from the top surface of the passivation insulating layer into the substrate, wherein the doped region contact is electrically coupled to the doped region, wherein the doped region contact comprises a lower portion and an upper portion, wherein the lower portion of the doped region contact extends into the doped region and the upper portion of the doped region contact is surrounded by the passivation insulating layer and wherein the lower portion of the doped region contact has a first critical dimension, and the upper portion of the doped region contact has a second critical dimension greater than the first critical dimension.
However, Cheng is a pertinent art which teaches a field effect transistor structure with reduced contact resistance, and more particularly to reduce contact resistance between source/drains doped region and conductive source drain contacts ([0001]), wherein Figure 16 of Cheng teaches such a source/drains contact (230, [0095]), wherein the source/drains contact is electrically coupled to doped regions (120), wherein the source/drains contact (doped region contact) comprises a lower portion (within 120) and an upper portion (above the layer 120), wherein the lower portion of the source/drains contact extends into the doped region (120), and the upper portion of the source/drains contact is surrounded by a passivation insulating layer (210); and wherein the lower portion of the source/drains contact (230) has a first critical dimension, and the upper portion of the doped region contact has a second critical dimension greater than the first critical dimension.
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the device of CHEN as claimed according to the teaching of Cheng in order to improve contact resistance ([0001] of Cheng) between the doped region contacts (603 shown in Figure 2 applicable to structure of Figure 9) and the doped regions (301/303) in the device of CHEN.
Claims 10-12 are rejected under 35 U.S.C. 103 as being obvious over CHEN (US 20220149195 A1) in view of Cheng et al (US 20170373162 A1) as applied to claim above 9, and further in view of Chen (US 6150267 A).
Regarding claims 10-12, Figure 9 of CHEN in view of Cheng do not teach that the semiconductor device of claim 9, wherein the first critical dimension gradually decreases at positions of increasing distance from a top surface of the substrate, while the second critical dimension is constant, wherein a peripheral surface of the lower portion of the doped region contact is discontinuous with a peripheral surface of the upper portion of the doped region contact and wherein the lower portion of the doped region contact and the upper portion of the doped region contact are integrally formed.
However, Chen is a pertinent art which teaches a source/drain regions which gradually decreases at positions of increasing distance from a top surface of the substrate in Figure 3D in order to reduce contact resistance as well as leakage current (Col. 2, lines 50-55 and Col. 4, lines 40-50).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the device of CHEN in view of Cheng according to the teaching of Chen as claimed above in order to lower the leakage current (Col. 2, lines 50-55, Chen).
Claims 14-15 are rejected under 35 U.S.C. 103 as being obvious over CHEN (US 20220149195 A1) in view of Matsumoto et al (US 20020105046 A1).
Regarding claims 14-15, Figure 9 of CHEN does not teach that the semiconductor device of claim 13, wherein the doped region contact comprises a barrier layer and a conductive layer disposed over and surrounded by the barrier layer, wherein the passivation insulating layer surrounds the barrier layer of the doped region contact , wherein a top surface of the barrier layer, a top surface of the conductive layer, and the top surface of the passivation insulating layer are coplanar, and wherein the barrier layer has a first thickness on sidewalls of the conductive layer and a second thickness under a bottom surface of the conductive layer, wherein the first thickness of the barrier layer is less than the second thickness of the barrier layer.
However, Matsumoto is a pertinent art which teaches a an integrated semiconductor circuit device, wherein Figure 1 of Matsumoto teaches a source/drain contact 9 comprises a barrier layer and a conductive layer disposed over and surrounded by the barrier layer, wherein the barrier layer has a first thickness on sidewalls of the conductive layer and a second thickness under a bottom surface of the conductive layer, wherein the first thickness of the barrier layer is less than the second thickness of the barrier layer ([0046]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of CHEN (Figure 9) such that the doped region contact comprises a barrier layer and a conductive layer disposed over and surrounded by the barrier layer, wherein the passivation insulating layer surrounds the barrier layer of the doped region contact, wherein a top surface of the barrier layer, a top surface of the conductive layer, and the top surface of the passivation insulating layer are coplanar, and wherein the barrier layer has a first thickness on sidewalls of the conductive layer and a second thickness under a bottom surface of the conductive layer, wherein the first thickness of the barrier layer is less than the second thickness of the barrier layer according to the teaching of Matsumoto in order to provide a diffusion barrier between a conductive layer and the passivation layer.
Response to Arguments
Applicant's arguments filed on 08/20/2026 have been fully considered but they are not persuasive.
Applicant’s main arguments regarding claim 1 include: CHEN does not teach the limitation of “a doped region contact disposed on the substrate at a position between the tunnel insulating layer and the control gate and wherein a top surface of the doped region contact is positioned above a top surface of the control gate” added to claim 1.
In response, the Examiner respectfully points out that “A prior art reference must be considered in its entirety, i.e., as a whole, including portions that would lead away from the claimed invention, MPEP § 2141.02. In this case, Figure 9 of CHEN in combination with the teaching of Figures 35-36 of CHEN teach the amended limitations of claim 1 as explained in the rejection of claim 1 above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAJA AHMAD whose telephone number is (571)270-7991. The examiner can normally be reached on Monday to Friday from 8:00 AM to 5:00 PM (Eastern Time).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAJA AHMAD/
Primary Examiner, Art Unit 2813
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