Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the Applicant Election filled on 05/28/2026. Currently, claims 1-20 are pending in the application. Claims 16-20 have been withdrawn from consideration.
Election/Restrictions
Applicant's election without traverse of Group I and Species I (Figures 1-2 and 4), claims 1-15, in the reply filed on 05/28/2026 is acknowledged, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6 and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by CHEN (US 20220149195 A1).
Regarding claim 1, Figure 9 of CHEN discloses a semiconductor device, comprising:
a substrate (101, [0067]);
a tunnel insulating layer (207, [0073]) disposed over the substrate;
a floating gate (211, [0073]) disposed over the tunnel insulating layer;
a laterally oxidized intervention layer (209, [0073]) disposed over the floating gate;
a control gate (501, [0067]) disposed over the laterally oxidized intervention layer; and
a selection unit (401, [0067]) disposed on the substrate, wherein the selection unit comprises a selection unit insulating layer (403, [0081]) and a selection unit conductive layer (405, [0081]);
wherein the laterally oxidized intervention layer (209) comprises a sidewall portion (209F) and a center portion (middle of 209), and the sidewall portion has an oxygen concentration greater than that of the center portion ([0005]).
Regarding claim 2, Figure 9 of CHEN discloses that the semiconductor device of claim 1, wherein the selection unit (401) is separated from the floating gate (211).
Regarding claim 3, Figure 9 of CHEN discloses that the semiconductor device of claim 2, further comprising a plurality of doped regions (301/303/305, [0084]) disposed in the substrate, and a first well region (107, [0085]) in the substrate, wherein the plurality of doped regions are disposed in the first well region.
Regarding claim 4, Figure 9 of CHEN discloses that the semiconductor device of claim 3, further comprising a plurality of selection unit spacers (409, [0081]) disposed on sidewalls of the selection unit (401).
Regarding claim 5, Figure 9 of CHEN discloses that the semiconductor device of claim 4, further comprising a selection unit capping layer (407, [0083]) disposed over the selection unit (401), wherein the selection unit insulating layer (403) has a thickness between about 5 angstroms and about 50 angstrom ([0082]), and wherein the selection unit conductive layer (405) has a thickness between about 150 nm and about 300 nm ([0082]).
Regarding claim 6, Figure 9 of CHEN discloses that the semiconductor device of claim 5, further comprising a passivation insulating layer (105, [0067]) disposed on the substrate, wherein the passivation insulating layer covers the selection unit capping layer (407) and the selection unit spacers (409).
Regarding claim 13, Figure 2/9 of CHEN discloses that the semiconductor device of claim 6, further comprising a plurality of doped region contacts (not shown in Figure 9 but anticipated to have contact like 603 as shown in Figure 2, [0067]) extending from a top surface of the passivation insulating layer to a top surface of the substrate, wherein the doped region contacts are electrically coupled to the doped regions (301/303/305).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-9 are rejected under 35 U.S.C. 103 as being obvious over CHEN (US 20220149195 A1) in view of Cheng et al (US 20170373162 A1).
Regarding claims 7-9, Figure 9 of CHEN does not teach that the semiconductor device of claim 6, further comprising a plurality of doped region contacts extending from a top surface of the passivation insulating layer into the doped regions, wherein the doped region contacts are electrically coupled to the doped regions, wherein the doped region contact comprises a lower portion and an upper portion, wherein the lower portion of the doped region contact extends into the doped region and the upper portion of the doped region contact is surrounded by the passivation insulating layer and wherein the lower portion of the doped region contact has a first critical dimension, and the upper portion of the doped region contact has a second critical dimension greater than the first critical dimension.
However, Cheng is a pertinent art which teaches a field effect transistor structure with reduced contact resistance, and more particularly to reduce contact resistance between source/drains doped region and conductive source drain contacts ([0001]), wherein Figure 16 of Cheng teaches such a source/drains contact (230, [0095]), wherein the source/drains contact is electrically coupled to doped regions (120), wherein the source/drains contact (doped region contact) comprises a lower portion (within 120) and an upper portion (above the layer 120), wherein the lower portion of the source/drains contact extends into the doped region (120), and the upper portion of the source/drains contact is surrounded by a passivation insulating layer (210); and wherein the lower portion of the source/drains contact (230) has a first critical dimension, and the upper portion of the doped region contact has a second critical dimension greater than the first critical dimension.
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the device of CHEN as claimed according to the teaching of Cheng in order to improve contact resistance ([0001] of Cheng) between the doped region contacts (603 shown in Figure 2 applicable to structure of Figure 9) and the doped regions (301/303) in the device of CHEN.
Claims 10-12 are rejected under 35 U.S.C. 103 as being obvious over CHEN (US 20220149195 A1) in view of Cheng et al (US 20170373162 A1) as applied to claim above 9, and further in view of Chen (US 6150267 A).
Regarding claims 10-12, Figure 9 of CHEN in view of Cheng do not teach that the semiconductor device of claim 9, wherein the first critical dimension gradually decreases at positions of increasing distance from a top surface of the substrate, while the second critical dimension is constant, wherein a peripheral surface of the lower portion of the doped region contact is discontinuous with a peripheral surface of the upper portion of the doped region contact and wherein the lower portion of the doped region contact and the upper portion of the doped region contact are integrally formed.
However, Chen is a pertinent art which teaches a source/drain regions which gradually decreases at positions of increasing distance from a top surface of the substrate in Figure 3D in order to reduce contact resistance as well as leakage current (Col. 2, lines 50-55 and Col. 4, lines 40-50).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the device of CHEN in view of Cheng according to the teaching of Chen as claimed above in order to lower the leakage current (Col. 2, lines 50-55, Chen).
Claims 14-15 are rejected under 35 U.S.C. 103 as being obvious over CHEN (US 20220149195 A1) in view of Matsumoto et al (US 20020105046 A1).
Regarding claims 14-15, Figure 9 of CHEN does not teach that the semiconductor device of claim 13, wherein the doped region contact comprises a barrier layer and a conductive layer disposed over and surrounded by the barrier layer, wherein the passivation insulating layer surrounds the barrier layer of the doped region contact and wherein the barrier layer has a first thickness on sidewalls of the conductive layer and a second thickness under a bottom surface of the conductive layer, wherein the first thickness of the barrier layer is less than the second thickness of the barrier layer.
However, Matsumoto is a pertinent art which teaches a an integrated semiconductor circuit device, wherein Figure 1 of Matsumoto teaches a source/drain contact 9 comprises a barrier layer and a conductive layer disposed over and surrounded by the barrier layer, wherein the barrier layer has a first thickness on sidewalls of the conductive layer and a second thickness under a bottom surface of the conductive layer, wherein the first thickness of the barrier layer is less than the second thickness of the barrier layer ([0046]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of CHEN (Figure 9) such that the doped region contact comprises a barrier layer and a conductive layer disposed over and surrounded by the barrier layer, wherein the passivation insulating layer surrounds the barrier layer of the doped region contact and wherein the barrier layer has a first thickness on sidewalls of the conductive layer and a second thickness under a bottom surface of the conductive layer, wherein the first thickness of the barrier layer is less than the second thickness of the barrier layer according to the teaching of Matsumoto in order to provide a diffusion barrier between a conductive layer and the passivation layer.
Examiner Notes
A reference to specific paragraphs, columns, pages, or figures in a cited prior art reference is not limited to preferred embodiments or any specific examples. It is well settled that a prior art reference, in its entirety, must be considered for all that it expressly teaches and fairly suggests to one having ordinary skill in the art. Stated differently, a prior art disclosure reading on a limitation of Applicant's claim cannot be ignored on the ground that other embodiments disclosed were instead cited. Therefore, the Examiner's citation to a specific portion of a single prior art reference is not intended to exclusively dictate, but rather, to demonstrate an exemplary disclosure commensurate with the specific limitations being addressed. In re Heck, 699 F.2d 1331, 1332-33,216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)). In re: Upsher-Smith Labs. v. Pamlab, LLC, 412 F.3d 1319, 1323, 75 USPQ2d 1213, 1215 (Fed. Cir. 2005); In re Fritch, 972 F.2d 1260, 1264, 23 USPQ2d 1780, 1782 (Fed. Cir. 1992); Merck& Co. v. BiocraftLabs., Inc., 874 F.2d 804, 807, 10 USPQ2d 1843, 1846 (Fed. Cir. 1989); In re Fracalossi, 681 F.2d 792,794 n.1, 215 USPQ 569, 570 n.1 (CCPA 1982); In re Lamberti, 545 F.2d 747, 750, 192 USPQ 278, 280 (CCPA 1976); In re Bozek, 416 F.2d 1385, 1390, 163 USPQ 545, 549 (CCPA 1969).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAJA AHMAD whose telephone number is (571)270-7991. The examiner can normally be reached on Monday-Friday, 8:00 AM - 5:00 PM (Eastern Time).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice .
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KHAJA AHMAD/Primary Examiner, Art Unit 2813
Prosecution Insights