Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
1. Applicant's election, without traverse, of claims 11-20 in the “Response to Restriction Requirement” filed on 05/28/2026 is acknowledged and entered by the Examiner. Applicant’s cancellation of claims 1-10 in “Claims” filed on 05/28/2026 is acknowledged.
This office action consider claims 11-20 pending for prosecution.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:-
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (100; Fig 3A; [0063]) = (element 100; Figure No. 3A; Paragraph No. [0063]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
2. Claims 11-15 and 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hijioka et al. (US 20130092993 A1; hereinafter Hijioka).
Regarding claim 11, Hijioka teaches a semiconductor structure (see the entire document, specifically Fig. 1+; [0011+], and as cited below), comprising:
a substrate (1; Fig. 18; see [0039]);
a lower electrode layer (13; Fig. 18; see [0036]), disposed on the substrate (1; Fig. 18; see [0039]);
a first dielectric layer ({7b, 6c}; Fig. 18; [0056]), disposed on the lower electrode layer (13; Fig. 18; see [0036]);
a second dielectric layer ({7c, 6d, 7d}; Fig. 18; [0056]), disposed on the first dielectric layer ({7b, 6c}; Fig. 18; [0056]); and
a plurality of capacitor structures (see Fig. 18; see [0098-0112]), disposed in the first dielectric layer ({7b, 6c}; Fig. 18; [0056]) and the second dielectric layer ({7c, 6d, 7d}; Fig. 18; [0056]), and each of the plurality of capacitor structures (see Fig. 18; see [0098-0112]) comprising:
a sealing layer (17; Fig. 18; see [0064, 0067, 0106]), disposed in an upper portion of each of the plurality of capacitor structures (see Fig. 18; see [0098-0112]);
a first conductive layer (31; Fig. 18; see [0104]), disposed over the lower electrode layer (13; Fig. 18; see [0036]) and surrounding a sidewall and a bottom surface of the sealing layer (17; Fig. 18; see [0064, 0067, 0106]);
a top capacitor plate (16; Fig. 18; see [0058, 0101]), disposed over the lower electrode (13; Fig. 18; see [0036]) layer and surrounding a sidewall and a bottom surface of the first conductive layer (31; Fig. 18; see [0104]);
an oxide layer (15; Fig. 18; see [0101]), disposed over the lower electrode layer (13; Fig. 18; see [0036]) and surrounding a sidewall and a bottom surface of the top capacitor plate (16; Fig. 18; see [0101]); and
a bottom capacitor plate (14; Fig. 18; see [0100]), disposed on the lower electrode layer (13; Fig. 18; see [0036]) and surrounding a sidewall and a bottom surface of the oxide layer (15; Fig. 18; see [0101]).
Regarding claim 12, Hijioka teaches all of the features of claim 11.
Hijioka further comprising: a second conductive layer (18a; Fig. 18; see [0060, 0064]), disposed over the first conductive layer (31; Fig. 18; see [0104]) and the top capacitor plate (16; Fig. 18; see [0058, 0101]); a second film layer (barrier metal film around 18a; see Fig. 18; see [0067, 0068]), surrounding a sidewall and a bottom surface of the second conductive layer (18a; Fig. 18; see [0060, 0064]); and a first film layer (7d; see Fig. 18; see [0107]), surrounding a sidewall and a bottom surface of the second film layer (barrier metal film around 18a; see Fig. 18; see [0067, 0068]).
Regarding claim 13, Hijioka teaches all of the features of claim 11.
Hijioka further teaches wherein a bottom surface of the bottom capacitor plate (14; Fig. 18; see [0100]) contacts a top surface of the lower electrode layer (13; Fig. 18; see [0100]).
Regarding claim 14, Hijioka teaches all of the features of claim 11.
Hijioka further teaches wherein an upper portion of the first conductive layer (31; Fig. 18; see [0104]) has an upper width, a lower portion of the first conductive layer (31; Fig. 18; see [0104]) has a lower width, and the upper width is greater than the lower width (see Fig. 18).
Regarding claim 15, Hijioka teaches all of the features of claim 11.
Hijioka further teaches wherein the sealing layer (17; Fig. 18; see [0064, 0067, 0106]) is a U-shape in a cross-section view.
Regarding claim 17, Hijioka teaches all of the features of claim 12.
Hijioka further teaches wherein a top surface of the second conductive layer (18a; Fig. 18; see [0060, 0064]) and a top surface of the second dielectric layer ({7c, 6d, 7d}; Fig. 18; [0056]) are coplanar.
Regarding claim 18, Hijioka teaches all of the features of claim 11.
Hijioka further teaches wherein the top capacitor plate (16; Fig. 18; see [0058, 0101]; titanium nitride) comprises TiN.
Regarding claim 19, Hijioka teaches all of the features of claim 11.
Hijioka further teaches wherein the sealing layer (17; Fig. 18; see [0064, 0067, 0106]; see [0064] in view of [0067]; titanium nitride) comprises TiN.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
3. Claim 16 is rejected under 35 U.S.C.103 as being unpatentable over Hijioka et al. (US 20130092993 A1; hereinafter Hijioka), in view of the following statement.
Regarding claim 16, Hijioka teaches all of the features of claim 12.
Hijioka further teaches wherein the oxide layer (15; Fig. 18; see [0101]) on an upper portion of an inner sidewall of the second dielectric layer ({7c, 6d, 7d}; Fig. 18; [0056]) (see below for “surrounds a sidewall of”) the first film layer (7d; see Fig. 18; see [0107]).
As noted above, Hijioka does not expressly disclose “wherein the oxide layer on an upper portion of an inner sidewall of the second dielectric layer surrounds a sidewall of” the first film layer”.
However, the Applicant has not presented persuasive evidence that the claimed “wherein the oxide layer on an upper portion of an inner sidewall of the second dielectric layer surrounds a sidewall of” the first film layer” is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work wherein the oxide layer on an upper portion of an inner sidewall of the second dielectric layer surrounds a sidewall of” the first film layer). Also, the Applicant has not shown that “wherein the oxide layer on an upper portion of an inner sidewall of the second dielectric layer surrounds a sidewall of” the first film layer” produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. Therefore, no rationale is given that the invention will not function without “wherein the oxide layer on an upper portion of an inner sidewall of the second dielectric layer surrounds a sidewall of” the first film layer”. Thus, the claimed “wherein the oxide layer on an upper portion of an inner sidewall of the second dielectric layer surrounds a sidewall of” the first film layer” is not critical to the invention.
Examiner would like to note that MPEP §2144.04.IV(B) guideline, where change of shape is a Legal Precedent as Source of Supporting Rationale. See In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.).
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In view of the above, as there is no persuasive evidence that the particular configuration of “wherein the oxide layer on an upper portion of an inner sidewall of the second dielectric layer surrounds a sidewall of” the first film layer” is significant. Thus, the claimed limitation of “wherein the oxide layer on an upper portion of an inner sidewall of the second dielectric layer surrounds a sidewall of” the first film layer” is a matter of choice which a person of ordinary skill in the art would have found obvious as per MPEP §2144.04.IV(B) guideline. Therefore, the claimed limitation of “wherein the oxide layer on an upper portion of an inner sidewall of the second dielectric layer surrounds a sidewall of” the first film layer” is not patentable over Hijioka.
4. Claim 20 is rejected under 35 U.S.C.103 as being unpatentable over Hijioka et al. (US 20130092993 A1; hereinafter Hijioka), in view of Takase et al. (US 20210013253 A1; hereinafter Takase).
Regarding claim 20, Hijioka teaches all of the features of claim 12.
Hijioka further teaches wherein the second conductive layer (18b; Fig. 18; see [0060, 0064]) (see below for “comprises indium tin oxides”).
As noted above, Hijioka does not expressly disclose “wherein the second conductive layer comprises indium tin oxides”.
However, in the analogous art, Takase teaches an electronic device ([0001]), wherein (Figs. 1+; [0001+]) a transparent electrode (216; Fig. 7; [0122]) is formed over a capacitor (200; [0124]), where the transparent electrode (216; Fig. 7; [0122]) comprises of a transparent conductive film such as indium tin oxide (ITO).
It would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to modify Hijioka’s conductive layer material in view of Takase’s electrode conductive material, and thereby, modified Hijioka’s (by Chia) device will have wherein the second conductive layer (Hijioka 18b; Fig. 18; see [0060, 0064] in view of material of Takase 216; Fig. 7; [0122]) comprises indium tin oxides (in view of material of Takase 216; Fig. 7; [0122]; indium tin oxide (ITO)).
The ordinary artisan would have been motivated to modify Vincent in the manner set forth above, at least, because this inclusion provides a conductor layer comprising of a transparent conductive film such as indium tin oxide (ITO) (Takase [0122]), where indium tin oxide (ITO) is a known material that combines high electrical conductivity and optical transparency, which is beneficial for electronic devices and applications.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Omar Mojaddedi whose telephone number is 313-446-6582. The examiner can normally be reached on Monday – Friday, 8:00 a.m. to 4:00 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado, can be reached on 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/OMAR F MOJADDEDI/Examiner, Art Unit 2898
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