CTNF 18/443,917 CTNF 89223 DETAILED ACTION 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-8 and 10 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Mathew et al. (US 2006/0022264) (hereafter Mathew) . Regarding claim 1 , Mathew (see upside down figures of Figs. 9 and 11) discloses a device comprising: a channel layer 16 (Fig. 9, paragraph 0020); a gate structure (20 and 22 in Fig. 9, paragraph 0023) across the channel layer 16 (Fig. 9), wherein the gate structure (20 and 22 in Fig. 9) comprises: a gate dielectric layer 20 (Fig. 9, paragraph 0023); and a gate electrode 22 (Fig. 9, paragraph 0023) over the gate dielectric layer 20 (Fig. 9); a source/drain epitaxial structure (32 and 34 in Fig. 9, paragraph 0027) adjacent the gate structure (20 and 22 in Fig. 9) and electrically connected to the channel layer 16 (Fig. 9); and a gate via 66 (Fig. 11, paragraph 0037) under the gate structure (20 and 22 in Fig. 11) and in contact with the gate electrode 22 (Fig. 11). Regarding claim 2 , Mathew further discloses the device of claim 1, wherein the gate via 66 (Fig. 11) passes through the channel layer 16 (Fig. 11). Regarding claim 3 , Mathew further discloses the device of claim 2, further comprising a spacer structure 18 (Fig. 11, paragraph 0021) in contact with the gate via 66 (Fig. 11) and the channel layer 16 (Fig. 11). Regarding claim 4 , Mathew further discloses the device of claim 1, wherein the gate via 66 (Fig. 11) passes through the gate dielectric layer 20 (Fig. 11) of the gate structure (20 and 22 in Fig. 11). Regarding claim 5 , Mathew further discloses the device of claim 1, further comprising an isolation structure (18 and 46 in Fig. 11) adjacent (see Fig. 9, wherein the source/drain epitaxial structure (32 and 34) being adjacent the gate structure (20 and 22); and see Fig. 11, wherein the isolation structure (18 and 46) being adjacent the gate structure (20 and 22)) the source/drain epitaxial structure (32 and 34 in Fig. 9) and under the gate structure (20 and 22 in Fig. 11), wherein the gate via 66 (Fig. 11) is embedded in the isolation structure (18 and 46 in Fig. 11). Regarding claim 6 , Mathew further discloses the device of claim 5, wherein a top surface of the isolation structure (18 and 46 in Fig. 11) is lower (see upside down figure of Fig. 11, wherein top surface of 46 is lower than top surface of 66) than a top surface of the gate via 66 (fig. 11). Regarding claim 7 , Mathew further discloses the device of claim 1, further comprising a dielectric cap 36 (Fig. 11, paragraph 0028) over the gate structure (20 and 22 in Fig. 11), such that the gate structure (20 and 22 in Fig. 11) is between the dielectric cap 36 (Fig. 11) and the gate via 66 (Fig. 11). Regarding claim 8 , Mathew further discloses the device of claim 1, further comprising an ILD layer 36 (Fig. 11, paragraph 0028) surrounding the gate structure (20 and 22 in Fig. 11), wherein a top surface of the ILD layer 36 (Fig. 11) is higher than a top surface of the gate via 66 (Fig. 11). Regarding claim 10 , Mathew further discloses the device of claim 1, wherein the gate structure (20 and 22 in Fig. 11) surrounds a top portion of the gate via 66 (Fig. 11) . 07-15 AIA Claim 11 is rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Lilak et al. (US 2020/0294998) (hereafter Lilak) . Regarding claim 11 , Lilak (see upside down figure of Fig. 1A) discloses a device comprising: a semiconductive fin (116B and 124B in Fig. 1A, paragraph 0013); a gate structure (120B and 122B in Fig. 1A, paragraph 0021) across (see Fig. 3A) the semiconductive fin 116B (Fig. 1A); a front-side multilayer interconnection (MLI) structure 103 (Fig. 1A, paragraph 0013) over the gate structure (120B and 122B in Fig. 1A); a backside MLI structure (M N in Fig. 1A, paragraph 0029) under the semiconductive fin 116B (Fig. 1A); and a gate via (M 0 in Fig. 1A, paragraph 0029) electrically connected to the gate structure (120B and 122B in Fig. 1A) and the backside MLI structure (M N in Fig. 1A) . 07-15 AIA Claim s 16-20 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Doris et al. (US 2013/0299897) (hereafter Doris) . Regarding claim 16 , Doris (see upside down figure of Fig. 15) discloses a device comprising: a channel layer 32 (Fig. 15, paragraph 0048); a gate structure (54, 52, and 86 in Fig. 15) wrapping around the channel layer 32 (Fig. 15); a first source/drain epitaxial structure 62A (Fig. 15, paragraph 0077) and a second source/drain epitaxial structure 62B (Fig. 15, paragraph 0077) connected to the channel layer 32 (Fig. 15); a dielectric cap 58 (Fig. 15, paragraph 0051) covering the gate structure (54, 52, and 86 in Fig. 15); and a gate via (96 and 106 in Fig. 15, paragraph 0078) connected to the gate structure (54, 52, and 86 in Fig. 15), wherein the gate via (96 and 106 in Fig. 15) is closer to the channel layer 32 (Fig. 15) than to the dielectric cap 58 (Fig. 15). Regarding claim 17 , Doris further discloses the device of claim 16, wherein the gate via (96 and 106 in Fig. 15) is directly under the dielectric cap 58 (Fig. 15). Regarding claim 18 , Doris further discloses the device of claim 16, wherein the gate via (96 and 106 in Fig. 15) is directly under the channel layer 32 (Fig. 15. Regarding claim 19 , Doris further discloses the device of claim 16, further comprising an isolation structure 100 (Fig. 15, paragraph 0070) under the gate structure (54, 52, and 86 in Fig. 15), wherein the gate via (96 and 106 in Fig. 15) is embedded in the isolation structure 100 (Fig. 15). Regarding claim 20 , Doris further discloses the device of claim 16, further comprising a dielectric spacer 82 (Fig. 15, paragraph 0066) surrounding the gate via (96 and 106 in Fig. 15) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-22-aia AIA Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Mathew as applied to claim 1 above, and further in view of Imai et al. (US 2021/0183899) (hereafter Imai) . Regarding claim 9 , Mathew discloses the device of claim 1, however Mathew does not disclose the gate via tapers downward. Imai discloses the gate via (CHg in Fig. 5B, paragraph 0207, wherein “tapered shape” ) tapers downward. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Mathew to form the gate via tapers downward, as taught by Imai, since at least a part of the gate contact hole CHg (Imai, Fig. 5B, paragraph 0218) is located on the gate electrode GE (Imai, Fig. 5B, paragraph 0218) even when misalignment occurs such that electrical connection with the gate electrode GE (Imai, Fig. 5B, paragraph 0218) and the gate bus line GL (Imai, Fig. 5B, paragraph 0218) can be secured . 07-22-aia AIA Claim s 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Lilak as applied to claim 11 above, and further in view of Doris et al. (US 2013/0299897) (hereafter Doris) . Regarding claim 12 , Lilak discloses the device of claim 11, however Lilak does not disclose comprising a spacer structure surrounding the gate via, wherein the gate via and the spacer structure are embedded in the semiconductive fin. Doris discloses comprising a spacer structure 82 (Fig. 15, paragraph 0066) surrounding the gate via (96 and 106 in Fig. 15, paragraph 0078), wherein the gate via (96 and 106 in Fig. 15) and the spacer structure 82 (Fig. 15) are embedded in the semiconductive fin (32, 62A, and 62B in Fig. 15). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Mathew to form a spacer structure surrounding the gate via, wherein the gate via and the spacer structure are embedded in the semiconductive fin, as taught by Doris, since a spacer structure 82 (Doris, Fig. 15) electrically isolates between a gate via (Doris, 96 and 106 in Fig. 15) and source/drain contact via structures (Doris, 92A, 92B, 102A, and 102B in Fig. 15). Regarding claim 13 , Lilak discloses the device of claim 11, however Lilak does not disclose an isolation structure surrounding the semiconductive fin and under the gate structure, wherein the gate via is embedded in the isolation structure. Doris discloses an isolation structure 82 (Fig. 15, paragraph 0066) surrounding the semiconductive fin (32, 62A, and 62B in Fig. 15) and under (see upside down figure of Fig. 15) the gate structure (54 and 86 in Fig. 15), wherein the gate via (96 and 106 in Fig. 15, paragraph 0078) is embedded in the isolation structure 82 (Fig. 15). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Mathew to form an isolation structure surrounding the semiconductive fin and under the gate structure, wherein the gate via is embedded in the isolation structure, as taught by Doris, since a spacer structure 82 (Doris, Fig. 15) electrically isolates between a gate via (Doris, 96 and 106 in Fig. 15) and source/drain contact via structures (Doris, 92A, 92B, 102A, and 102B in Fig. 15). Regarding claim 14 , Lilak discloses the device of claim 11, however Lilak does not disclose a top surface of the gate via is lower than a top surface of the gate structure. Doris discloses a top surface of the gate via (96 and 106 in Fig. 15, paragraph 0078) is lower (see upside down figure of Fig. 15) than a top surface of the gate structure 54 (Fig. 15). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Mathew to form a top surface of the gate via is lower than a top surface of the gate structure, as taught by Doris, since a back gate contact via structure 106 (Doris, Fig. 15, paragraph 0078) can be formed, which is electrically shorted to the back gate electrode 86 (Doris, Fig. 15, paragraph 0078) through the back gate metal semiconductor alloy portion 96 (Doris, Fig. 15, paragraph 0078). Regarding claim 15 , Lilak further discloses the device of claim 11, further comprising source/drain epitaxial structures 124B (Fig. 1A, paragraph 0013) connected to the semiconductive fin 116B (Fig. 1A) and on opposite sides of the gate structure (120B and 122B in Fig. 1A). Lilak does not disclose a top surface of the gate via is higher than a bottom surface of one of the source/drain epitaxial structures. Doris discloses a top surface of the gate via (96 and 106 in Fig. 15, paragraph 0078) is higher (see upside down figure of Fig. 15) than a bottom surface of one of the source/drain epitaxial structures (62A and 62B in Fig. 15, paragraph 0052). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Mathew to form a top surface of the gate via is higher than a bottom surface of one of the source/drain epitaxial structures, as taught by Doris, since a back gate contact via structure 106 (Doris, Fig. 15, paragraph 0078) can be formed, which is electrically shorted to the back gate electrode 86 (Doris, Fig. 15, paragraph 0078) through the back gate metal semiconductor alloy portion 96 (Doris, Fig. 15, paragraph 0078). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAMONT B KOO whose telephone number is (571)272-0984. The examiner can normally be reached 7:00 AM - 3:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /L.B.K/Examiner, Art Unit 2813 /STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813 Application/Control Number: 18/443,917 Page 2 Art Unit: 2813 Application/Control Number: 18/443,917 Page 3 Art Unit: 2813 Application/Control Number: 18/443,917 Page 4 Art Unit: 2813 Application/Control Number: 18/443,917 Page 5 Art Unit: 2813 Application/Control Number: 18/443,917 Page 6 Art Unit: 2813 Application/Control Number: 18/443,917 Page 7 Art Unit: 2813 Application/Control Number: 18/443,917 Page 8 Art Unit: 2813 Application/Control Number: 18/443,917 Page 9 Art Unit: 2813
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