DETAILED ACTION
Examiner’s Note
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs, columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Election/Restrictions
Applicant’s election without traverse of Invention II (method of making semiconductor device), species A, reflected in claims Figs. 1, 2A-2C in the reply filed on 07/02/2026 is acknowledged. Claims 15-20 are cancelled.
Claims 5-7 include features (forming another conductive contact plug passing through the another interlayer dielectric layer to electrically connect to the metal gate structure) of species B/fig. 3-4 and will be considered as withdrawn.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The elected drawings fig. 1, 2A-2C must show every feature of the invention specified in the claims. Therefore, elements described below must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
fin structure (claims 1-2, 8-9): applicant’s specification mentions reference 129 as fin structure in fig. 1, 2A and reference 111 as base portion of the fin structure in fig. 1, 2A-2B. However, this is not clear which portion of device 100 is considered as a fin structure, i.e., a thin, vertical semiconductor part protruded from the substrate. A boundary of element 129 needs to be drawn in the applicant’s drawings.
at least one interlayer dielectric layer (claims 1-2, 8-9), the interlayer dielectric layer (claims 3-5, 9-12, claims 21-22, 24-25), another interlayer dielectric layer (claims 5-7, 12-14 and 25-26),
claims 1-14, 21-26 describe a method of forming components of ‘a semiconductor device’ using several steps e.g., forming a fin structure, gate structure, isolation region, conductive contact layer, contact plug etc. and depositing, etching, removing, laterally etching etc. and some of the steps have sequences (¶ [0022] mentions ‘After the stacked semiconductor layers are formed, fin structures are formed’, ¶ [0024] mentions, ‘After the fin structures 129 are formed, an insulating material layer (not shown) including one or more layers of insulating material is formed’, ¶ [0025] describes ‘Then, as shown in FIG. 2A, the insulating material layer is recessed to form an isolation insulating layer 115’, ¶ [0027] describes, ‘After the isolation insulating layer is formed, a sacrificial (dummy) gate structure is formed’ etc.). Applicant’s specification points to fig. 2A-2C (mostly fig. 2A) for these steps. However, fig. 2A shows a structure having most of the componenets already formed and thus failed to show individual steps elaborating sequence of the steps. Thus, applicant’s drawings fail to show the steps of the claimed method.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description:
Fig. 1 shows the gate dielectric layer 182 and the gate electrode layer 184 wrong.
¶ [017] of the applicant’s specification describes ‘As shown FIG. 1, the cross section, perpendicular to the Y direction, of the insulating inner spacer 135 has a rounded convex shape (e.g., semi-circular or U-shape) toward the gate electrode layer 184’. However, fig. 1 doesn’t show any rounded convex shape of element 135.
¶ [018] of the applicant’s specification describes ‘a conductive contact plug 175 passing though the ILD layer 170 is disposed over the conductive contact layer 172’. However, fig. 1 doesn’t show elements 175.
This application has more discrepancies among written descriptions, drawings and claims than the described above. The applicant is requested by the office to review the whole specification along with the drawings and claims to ensure the steps of the claimed method and claimed elements are described/shown.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-4 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claims 2-4, 12-14 recite the limitation " the interlayer dielectric layer ". There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 8-11 and 21-26 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Sung et al. (US 20240284687 A1, hereinafter Sung’687).
Regarding independent claim 1, Sung’687 teaches, “A method of manufacturing a semiconductor device (fig. 1-39; ¶ [0001] - ¶ [0155]), comprising:
forming a fin structure (nanosheet stack, fig. 2-3) over a substrate (102);
forming a sacrificial gate structure (112, 116-2, fig. 4) over the fin structure;
etching a source/drain region of the fin structure (fig. 7), the source/drain region being not covered by the sacrificial gate structure, thereby forming a source/drain space;
forming an isolation region (116-1, fig. 7) at a bottom portion of the source/drain space;
forming a doped source/drain epitaxial layer (120, fig. 9) over the isolation region (116) in the source/drain space;
forming a conductive contact layer (124, fig. 10) over the doped source/drain epitaxial layer (120); and
forming at least one interlayer dielectric layer (126) and forming at least one conductive contact plug (128, 130, 132) passing through the at least one interlayer dielectric layer (126) to electrically connect to the conductive contact layer (124)”.
Regarding claim 2, Sung’687 further teaches, “The method of claim 1, further comprising:
removing the sacrificial gate structure (112, figs. 9-10); and
forming a metal gate structure (122) over the fin structure, wherein the interlayer dielectric layer (126) surrounds side walls of the metal gate structure (112)”.
Regarding claim 3, Sung’687 further teaches, “The method of claim 2, wherein the interlayer dielectric layer is a low dielectric constant silicon carbide film (¶ [0094])”.
Regarding claim 4, Sung’687 further teaches, “The method of claim 3, wherein the interlayer dielectric layer is made of SiOC, and the dielectric constant of SiOC is equal to or less than 3.1 (¶ [0094])”.
Regarding independent claim 8, Sung’687 teaches, “A method of manufacturing a semiconductor device (fig. 1-39; ¶ [0001] - ¶ [0155]), comprising:
forming a fin structure (nanosheet stack, fig. 2-3) in which first semiconductor layers (106) and second semiconductor layers (104) are alternately stacked;
forming a sacrificial gate structure (112, 116-2, fig. 4) over the fin structure;
etching a source/drain region of the fin structure (fig. 7), the source/drain region being not covered by the sacrificial gate structure, thereby forming a source/drain space;
forming cavities (fig. 8; ¶ [0088]) on an end of each of the first semiconductor layers where the first semiconductor layers (106) intersect with the source/drain space by laterally etching the first semiconductor layers through the source/drain space;
forming an inner spacer (118) made of a dielectric material in the cavities of the first semiconductor layers (106);
forming an electrical isolation region (116-1) at a bottom of the source/drain region; and
forming a doped source/drain epitaxial layer (120, fig. 9) over the isolation region (116) in the source/drain space;
forming a conductive contact layer (124, fig. 10) over the doped source/drain epitaxial layer (120); and
forming at least one interlayer dielectric layer (126, fig. 11) and forming at least one conductive contact plug (128, 130, 132) passing through the at least one interlayer dielectric layer (126) to electrically connect to the conductive contact layer (124)”.
Regarding claim 9, Sung’687 further teaches, “The method of claim 8, further comprising:
removing the sacrificial gate structure (112, figs. 9-10); and
forming a metal gate structure (122) over the fin structure, wherein the interlayer dielectric layer (126) surrounds side walls of the metal gate structure (112)”.
Regarding claim 10, Sung’687 further teaches, “The method of claim 9, wherein the interlayer dielectric layer is a low dielectric constant silicon carbide film (¶ [0094])”.
Regarding claim 11, Sung’687 further teaches, “The method of claim 10, wherein the interlayer dielectric layer is made of SiOC, and the dielectric constant of SiOC is equal to or less than 3.1 (¶ [0094])”.
Regarding independent claim 21, Sung’687 teaches, “A method of manufacturing a semiconductor device (fig. 1-39; ¶ [0001] - ¶ [0155]), comprising:
forming a plurality of semiconductor nanostructures (nanosheet stack, fig. 2-3) over a substrate (102);
forming an electrical isolation region (116, fig. 7) in a drain region and a source region of the substrate (102);
forming a doped source/drain epitaxial layer (120) over the electrical isolation region and in contact with the semiconductor nanostructures;
forming a gate dielectric layer (122, ¶ [0091]) surrounding channel regions of the semiconductor nanostructures;
forming a gate electrode layer (122, ¶ [0091]) surrounding the gate dielectric layer;
forming a conductive contact layer (124, fig. 10) over the doped source/drain epitaxial layer (120);
depositing an interlayer dielectric layer (126, fig. 10) over the conductive contact layer (124), wherein the interlayer dielectric layer (126) comprises a silicon carbide (SiOC, ¶ [0094]) film; and
forming at least one conductive contact plug (128, 130, 132, fig. 11) through the interlayer dielectric layer (126) to electrically connect to the conductive contact layer (124)”.
Regarding claim 22, Sung’687 further teaches, “The method of claim 21, wherein depositing the interlayer dielectric layer (126, fig. 11) comprises surrounding sidewalls of the conductive contact layer (124) with the silicon carbide film”.
Regarding claim 23, Sung’687 further teaches, “The method of claim 21, wherein the silicon carbide film has a dielectric constant equal to or less than about 3.1, ¶ [0094]”.
Regarding claim 24, Sung’687 further teaches, “The method of claim 21, further comprising:
forming a replacement metal gate structure (122, fig. 10) over the semiconductor nanostructures before depositing the interlayer dielectric layer (126),
wherein depositing the interlayer dielectric layer (126) comprises surrounding sidewalls of the replacement metal gate structure (122) with the silicon carbide film”.
Regarding claim 25, Sung’687 further teaches, “The method of claim 24, further comprising:
forming another interlayer dielectric layer (148, fig. 15) over the replacement metal gate structure (122) and the interlayer dielectric layer (126);
forming another conductive contact plug (142, 144, 146) through the another interlayer dielectric layer (148) to electrically connect to the conductive contact layer (124)”.
Regarding claim 26, Sung’687 further teaches, “The method of claim 25, wherein the another interlayer dielectric layer (148) is made of SiOC, and the dielectric constant of SiOC is equal to or less than 3.1 (¶ [0100], ¶ [0094])”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266 and email address is mohammad.hoque@uspto.gov. The examiner can normally be reached 9AM-7PM EST.
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/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817
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