DETAILED ACTION
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on March 11, 2026, has been entered.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The prior §112 rejections are withdrawn in view of the amended claims.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 32 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 32 is currently amended to recite the coupling mechanism material layer is a continuous layer thereby adding new matter. Previously the claim stated the coupling mechanism material layer includes a plurality of “discrete blocks”, consistent with Fig. 8A showing the individual blocks 32 are spaced apart, and are not a continuous layer. Claim 34 similarly recites a plurality of blocks of coupling mechanism material, also consistent with Fig. 8A. The coupling mechanism material layer is not a continuous layer according to the figures, further noting the specification refers to “blocks 32”.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 16, 18, 20-22, 25, 27-29, 33-35, and 38 are rejected under 35 U.S.C. 103 as being unpatentable over Truhitte et al. (US 2016/0027694), of record, in view of Sirinorakul (US 2011/0241189), newly cited, and Shimoyama et al. (US 2008/0032485), of record.
(Re Claim 16) Truhitte teaches an assembly, comprising (see Figs. 26A-26H and supporting text):
a semiconductor wafer (94) with an array of devices fabricated on a frontside thereof (note the devices having symmetric contacts/terminals on opposite sides being vertical devices thus the devices are on either or both sides);
a coupling mechanism material layer (90) disposed on a backside of the semiconductor wafer; and
a one-piece panel of spacer blocks (88) having a bottom surface disposed on the coupling mechanism material layer, the one-piece panel of spacer blocks including an array of spacer blocks with connecting strips of metal joining adjacent spacer blocks, the spacer blocks in the one-piece panel of spacer blocks being bonded to the backside of the semiconductor wafer, the connecting strips joining adjacent spacer blocks in the one-piece panel of spacer blocks being severable in a wafer singulation action to separate individual vertical device stacks, each of the individual vertical device stacks including a device die bonded to a spacer block (Fig. 26D).
Truhitte is silent regarding the connecting strips being recessed from the bottom surface. A PHOSITA desiring to make, use and improve upon Truhitte’s assembly would be motivated to look to related art to teach possible alternatives for the panel of spacer blocks to determine if other shapes are advantageous. Related art from Shimoyama teaches the connecting strips can be coplanar with the bottom surface (Fig. 4B, corresponding to Truhitte’s 88), or recesses can be formed from both sides (Fig. 4C). Related art from Sirinorakul (see Figs. 1-4E) also teaches the connecting strips can be coplanar with the bottom surface (Fig. 4C, corresponding to Truhitte’s 88) or recesses can be formed from both sides (Fig. 4E). From the disclosures of Shimoyama and Sirinorakul, the two different structures are art recognized alternatives, both obvious to try, each having predictable results and an expectation of success. Shimoyama (¶¶11-13,30) and Sirinorakul (¶¶3-8, 32-33,40), both recognize that their structures are advantageous when dicing (e.g. blade wear, burrs, chipping, etc.). A PHOSITA would find it obvious to try the alternative wherein the connecting strips are recessed from both sides as taught by both Shimoyama and Sirinorakul for the dicing advantages noted by each.
(Re Claim 18) wherein the device die is about 100 microns thick or less (¶88, the wafer may be about 4 mils thick which is about 100 microns).
(Re Claim 20) wherein the one-piece panel of spacer blocks has a planar shape conforming to a shape of the semiconductor wafer (Fig. 26C).
(Re Claim 21) wherein each of the individual vertical device stacks is configured to be moved and placed in a circuit package as a single pre-formed unit (Fig. 26C).
(Re Claim 22) wherein a spacer block structurally reinforces the device die (Fig. 26C).
(Re Claim 25) wherein the spacer blocks in the one-piece panel of spacer blocks are aligned with respective device die when the one-piece panel of spacer blocks is placed as a single unit on the coupling mechanism material layer on a backside of the semiconductor wafer (Fig. 26C).
(Re Claim 27) wherein the one-piece panel of spacer blocks has a surface of the spacer blocks that is plated1 with a metal layer (¶105 noting any of the methods disclosed for forming a die attach material are applicable, ¶90 discloses metal).
(Re Claim 28) wherein the metal layer includes silver (¶¶105, 90, 88, silver alloy).
(Re Claim 29) wherein the coupling mechanism material layer includes a solder material layer (¶¶105, 90: solder).
(Re Claim 33) wherein the spacer block is wider than a device die (see Figs. 26C, in the vertical direction the spacer blocks are clearly wider than the device die, the claim language does not preclude this treatment, the width may be measured in any direction/orientation, alternatively, in Fig. 26D, the spacer blocks are wider in the lateral/horizontal direction than the dies are in the lateral/horizontal direction).
(Re Claim 34) Truhitte teaches an assembly, comprising:
a semiconductor wafer (¶105, wafer of semiconductor die 94) with an array of devices fabricated on a frontside thereof;
a plurality of blocks of coupling mechanism material (90) disposed on a backside of the semiconductor wafer (Fig. 26C, note the devices having symmetric contacts/terminals on opposite sides being vertical devices thus the devices are on either or both sides); and
a plurality of spacer blocks (88) each having a bottom surface bonded to the backside of the semiconductor wafer by the plurality of blocks of coupling mechanism material, the plurality of spacer blocks being arranged in a grid and connected together as a unit by connecting strips of metal joining adjacent spacer blocks in the grid,
the connecting strips joining adjacent spacer blocks in the grid being severable in a wafer singulation action to separate individual vertical device stacks, each of the individual vertical device stacks including a device die bonded to a spacer block (see Figs. 26A-26H).
Truhitte is silent regarding respective bottom surfaces of the adjacent spacer blocks are separated by a gap. A PHOSITA desiring to make, use and improve upon Truhitte’s assembly would be motivated to look to related art to teach possible alternatives for the panel of spacer blocks to determine if other shapes are advantageous. Related art from Shimoyama teaches the connecting strips can be coplanar with the bottom surface (Fig. 4B, corresponding to Truhitte’s 88), or recesses can be formed from both sides (Fig. 4C). Related art from Sirinorakul (see Figs. 1-4E) also teaches the connecting strips can be coplanar with the bottom surface (Fig. 4C, corresponding to Truhitte’s 88) or recesses can be formed from both sides (Fig. 4E). From the disclosures of Shimoyama and Sirinorakul, the two different structures are art recognized alternatives, both obvious to try, each having predictable results and an expectation of success. Shimoyama (¶¶11-13,30) and Sirinorakul (¶¶3-8, 32-33,40), both recognize that their structures are advantageous when dicing (e.g. blade wear, burrs, chipping, etc.). A PHOSITA would find it obvious to try the alternative wherein the connecting strips are recessed from both sides as taught by both Shimoyama and Sirinorakul for the dicing advantages noted by each.
(Re Claim 35) wherein the connecting strips are spaced apart from the plurality of blocks of coupling mechanism material (Fig. 26F showing the connecting strips spaced apart from 90).
(Re Claim 38) wherein respective top surfaces of the plurality of spacer blocks are arranged in a first plane and respective bottom surfaces of the plurality of spacer blocks are arranged in a second plane, wherein the connecting strips of metal are non- coplanar with the first plane and the second plane (as modified to above to use the alternative connecting strips recessed from both sides of the spacer block panel).
(Re Claim 39) Truhitte teaches an assembly, comprising: a semiconductor wafer with an array of devices fabricated on a frontside thereof; and a spacer block panel having a bottom surface bonded to a backside of the semiconductor wafer by a layer of coupling mechanism material, the spacer block panel including a plurality of spacer blocks arranged in a grid and joined by a plurality of connection strips, wherein each of the plurality of connection strips joins a pair of adjacent spacer blocks in the spacer block panel, the plurality of connection strips being severable in a wafer singulation action to separate individual vertical device stacks, each of the individual vertical device stacks including a device die bonded to a spacer block (claim 39 recites the same limitations in claims 16 and 34+38 and the mapping of elements is the same as above).
Truhitte is silent regarding the plurality of connection strips being recessed from the bottom surface of the spacer block panel and recessed from a top surface of the spacer block panel. A PHOSITA desiring to make, use and improve upon Truhitte’s assembly would be motivated to look to related art to teach possible alternatives for the panel of spacer blocks to determine if other shapes are advantageous. Related art from Shimoyama teaches the connecting strips can be coplanar with the bottom surface (Fig. 4B, corresponding to Truhitte’s 88), or recesses can be formed from both sides (Fig. 4C). Related art from Sirinorakul (see Figs. 1-4E) also teaches the connecting strips can be coplanar with the bottom surface (Fig. 4C, corresponding to Truhitte’s 88) or recesses can be formed from both sides (Fig. 4E). From the disclosures of Shimoyama and Sirinorakul, the two different structures are art recognized alternatives, both obvious to try, each having predictable results and an expectation of success. Shimoyama (¶¶11-13,30) and Sirinorakul (¶¶3-8, 32-33,40), both recognize that their structures are advantageous when dicing (e.g. blade wear, burrs, chipping, etc.). A PHOSITA would find it obvious to try the alternative wherein the connecting strips are recessed from both sides as taught by both Shimoyama and Sirinorakul for the dicing advantages noted by each.
Claims 16-18, 20-22, 25, 27-29, 33-35, and 38 are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al. (US 2008/0003720), of record, in view of Truhitte et al. (US 2016/0027694), of record, Sirinorakul (US 2011/0241189), newly cited, and Shimoyama et al. (US 2008/0032485), of record.
(Re Claim 16) Lu teaches an assembly, comprising (see Figs. 2C-2D and supporting text):
a semiconductor wafer (235) with an array of devices fabricated on a frontside thereof (backside of the wafer has solder 245, frontside has devices);
a coupling mechanism material layer (solder 220/245, after reflow 250) disposed on a backside of the semiconductor wafer; and
a one-piece panel of spacer blocks (210) having a bottom surface disposed on the coupling mechanism material layer, the one-piece panel of spacer blocks including an array of spacer blocks with connecting strips of metal joining adjacent spacer blocks, the spacer blocks in the one-piece panel of spacer blocks being bonded to the backside of the semiconductor wafer (Fig. 2C-2D, 210 is bonded to wafer 235),
the connecting strips (thinned portions of 210) joining adjacent spacer blocks in the one-piece panel of spacer blocks being severable in a wafer singulation action to separate individual vertical device stacks, each of the individual vertical device stacks including a device die bonded to a spacer block (Figs. 2C-2D).
Lu is silent regarding the connecting strips being spaced apart from the coupling mechanism material layer. A PHOSITA desiring to make, use, and improve upon Lu’s invention would be motivated to look to related art to teach possible improvements. Related art from Truhitte discloses rather than forming a continuous solder layer over the entire wafer and/or panel of spacer blocks, the coupling mechanism material can be formed as discrete blocks (see Fig. 26B). Forming the coupling mechanism material layer in this manner has several advantages including using/wasting less coupling material leading to cost savings, and by not forming the coupling material in the dicing lines, avoiding clogging dicing saw blades with the additional material, leading to longer lasting dicing blades. In view of Truhitte, a PHOSITA would find it obvious to form the coupling material 220 in discrete blocks in order to use less material while also increasing the life of dicing blades, and in doing so the connecting strips will be spaced apart from as claimed.
Lu is silent regarding the connecting strips being recessed from the bottom surface. A PHOSITA desiring to make, use and improve upon Lu’s assembly would be motivated to look to related art to teach possible alternatives for the panel of spacer blocks to determine if other shapes are advantageous. Related art from Shimoyama teaches the connecting strips can be coplanar with the bottom surface (Fig. 4B, corresponding to Lu’s 210), or recesses can be formed from both sides (Fig. 4C). Related art from Sirinorakul (see Figs. 1-4E) also teaches the connecting strips can be coplanar with the bottom surface (Fig. 4C, corresponding to Lu’s 210) or recesses can be formed from both sides (Fig. 4E). From the disclosures of Shimoyama and Sirinorakul, the two different structures are art recognized alternatives, both obvious to try, each having predictable results and an expectation of success. Shimoyama (¶¶11-13,30) and Sirinorakul (¶¶3-8, 32-33,40), both recognize that their structures are advantageous when dicing (e.g. blade wear, burrs, chipping, etc.). A PHOSITA would find it obvious to try the alternative wherein the connecting strips are recessed from both sides as taught by both Shimoyama and Sirinorakul for the dicing advantages noted by each.
(Re Claim 17) wherein the spacer blocks are made of a metal or a conductive metal alloy including at least one of copper (Cu), aluminum (Al), copper-molybdenum (CuMo), aluminum silicon carbide composite (AlSiC), or aluminum silicon magnesium alloy (AlSiMg) (¶40: copper).
(Re Claim 18) wherein the device die is about 100 microns thick or less (¶43).
(Re Claim 20) wherein the one-piece panel of spacer blocks has a planar shape conforming to a shape of the semiconductor wafer (Figs. 2C-2D).
(Re Claim 21) wherein each of the individual vertical device stacks is configured to be moved and placed in a circuit package as a single pre-formed unit (Fig. 2C-2D).
(Re Claim 22) wherein a spacer block structurally reinforces the device die (Fig. 2C-2D).
(Re Claim 25) wherein the spacer blocks in the one-piece panel of spacer blocks are aligned with respective device die when the one-piece panel of spacer blocks is placed as a single unit on the coupling mechanism material layer on a backside of the semiconductor wafer (Fig. 2C-2D, ¶46: aligned).
(Re Claim 27) wherein the one-piece panel of spacer blocks has a surface of the spacer blocks that is plated2 with a metal layer (solder 220).
(Re Claim 28) wherein the metal layer includes silver (¶41).
(Re Claim 29) wherein the coupling mechanism material layer includes a solder material layer (solder 220).
(Re Claim 33) wherein the spacer block is wider than a device die (see Figs. 2D-2E, in the vertical direction the spacer blocks are clearly wider than the device die, the claim language does not preclude this treatment, the width may be measured in any direction/orientation).
(Re Claims 34-35) Lu teaches an assembly, comprising:
a semiconductor wafer (235) with an array of devices fabricated on a frontside thereof (backside of the wafer has solder 245, frontside has devices);
a plurality of blocks of coupling mechanism material (220, discussed below) disposed on a backside of the semiconductor wafer; and
a plurality of spacer blocks (210) each having a bottom surface bonded to the backside of the semiconductor wafer by the plurality of blocks of coupling mechanism material, the plurality of spacer blocks being arranged in a grid and connected together as a unit by connecting strips (thinned portions of 210) of metal joining adjacent spacer blocks in the grid,
the connecting strips joining adjacent spacer blocks in the grid being severable in a wafer singulation action to separate individual vertical device stacks, each of the individual vertical device stacks including a device die bonded to a spacer block(see Figs. 2C-2D).
Lu is silent regarding a plurality of blocks of coupling mechanism material. A PHOSITA desiring to make, use, and improve upon Lu’s invention would be motivated to look to related art to teach possible improvements. Related art from Truhitte discloses rather than forming a continuous solder layer over the entire wafer and/or panel of spacer blocks, the coupling mechanism material can be formed as discrete blocks (see Fig. 26B). Forming the coupling mechanism material layer in this manner has several advantages including using/wasting less coupling material leading to cost savings, and by not forming the coupling material in the dicing lines, avoiding clogging dicing saw blades with the additional material, leading to longer lasting dicing blades. In view of Truhitte, a PHOSITA would find it obvious to form the coupling material 220 in discrete blocks in order to use less material while also increasing the life of dicing blades, and in doing so the connecting strips will be spaced apart from as claimed: (Re Claim 35) wherein the connecting strips are spaced apart from the plurality of blocks of coupling mechanism material.
Lu is silent regarding the bottom surfaces of the adjacent spacer blocks are separated by a gap. A PHOSITA desiring to make, use and improve upon Lu’s assembly would be motivated to look to related art to teach possible alternatives for the panel of spacer blocks to determine if other shapes are advantageous. Related art from Shimoyama teaches the connecting strips can be coplanar with the bottom surface (Fig. 4B, corresponding to Lu’s 210), or recesses can be formed from both sides (Fig. 4C). Related art from Sirinorakul (see Figs. 1-4E) also teaches the connecting strips can be coplanar with the bottom surface (Fig. 4C, corresponding to Lu’s 210) or recesses can be formed from both sides (Fig. 4E). From the disclosures of Shimoyama and Sirinorakul, the two different structures are art recognized alternatives, both obvious to try, each having predictable results and an expectation of success. Shimoyama (¶¶11-13,30) and Sirinorakul (¶¶3-8, 32-33,40), both recognize that their structures are advantageous when dicing (e.g. blade wear, burrs, chipping, etc.). A PHOSITA would find it obvious to try the alternative wherein the connecting strips are recessed from both sides as taught by both Shimoyama and Sirinorakul for the dicing advantages noted by each.
(Re Claim 38) wherein respective top surfaces of the plurality of spacer blocks are arranged in a first plane and respective bottom surfaces of the plurality of spacer blocks are arranged in a second plane, wherein the connecting strips of metal are non- coplanar with the first plane and the second plane (as modified to above to use the alternative connecting strips recessed from both sides of the spacer block panel).
Claims 16-18, 20-22, 25, 27-29, 33-35, and 38 are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al. (US 2008/0003720), of record, in view of Truhitte et al. (US 2016/0027694), of record, Sirinorakul (US 2011/0241189), newly cited, and Shimoyama et al. (US 2008/0032485), of record.
(Re Claim 39) Lu teaches an assembly, comprising:
a semiconductor wafer (235) with an array of devices fabricated on a frontside thereof (backside of the wafer has solder 245, frontside has devices); and
a spacer block panel (210) having a bottom surface bonded to a backside of the semiconductor wafer by a layer of coupling mechanism material (220), the spacer block panel including a plurality of spacer blocks arranged in a grid and joined by a plurality of connection strips (thinned portions of 210), wherein each of the plurality of connection strips joins a pair of adjacent spacer blocks in the spacer block panel, the plurality of connection strips being severable in a wafer singulation action to separate individual vertical device stacks, each of the individual vertical device stacks including a device die bonded to a spacer block (see Figs. 2C-2D).
Lu is silent regarding the plurality of connection strips being recessed from the bottom surface of the spacer block panel and recessed from a top surface of the spacer block panel. A PHOSITA desiring to make, use and improve upon Lu’s assembly would be motivated to look to related art to teach possible alternatives for the panel of spacer blocks to determine if other shapes are advantageous. Related art from Shimoyama teaches the connecting strips can be coplanar with the bottom surface (Fig. 4B, corresponding to Lu’s 210), or recesses can be formed from both sides (Fig. 4C). Related art from Sirinorakul (see Figs. 1-4E) also teaches the connecting strips can be coplanar with the bottom surface (Fig. 4C, corresponding to Lu’s 210) or recesses can be formed from both sides (Fig. 4E). From the disclosures of Shimoyama and Sirinorakul, the two different structures are art recognized alternatives, both obvious to try, each having predictable results and an expectation of success. Shimoyama (¶¶11-13,30) and Sirinorakul (¶¶3-8, 32-33,40), both recognize that their structures are advantageous when dicing (e.g. blade wear, burrs, chipping, etc.). A PHOSITA would find it obvious to try the alternative wherein the connecting strips are recessed from both sides as taught by both Shimoyama and Sirinorakul for the dicing advantages noted by each.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over by Lu et al. in view of Truhitte et al. Sirinorakul, and Shimoyama et al. as applied above, and further in view of DiGiacomo et al. (US 5,981,310), all of record.
(Re Claim 19) Lu is silent regarding the thickness of the spacer block. A PHOSITA would be motivated to look to related spacer block structures to teach suitable thicknesses in order to make and use Lu’s device. Related art from DiGiacomo teaches a spacer block may be 1-2.5 mm thick (col 5 lines 57-64) so that it can absorb any vertical (Z-direction) displacement of the chip with minor stress. A PHOSITA would find it obvious to make Lu’s spacer block 1-2.5 mm in thickness for the advantages noted by DiGiacomo. Regarding a coupling mechanism of greater than 200 microns, DiGiacomo also discloses the solder may be 15 mils thick (col 6 lines 1-7). Using a thicker solder also absorbs stress and can accommodate variations in thickness in the bonded device stack.
Claims 23, 36, and 37 are rejected under 35 U.S.C. 103 as being unpatentable over Truhitte et al. Sirinorakul, and Shimoyama et al. as applied above, and further in view of Liu et al. (US 2019/0355634) and Apelsmeier et al. (US 2021/0091054).
Claims 23, 36, and 37 are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al., Truhitte et al., Sirinorakul and Shimoyama et al. as applied above, and further in view of Liu et al. (US 2019/0355634) and Apelsmeier et al. (US 2021/0091054).
(Re Claim 23) wherein the coupling mechanism material layer includes a preform sinter (Truhitte discloses the use of solder preforms ¶¶90,105).
(Re Claim 36) wherein the plurality of blocks of coupling mechanism material includes a sinter material.
(Re Claim 37) wherein the plurality of blocks of coupling mechanism material includes a sinter material (Truhitte discloses the use of solder preforms ¶¶90,105).
Truhitte (and Lu modified in view of Truhitte) teach a solder preform but is silent regarding a sinter preform. A PHOSITA desiring to make, use, and improve upon Truhitte or modified Lu would be motivated to look to related art to teach other suitable materials that may offer advantages. Related art from Liu discloses metal preforms may be either solder or sinter preforms (¶57). Related art from Apelsmeier also similarly teaches preforms may either be solder or sinter preforms (¶¶ 33-36, 71 and 80). A PHOSITA would recognize sintering provides superior joint reliability, higher melting points, better thermal management, and improved resistance to thermal cycling than conventional solder connections. In view of the prior art teaching preforms may either be solder or sinter material, and in light of the known advantages of sintering, a PHOSITA would find it obvious to substitute the solder preforms disclosed by Truhitte for sinter preforms. Regarding claim 36, as discussed above, since a PHOSITA would find it obvious to substitute a sinter material for a solder material, and thus one would obviously then perform a conventional sintering process which involves the application of heat and pressure for sintering.
Response to Arguments
Applicant’s arguments have been considered but are moot in view of the new grounds of rejection necessitated by amendment.
Conclusion
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/ERIK T. K. PETERSON/Primary Examiner, Art Unit 2898
1 Claim 27 is a product-by-process claim, see MPEP §2113(I).
2 Claim 27 is a product-by-process claim, see MPEP §2113(I).