DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to the amendments filed on 08/28/2026.
Applicant’s amendments filed 08/28/2026 have been fully considered and reviewed by the examiner. The examiner notes the amendment of claims 1-11, 14-18, and 21-22.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-18 and 21-22 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 (claim 21) recites “wherein the stress-release passivation pattern” is “free of underfill material and free of molding compound”. However, the original specification does not recite that “the stress-release passivation pattern is free of underfill material and free of molding compound”. Any negative limitation or exclusionary proviso must have basis in the original disclosure. If alternative elements are positively recited in the specification, they may be explicitly excluded in the claims. The mere absence of a positive recitation is not basis for an exclusion. Thus, claim 1 (claim 21) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention.
Claim 11 recites “wherein the stress-release passivation pattern” is “free of the underfill material”. However, the original specification does not recite that “the stress-release passivation pattern is free of underfill material”. Any negative limitation or exclusionary proviso must have basis in the original disclosure. If alternative elements are positively recited in the specification, they may be explicitly excluded in the claims. The mere absence of a positive recitation is not basis for an exclusion. Thus, claim 11 contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over CN 114937642 A to Lai et al. (US 2022/0344174 is presented as a translation, hereinafter Lai) in view of Chen (US 2011/0193198), Lai et al. (US 2013/0320522, hereinafter Lai’222), Furusawa et al. (US 2006/0055005, hereinafter Furusawa), and Yu et al. (US 2021/0066254, hereinafter Yu).
With respect to claim 11, Lai discloses an integrated circuit (IC) structure (Lai, Figs. 7A-7C, 14, ¶0020-¶0063, ¶0073-¶0075) comprising:
a substrate (901) (Lai, Figs. 7A-7B, 14, ¶0060, ¶0073-¶0075);
a plurality of semiconductor chips (e.g., semiconductor dies 201/203) (Lai, Figs. 7A-7B, 14, ¶0030, ¶0073-¶0075) attached to the substrate (901) and electrically connected to the substrate (901); and
an underfill material (205) (Lai, Figs. 7A-7B, 14, ¶0032, ¶0073-¶0075) filled in spaces between the semiconductor chips (201/203) and the substrate (901), wherein the plurality of semiconductor chips (201/203) includes a first semiconductor chip (e.g., 201 or 203), and wherein the first semiconductor chip includes
a semiconductor substrate (e.g., each semiconductor die 201/203 includes a semiconductor substrate having a circuit region) having a circuit region and a chip corner region (e.g., a corner region of the semiconductor device including the semiconductor dies 201/203) (Lai, Figs. 7A-7c, 14, ¶0052, ¶0073-¶0075), the chip corner region being free of integrated circuit (e.g., corner region includes an opening 701 in the encapsulant 301 that is free of integrated circuit) (Lai, Figs. 7A-7C, 14, ¶0052-¶0056, ¶0073-¶0075) and spanning a dimension ranging between 150 mm (W3 and L2) and 300 mm (W2 and L3).
Further, Hsu does not specifically disclose that (1) the first semiconductor chip includes IC devices formed on the semiconductor substrate within the circuit region, and a passivation structure formed over the IC devices, wherein the passivation layer includes a first silicon nitride layer, an un-doped silica glass (USG) layer over the first silicon nitride layer, and a second silicon nitride layer over the USG layer, wherein the passivation structure includes a stress-release passivation pattern formed in the chip corner region, (2) the stress-release passivation pattern extending through the second silicon nitride layer and the USG layer and terminating on the first silicon nitride layer such that the first silicon nitride layer is exposed by the stress-release passivation pattern, and wherein the stress-release passivation pattern is laterally within a periphery of the first semiconductor chip and is free of the underfill material, (3) spanning a dimension ranging between 50 mm and 100 mm.
Regarding (1), Chen teaches forming a semiconductor chip including IC devices (e.g., CMOS transistors 33) (Chen, Figs. 1A, 2, ¶0017) formed on the substrate (30) within the circuit region (32), and a passivation layer (44) (Chen, Figs. 1A, 2, ¶0018) formed over the IC devices (33); and a stress-release pattern (e.g., the corner stress release (CSR) structure 10) (Chen, Figs. 1A, 2, ¶0015) formed in the chip corner region (6).
Further, Lai’222 teaches forming a package (Lai’222, Fig.1a, ¶0001, ¶0012, ¶0031-¶0034) comprising a passivation layer (22/28/29) including a first passivation layer (22) made of SiN, a second passivation layer (28) made of an un-doped silica glass (USG) layer, and a third passivation layer (29) made of silicon nitride, to provide protection of underlying metallization layers of the wafer level chip scale package (WLCSP).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the IC structure of Lai by forming a semiconductor chip including a corner region having a stress release pattern as taught by Chen, and forming a corner region including a trench extending through the passivation layer of Lai’222, wherein the passivation layer includes a plurality of SiN layers and USG layer as taught by Lai’222 to have the IC structure, wherein the first semiconductor chip includes IC devices formed on the semiconductor substrate within the circuit region, and a passivation structure formed over the IC devices, wherein the passivation layer includes a first silicon nitride layer, an un-doped silica glass (USG) layer over the first silicon nitride layer, and a second silicon nitride layer over the USG layer, wherein the passivation structure includes a stress-release passivation pattern formed in the chip corner region, in order to provide a corner stress structure to effectively release the stresses; and to reduce the delamination stresses near the chip corner and edges; and to provide protection of underlying metallization layers of the wafer level chip scale package (Chen, ¶0001, ¶0005, ¶0015, ¶0018; Lai’222, ¶0001, ¶0031, ¶0034).
Regarding (2), Furusawa teaches forming a semiconductor device (Furusawa, Figs. 1-2, 5-8, 10, 13, ¶0011-¶0012, ¶0027-¶0043, ¶0047-¶0060) comprising a chip corner (4) having seal ring structures (123/124) including a crack prevention pattern extending through the second insulating layer (103) and the middle layer (102) and terminating on the first insulating layer (101) such that the first insulating layer (101) is exposed by the crack prevention pattern (123/124), wherein the crack prevention pattern is laterally within a periphery of the semiconductor chip and is free of the underfill material, to provide the corner crack prevention pattern to prevent propagation of cracks.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the IC structure of Lai by forming a semiconductor chip including a corner region having a crack prevention pattern as taught by Furusawa, wherein the crack prevention pattern formed in the passivation layer including a plurality of SiN layers and USG layer as taught by Lai’222 to have the IC structure, wherein the stress-release passivation pattern extending through the second silicon nitride layer and the USG layer and terminating on the first silicon nitride layer such that the first silicon nitride layer is exposed by the stress-release passivation pattern, and wherein the stress-release passivation pattern is laterally within a periphery of the first semiconductor chip and is free of the underfill material, in order to prevent propagation of cracks; and to provide protection of underlying metallization layers of the wafer level chip scale package (Furusawa, ¶0011-¶0012, ¶0038-¶0043, ¶0048, ¶0059; Lai’222, ¶0001, ¶0031, ¶0034).
Regarding (3), Yu teaches forming a semiconductor device (100) (Yu, Fig. 2, ¶0002, ¶0027-¶0032) comprising a corner region including an area formed by the flange portions (100f) ranging from 1 mm to 80 mm. The claimed range overlaps the rnage of prior art.
In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (M.P.E.P. §2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the IC structure of Lai by forming a semiconductor chip including a corner region including an area formed by the flange portions as taught by Yu to have the IC structure, wherein spanning a dimension ranging between 50 mm and 100 mm, in order to provide a semiconductor package with improved integration density (Yu, ¶0002, ¶0027-¶0029).
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over CN 114937642 A to Lai in view of Chen (US 2011/0193198), Lai’222 (US 2013/0320522), Furusawa (US 2006/0055005), and Yu (US 2021/0066254) as applied to claim 11, and further in view of Lin et al. (US 2021/0407963, hereinafter Lin’963).
Regarding claim 12, Lai in view of Chen, Lai’222, Furusawa, and Yu discloses the IC structure of claim 11. Further, Lai does not specifically disclose a lid configured over the semiconductor chips and secured to the substrate, wherein the semiconductor chips are enclosed by the lid and the substrate.
However, Lin’963 teaches forming a lid (e.g., a heat dissipation lid 600) (Lin’963, Figs. 1, 4, ¶0017-¶0060) configured over the semiconductor chips (10/20) (Lin’963, Figs. 1, 4, ¶0019-¶0034) and secured to the substrate (300/500), wherein the semiconductor chips (10/20) are enclosed by the lid (600) and the substrate (300/500) (Lin’963, Figs. 1, 4, ¶0034-¶0052).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the IC structure of Lai/Chen/Lai’222/Furusawa/Yu by forming a lid structure as taught by Lin’963 to have the IC structure, wherein a lid configured over the semiconductor chips and secured to the substrate, wherein the semiconductor chips are enclosed by the lid and the substrate, in order to effectively dissipate heat from the semiconductor package (Lin’963, ¶0001, ¶0017, ¶0057).
Regarding claim 13, Lai in view of Chen, Lai’222, Furusawa, and Yu discloses the IC structure of claim 11. Further, Lai discloses the IC structure, wherein the substrate (901) (Lai, Figs. 7A-7B, 14, ¶0049, ¶0060, ¶0073-¶0075) includes a first surface and a second surface opposite from the first surface, wherein the semiconductor chips (201/203) are attached to the first surface (e.g., a top surface) of the substrate (901), but does not specifically disclose that the IC structure further includes large- scale-integrated passive devices (LS-IPDs) formed on the second surface of the substrate.
However, Lin’963 teaches forming a package comprising the semiconductor chips (10/20) (Lin’963, Figs. 1, 4, ¶0019-¶0034) attached to the first surface of the substrate (300/500), wherein the integrated passive devices (e.g., IPDs 550) Lin’963, Figs. 1, 4, ¶0052-¶0053) are formed on the second surface of the substrate (300/500), and further forming a heat dissipation lid (600) on the first surface of the substrate (300/500), to effectively remove heat from the package.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the IC structure of Lai/Chen/Lai’222/Furusawa/Yu by forming integrated passive devices on back side of the substrate as taught by Lin’963 to have the IC structure, wherein the IC structure further includes large- scale-integrated passive devices (LS-IPDs) formed on the second surface of the substrate, in order to provide a semiconductor package effectively dissipating heat from the semiconductor dies (Lin’963, ¶0001, ¶0017, ¶0052, ¶0057, ¶0074).
Allowable Subject Matter
The independent claim 1 would be allowable if rewritten to address the rejection of claim 1 under 35 USC 112(a).
The following is a statement of reasons for the indication of allowable subject matter:
The search of the prior art does not disclose or reasonably suggest forming an integrated circuit (IC) structure comprising a passivation layer structure including a first silicon nitride layer, an un-doped silica glass (USG) layer, and a second silicon nitride layer, and a polyimide layer formed over the passivation layer structure, wherein the chip corner region includes a stress-release passivation pattern and a stress-release polyimide pattern including an opening having a tilted edge and being different from the stress-release passivation pattern in location and in shape, wherein the stress-release passivation pattern extends through the second silicon nitride layer and the USG layer and exposes the first silicon nitride layer, in combinations with other claim limitations as required by claim 1.
The dependent claims 2-10 would be allowable by virtue of the dependence upon the independent claim 1.
Claim 14 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The search of the prior art does not disclose or reasonably suggest forming an integrated circuit (IC) structure comprising a passivation structure including a first silicon nitride layer, an un-doped silica glass (USG) layer, and a second silicon nitride layer, and a polyimide layer formed over the passivation structure, wherein the chip corner region includes a stress-release passivation pattern and a stress-release polyimide pattern, wherein the stress-release polyimide pattern being different from the stress-release passivation pattern in location and in shape, and wherein the stress-release passivation pattern extends through the second silicon nitride layer and the USG layer and exposes the first silicon nitride layer, in combinations with other claim limitations as required by claim 11 and 14.
The dependent claims 15-18 would be allowable by virtue of the dependence upon the claims 11 and 14.
The independent claim 21 would be allowable if rewritten to address the rejection of claim 21 under 35 USC 112(a).
The following is a statement of reasons for the indication of allowable subject matter:
The search of the prior art does not disclose or reasonably suggest forming an integrated circuit (IC) structure comprising a passivation structure including a first silicon nitride layer, an un-doped silica glass (USG) layer, and a second silicon nitride layer, and a polyimide layer formed over the passivation structure, wherein the chip corner region includes a stress-release passivation pattern and a stress-release polyimide pattern including an opening having a tilted edge and being different from the stress-release passivation pattern in location and in shape, wherein the stress-release passivation pattern extends through the second silicon nitride layer and the USG layer and exposes the first silicon nitride layer, in combinations with other claim limitations as required by claim 21.
The dependent claim 22 would be allowable by virtue of the dependence upon the independent claim 21.
Response to Arguments
Applicant's arguments filed 08/28/2026 have been fully considered but they are not persuasive.
In response to Applicant's argument that “the stress-release passivation pattern to be "free of underfill material and free of molding compound"”, the examiner submits that the above limitations are interpreted as negative limitations. Any negative limitation or exclusionary proviso must have basis in the original disclosure. If alternative elements are positively recited in the specification, they may be explicitly excluded in the claims. The mere absence of a positive recitation is not basis for an exclusion (See MPEP 2173.05(i)). The original specification does not define “underfill material and molding compound” as alternative elements that can be present or absent in the stress-release passivation pattern. The specification is silent regarding the presence or absence of “underfill material and molding compound” in the stress-release passivation pattern. Thus, claims 1, 11, and 21 contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATALIA GONDARENKO whose telephone number is (571)272-2284. The examiner can normally be reached 9:30 AM-7:30 PM.
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891
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