DETAILED ACTION
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e). Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Amendment
Acknowledgment is made of applicant's Amendment, filed 12-10-2025. The changes and remarks disclosed therein have been considered.
Claim(s) 1, 3, 5, 6, 9, 11, 13, and 14 has/have been amended, claim(s) 4 and 12 has/have been cancelled, claim(s) 1-3, 5-11, and 13-15 remain(s) pending in the application.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5, 9-11, and13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang, US 20220398439 A1.
As to claim 1, Zhang discloses discloses a calculating method, adapted to
a semiconductor device (see Zhang Fig 1 and Fig 29) comprising a memory cell array of a NOR type or NAND type (see Zhang Fig 15 and Para [0116]), wherein
[in] the calculating method comprises:
calculating a sum of currents flowing in a column direction of a plurality of bit lines (see Zhang Para [0117]) when each row is read [is calculated] in a reading operation of a plurality of rows of the memory cell array (see Zhang Para [0017]; Word line by word line is each row of a plurality of rows.); and
performing an A/D conversion on the sum of the currents in the column direction or a sum of currents in a matrix direction (see Zhang Fig 28 Ref 2850 and Para [0145]) to generate compressed digital data (see Zhang Fig 29 Ref 2911) having a number of bits that is smaller than a number of memory cells being read in the memory cell array (see Zhang Para [0145]; A single analog/digital output is less than multi-bit input values applied to sets of bit lines.).
As to claim 2, Zhang discloses the calculating method according to claim 1, further
calculating
the sum of the currents in the column direction and a sum of currents in a row direction of the plurality of bit lines (see Zhang Para [0118]).
As to claim 3, Zhang discloses the calculating method according to claim 2, wherein the calculating method calculates
a sum of currents in a matrix direction (see Zhang Fig 28 matrix associated with Ref VWL) corresponding to data stored in memory cells of a plurality of rows cross a plurality of columns (see Zhang Fig 28 Ref I.sub.SL).
As to claim 5, Zhang discloses the calculating method according to claim 1, further comprising
writing the compressed digital data into memory cells of the memory cell array (see Zhang Fig 29 Ref 2921 and Para [0145]).
As to claim 9, Zhang discloses a semiconductor device (see Zhang Fig 1), comprising:
a memory cell array of a NOR type or NAND type (see Zhang Fig 15 and Para [0116]), comprising a plurality of row lines, a plurality of bit lines, and a plurality of memory cells (see Zhang Fig 15); a reading part (see Zhang Fig 6A Ref 610) for reading out the memory cell array; a writing part (see Zhang Fig 6A Ref 620) for writing the memory cell array; and a calculating part (see Zhang Fig 2850) for calculating a sum of currents flowing in a column direction of the plurality of bit lines (see Zhang Para [0117]) when each row is read when the reading part performs reading of a plurality of rows (see Zhang Para [0017]; Word line by word line is each row of a plurality of rows.); wherein
the calculating part comprises an performing an A/D conversion part performing A/D conversion on the sum of the currents in the column direction or a sum of currents in a matrix direction (see Zhang Fig 28 Ref 2850 and Para [0145]) to generate compressed digital data (see Zhang Fig 29 Ref 2911) having a number of bits that is smaller than a number of memory cells being read in the memory cell array (see Zhang Para [0145]; A single analog/digital output is less than multi-bit input values applied to sets of bit lines.).
As to claim 10, Zhang discloses the semiconductor device of claim 9.
Claim 10 recites substantially the same limitations as claim 2.
All the limitations of claim 10 have already been disclosed by Zhang in claim 2 above.
As to claim 11, Zhang discloses the semiconductor device of claim 10.
Claim 11 recites substantially the same limitations as claim 3.
All the limitations of claim 11 have already been disclosed by Zhang in claim 3 above.
As to claim 13, Zhang discloses the semiconductor device of claim 12.
Claim 13 recites substantially the same limitations as claim 5.
All the limitations of claim 13 have already been disclosed by Zhang in claim 5 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang, US 20220398439 A1.
As to claim 6, Zhang discloses the calculating method according to claim 5, wherein
the memory cell array comprises a first storage plane (see Zhang Fig 28 plane associated with Ref VWL) and a second storage plane (see Zhang Fig 28 plane under Ref VWL), in reading out the first storage plane, a sum of currents flowing in the bit line in a matrix direction is calculated (see Zhang Fig 28 Ref 2850 and Para [0145])
Zhang does not appear to explicitly disclose
the plurality of bits of data is written into the second storage plane.
However, it would have been obvious to one skilled in the art at the time of the effective filing of the invention that a programming operation for weights, as disclosed by Zhang in figure 29, reference character 2905, may be implemented in a memory plane, as disclosed by Zhang in figure 28. Storing weights in sequential planes centralized data access (see Zhang [0139]).
As to claim 14, Zhang discloses the semiconductor device of claim 13.
Claim 14 recites substantially the same limitations as claim 6.
All the limitations of claim 14 have already been disclosed by Zhang in claim 6 above.
Claim(s) 7, 8, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang, US 20220398439 A1, in view of Ren, US 20240127888 A1.
As to claim 7, Zhang discloses the calculating method according to claim 1, wherein the calculating method calculates
a sum of first currents flowing in a first group of bit lines in the column direction, and a sum of second currents flowing in a second group of bit lines in the column direction (see Zhang Para [0117]).
Zhang does not appear to explicitly disclose as well as a difference between the sum of the first currents and the sum of the second currents.
Ren discloses as well as a difference between the sum of the first currents and the sum of the second currents (see Ren Fig 9).
It would have been obvious to one skilled in the art at the time of the effective filing of the invention that method, as disclosed by Zhang, may implement subtractive operations, as disclosed by Ren. The inventions are well known variants of in-memory computing operations and the combination of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is Ren’s attempt to lower computational complexity (see Ren Para [0004]).
As to claim 8, Zhang and Ren disclose the calculating method according to claim 7, wherein the sum of the first currents represents a positive coefficient and the sum of the second currents represents a negative coefficient (see Zhang Para [0080]).
As to claim 15, Zhang discloses the semiconductor device of claim 10.
Claim 15 recites substantially the same limitations as claim 7.
All the limitations of claim 15 have already been disclosed by Zhang and Ren in claim 7 above.
Response to Arguments
Applicant's arguments filed 12/10/2025 have been fully considered but they are not persuasive.
The amended language does not appear to overcome the broadest reasonable interpretation of the previously presented prior art.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEROME LARRY LEBOEUF whose telephone number is (571)272-7612. The examiner can normally be reached M-Th: 8:00AM - 6:00PM EST.
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/JEROME LEBOEUF/Primary Examiner, Art Unit 2824 - 01/27/2025