DETAILED ACTION
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e). Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Amendment
Acknowledgment is made of applicant's Amendment, filed 04-28-2026. The changes and remarks disclosed therein have been considered.
Claim(s) 1, 8 and 9 has/have been amended. Claim(s) 7 and 15 has/have been cancelled, and claim(s) 1-3, 5, 6, 8-11, 13 and 14 remain(s) pending in the application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5, 6, 8-11, 13 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang, US 20220398439 A1, in view of Castro, US 20240304254 A1.
As to claim 1, Zhang discloses a calculating method, adapted to
a semiconductor device (see Zhang Fig 1 and Fig 29) comprising a memory cell array of a NOR type or NAND type (see Zhang Fig 15 and Para [0116]), wherein
the calculating method comprises:
calculating a sum of currents flowing in a column direction of a plurality of bit lines (see Zhang Para [0117]) when each row is read in a reading operation of a plurality of rows of the memory cell array (see Zhang Para [0017]; Word line by word line is each row of a plurality of rows.); and
performing an A/D conversion on the sum of the currents in the column direction or a sum of currents in a matrix direction (see Zhang Fig 28 Ref 2850 and Para [0145]) to generate compressed digital data (see Zhang Fig 29 Ref 2911) having a number of bits that is smaller than a number of memory cells being read in the memory cell array (see Zhang Para [0145]; A single analog/digital output is less than multi-bit input values applied to sets of bit lines.).
Zhang does not appear to explicitly disclose
the calculating the sum of currents flowing in the column direction of the plurality of bit lines comprises:
calculating, by a positive adding part, a sum of first currents flowing in a first group of bit lines in the column direction;
calculating, by a negative adding part, a sum of second currents flowing in a second group of bit lines in the column direction; and
calculating, by a difference calculation part coupled to the positive adding part and the negative adding part, a difference between the sum of the first currents and the sum of the second currents.
Castro discloses
the calculating the sum of currents flowing in the column direction of the plurality of bit lines (see Castro Paras [0051] and [0532], and Figs 23 and 24) comprises:
calculating, by a positive adding part, a sum of first currents flowing in a first group of bit lines in the column direction (see Castro Fig 23 Ref 2351 and Fig 24 Ref 2408);
calculating, by a negative adding part, a sum of second currents flowing in a second group of bit lines in the column direction (see Castro Fig 23 Ref 2351 and Fig 24 Ref 2409); and
calculating, by a difference calculation part coupled to the positive adding part and the negative adding part, a difference between the sum of the first currents and the sum of the second currents (see Castro Fig 23 Ref 2363 and Para [0533]).
It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a method, as disclosed by Zhang, may implement subtractive operations as disclosed by Castro. The inventions are well known variants of in-memory computing operations and the combination of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is Castro’s attempt to increase matrix operation efficiency (see Castro Para [0039]).
As to claim 2, Zhang and Castro disclose the calculating method according to claim 1, further
calculating
the sum of the currents in the column direction and a sum of currents in a row direction of the plurality of bit lines (see Zhang Para [0118]).
As to claim 3, Zhang and Castro disclose the calculating method according to claim 2, wherein the calculating method calculates
a sum of currents in a matrix direction (see Zhang Fig 28 matrix associated with Ref VWL) corresponding to data stored in memory cells of a plurality of rows cross a plurality of columns (see Zhang Fig 28 Ref I.sub.SL).
As to claim 5, Zhang and Castro disclose the calculating method according to claim 1, further comprising
writing the compressed digital data into memory cells of the memory cell array (see Zhang Fig 29 Ref 2921 and Para [0145]).
As to claim 6, Zhang and Castro disclose the calculating method according to claim 5, wherein
the memory cell array comprises a first storage plane (see Zhang Fig 28 plane associated with Ref VWL) and a second storage plane (see Zhang Fig 28 plane under Ref VWL), in reading out the first storage plane, a sum of currents flowing in the bit line in a matrix direction is calculated (see Zhang Fig 28 Ref 2850 and Para [0145])
Zhang and Castro does not appear to explicitly disclose
the plurality of bits of data is written into the second storage plane.
However, it would have been obvious to one skilled in the art at the time of the effective filing of the invention that a programming operation for weights, as disclosed by Zhang in figure 29, reference character 2905, may be implemented in a memory plane, as disclosed by Zhang in figure 28. Storing weights in sequential planes centralized data access (see Zhang [0139]).
As to claim 8, Zhang and Castro disclose the calculating method according to claim 1, wherein the sum of the first currents represents a positive coefficient and the sum of the second currents represents a negative coefficient (see Castro Para [0080]).
As to claim 9, Zhang and Castro disclose a semiconductor device (see Zhang Fig 1), comprising:
a memory cell array of a NOR type or NAND type (see Zhang Fig 15 and Para [0116]), comprising a plurality of row lines, a plurality of bit lines, and a plurality of memory cells (see Zhang Fig 15); a reading part (see Zhang Fig 6A Ref 610) for reading out the memory cell array; a writing part (see Zhang Fig 6A Ref 620) for writing the memory cell array; and a calculating part (see Zhang Fig 2850) for calculating a sum of currents flowing in a column direction of the plurality of bit lines (see Zhang Para [0117]) when each row is read when the reading part performs reading of a plurality of rows (see Zhang Para [0017]; Word line by word line is each row of a plurality of rows.); wherein
the calculating part comprises an performing an A/D conversion part performing A/D conversion on the sum of the currents in the column direction or a sum of currents in a matrix direction (see Zhang Fig 28 Ref 2850 and Para [0145]) to generate compressed digital data (see Zhang Fig 29 Ref 2911) having a number of bits that is smaller than a number of memory cells being read in the memory cell array (see Zhang Para [0145]; A single analog/digital output is less than multi-bit input values applied to sets of bit lines.), wherein
the calculating part comprises: a positive adding part (see Castro Fig 23 Ref 2351 and Fig 24 Ref 2408), configured to calculate a sum of first currents flowing in a first group of bit lines in the column direction (see Castro Paras [0051] and [0532]); a negative adding part (see Castro Fig 23 Ref 2351 and Fig 24 Ref 2409), configured to calculate a sum of second currents flowing in a second group of bit lines in the column direction (see Castro Paras [0051] and [0532]); and a difference calculation part, coupled to the positive adding part and the negative adding part, configured to calculate a difference between the sum of the first currents and the sum of the second currents (see Castro Fig 23 Ref 2363 and Para [0533]).
As to claim 10, Zhang and Castro disclose the semiconductor device of claim 9.
Claim 10 recites substantially the same limitations as claim 2.
All the limitations of claim 10 have already been disclosed by Zhang and Castro in claim 2 above.
As to claim 11, Zhang and Castro disclose the semiconductor device of claim 10.
Claim 11 recites substantially the same limitations as claim 3.
All the limitations of claim 11 have already been disclosed by Zhang and Castro in claim 3 above.
As to claim 13, Zhang and Castro disclose the semiconductor device of claim 12.
Claim 13 recites substantially the same limitations as claim 5.
All the limitations of claim 13 have already been disclosed by Zhang and Castro in claim 5 above.
As to claim 14, Zhang and Castro disclose the semiconductor device of claim 13.
Claim 14 recites substantially the same limitations as claim 6.
All the limitations of claim 14 have already been disclosed by Zhang in claim 6 above.
Response to Arguments
Applicant's arguments filed 04/28/2026 have been fully considered but they are not persuasive.
New prior art has been provided which reads on the amended language.
Conclusion
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/JEROME LEBOEUF/Primary Examiner, Art Unit 2824 - 05/15/2026
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