DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Invention I, Species I in the reply filed on 8/4/2026 is acknowledged. The traversal is on the ground(s) that there is no unreasonable burden to search all inventions. This is not found persuasive because prior art that reads on one invention/species does not necessarily read on the others. Thus, as serious burden exists insofar as the need for different fields of search (different classes, search strategies, etc).
The requirement is still deemed proper and is therefore made FINAL.
Claims 7 and 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention and species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 8/4/2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over MAO et al. (US PG Pub 2026/0136531, hereinafter Mao).
Regarding claim 11, figure 8 of Mao discloses a method for forming a self-aligned interlayer dielectric (ILD) in a vertical channel structure, comprising:
selectively depositing an ILD (74) on a dielectric region (821) versus an exposed surface of a channel pillar (2) disposed within the dielectric region, wherein:
the channel pillar comprises silicon (Si, ¶ 42).
Mao does not explicitly disclose the dielectric region comprises silicon oxide (SiO2).
However, it would have been obvious to use silicon oxide since it is a well-known material in the art for dielectric layers.
Regarding claim 11, Mao does not explicitly disclose the channel pillar has a diameter of between 5 nm and 10 nm, and is spaced from an adjacent channel pillar by a spacing of between 18 nm and 25 nm.
However, it would have been obvious to form the channel pillar to have a diameter and be spaced at a distance within the claimed ranges, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Regarding claim 13, Mao does not explicitly disclose ILD comprises aluminum oxide (Al203), hafnium oxide (HfO2), titanium oxide (TiO2), zinc oxide (ZnO), or indium oxide (In203).
However, it would have been obvious to use one of the claimed materials since they are well-known material in the art for interlayer dielectric layers.
Regarding claim 14, Mao does not explicitly disclose
14. (Original) The method of claim 11, wherein the ILD has a thickness of between about 20 nm and about 30 nm.
However, it would have been obvious to form the ILD to have a thickness within the claimed ranges, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Allowable Subject Matter
Claims 1-5 and 7-10 are allowed.
Regarding claim 1, the closest prior art of record, MAO et al. (US PG Pub 2026/0136531), either singularly or in combination, does not disclose or suggest the combination of limitations including “a method for forming a storage node contact in a dynamic random access memory (DRAM) device, comprising:
performing an array wafer polish process to polish an array wafer from a top side of the array wafer, the array wafer comprising a bitline layer, a channel pillar over the bitline layer and surrounded by a gate oxide layer, a word line layer on both sides of the channel pillar, and a bottom source/drain (S/D) junction that electrically connects the channel pillar to the bitline layer, disposed within a shallow trench isolation (STI);
performing a junction implant and activation process to dope a top portion of the channel pillar and form a top S/D junction;
performing a selective dielectric deposition process to selectively form an interlayer dielectric (ILD) on the STI versus the top S/D junction;
performing a silicidation process to form an interface layer on an exposed surface of the top S/D junction;
performing a contact metal deposition process to deposit a contact metal layer on the ILD and the interface layer;
performing a storage node landing pad (SNLP) lithography and etch process to form a storage node landing pad in the contact metal layer; and
performing an insulator fill process to fill a gap between the storage node landing pad and an adjacent storage node landing pad with insulator fill material”.
Claim 15 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/YU-HSI D SUN/ Primary Examiner, Art Unit 2817
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