DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election, without traverse, of species IV: claims 18-20, in the “Response to Election / Restrict. ion Filed - 13 is acknowledged. Applicant cancellation of claim 1-17, amendment of claim 18 and submission of new claims 21-37 is noticed. Applicant’s statement, in Remarks - 08/11/2026 - Applicant Arguments/Remarks Made in an Amendment, that claim 18 is amended is not found correct in “ Claims - 08/11/2026”. A clarification is required on the statement.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (100; Fig 1A; [0022] or C 18, L 18-37)= (element 100; Figure No. 1; Paragraph No. [0022]) or Column No 18, Line Nos. 18-17. For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” or “Column No, Line Nos" shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The primary reference citation, in this case, Hung may not be preceded by the inventor tag, wherein the other reference citation. For example Chou, Nishida will carry inventor tag.These conventions are used throughout this document. These conventions are used throughout this document.
Claims 18-36 are rejected under 35 U.S.C. 103 as being unpatentable over Hung; Feng-Chi. et al. (US 0210210532 A1) hereinafter referenced as Hung; in view of CHOU; YI-HSIEN (US 20210217864 A1); hereinafter referenced as Chou ; in further view of NISHIDA; Keiji et al (US 20250133847 A1); hereinafter referenced as Nishida.
Regarding Claim 18. Hung teaches a method of manufacturing (block diagram 1800, in Fig 18) an image sensor, comprising (See the entire document Figs 18, 9-17 along with other figures and relevant disclosures, specifically; as cited below):
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Hung Figure 18 Chou Figure 2
forming a pixel region (110a/110b of 900; Fig 9 [0051-0053] in steps 1802; Fig 18; [0067]).
But, Hung does not expressly disclose forming a sacrificial region and related process step in:
“forming a sacrificial region between a first side of the substrate and the pixel region;
removing a portion of the substrate between the first side and the sacrificial region to form a first hole having a first width;
removing the sacrificial region to form a second hole in communication with the first hole and having a second width greater than the first width; and
forming a gate electrode having a first gate portion on the first side, a second gate portion in the first hole, and a third gate portion in the second hole”.
However, in the analogous art, Chou teaches a method of manufacturing a semiconductor device ([0001), wherein ([0020, fig 2; [0036]) creating of the first trenches and the second trench includes steps of forming a sacrificial layer comprising a plurality of first openings and at least one second opening to expose portions of an upper surface of the substrate; etching the substrate through the first openings and the second opening to form the first trenches and the second trench; and removing the sacrificial layer after the deposition of the electrode layer. (Fig 2; [0036]) illustrates a sacrificial layer 200 is formed on the semiconductor substrate 110 according to a step S304 in FIG. 2.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention, to incorporate the process step S304 of Chou into Hung‘s method so that the combination of (Hung and Chou) have process steps having, at least, “forming a sacrificial region (Chou) between a first side of the substrate (107 of 104) and the pixel region (110a/110b), since this inclusion, at least, protects against contamination and functions as a buffer layer for mitigating stress at the interface between substrate and overlaying layer (Chou [0036]).
The combination of (Hung and Chou) subsequently discloses:
removing a portion of the substrate (by a first etch [0055] with certain depth of trenches, within bulk region 107 of 104. as 1004 of 1000, that does not penetrate doped pixel region 110a/110b of 104; Fig 10; [0055] in a first sub-step 1804; Fig 18; [0068]) between the first side and the sacrificial region to form a first hole having a first width;
removing the sacrificial region (by implied remaining etch [0055] within bulk region 110a/110b of 104. as 1004 of 1000, that make hole into doped pixel region 110a/110b of 104; Fig 10; [0055] in a second sub-step 1804; Fig 18; [0068]) to form a second hole in communication with the first hole (see below “ having a second width greater than the first width”); and
forming a gate electrode (1102 of 1100; Fig 11 [0057] in part of steps 1806; Fig 18; [0069]) having a first gate portion on the first side (above 104f; depicted in Fig 12; [0058]), a second gate portion (between 102f and 110a in 107) in the first hole, and a third gate portion (within 110a) in the second hole”.
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Hung Figure 12
As indicated above, the combination of (Hung and Chou) does not expressly disclose: having a second width greater than the first width’ (of the first hole)
However, in the another analogous art, Nishida teaches an imaging apparatus ([0001), wherein (Fig 8; [0036]) having a second width (of 103a) greater than the first width’ (of the first hole 103) as disclosed in [0088] as “when the semiconductor substrate 101 is viewed from above, the enlarged diameter portions 103a and 103b on the bottom surface side of the vertical gate electrodes 103-1 and 103-2 protrude from the transfer gate electrode 103-3 on the semiconductor substrate 101”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention, to incorporate the teaching of Nishida into (Hung and Chou) method so that the combination of (Hung, Chou and Nishida) have process steps having, at least, having a second width (of 103a) greater than the first width’ (of the first hole 103), since this configuration, at least, by adopting a structure in which the bottom surface side of each of the vertical gate electrodes 103-1 and 103-2 is larger in diameter than the upper side, it is possible to increase the area of the surface (bottom surface) of the transfer gate 103 facing the photoelectric conversion unit 102 while securing the distance from the transfer gate electrode 103-3 to the floating diffusion region 105 and/or the ground contact 106, and thus it is possible to suppress deterioration in transfer efficiency while suppressing deterioration in image quality due to formation of the strong electric field (Nishida [0090)
Regarding Claim 19. The combination of (Hung, Chou and Nishida) the method according to claim 18, further teaches, (the method) further comprising forming a passivation layer (Chou [0036] an overlying layer 220) over the sacrificial region (Chou 200) .
Regarding Claim 20. The combination of (Hung, Chou and Nishida) the method according to claim 18, further teaches, (the method) further comprising forming a gate oxide (113 of 1100; Fig 11 [0056] in part of steps 1806; Fig 18; [0069]) along sidewalls of the first hole and the second hole.
Regarding Claim 21. The combination of (Hung, Chou and Nishida) the method according to claim 20, further teaches, wherein the sacrificial region (Chou 200; [0036]) is partially disposed in the pixel region (110a), wherein the first hole (that accommodate gate portion above 104f; depicted in Fig 12; [0058]) exposes the sacrificial region ( Chou 200) and is elongated in a first direction substantially perpendicular to the first side of the substrate, wherein the second hole (that accommodate gate portion between above 104f and 110a; depicted in Fig 12; [0058] in view of Nishida 103-2) is elongated in a second direction substantially parallel to the first side of the substrate, and wherein the second gate portion is disposed between and narrower than the first gate portion and the third gate portion (103-a).
Regarding Claim 22. The combination of (Hung, Chou and Nishida) the method according to claim 18, further teaches, wherein forming the sacrificial region (Chou 200) comprises doping a region of the substrate that is proximate the pixel region and that corresponds to the sacrificial region (Chou [0020, fig 2; [0036]) creating of the first trenches and the second trench includes steps of forming a sacrificial layer comprising a plurality of first openings and at least one second opening to expose portions of an upper surface of the substrate; etching the substrate through the first openings and the second opening to form the first trenches and the second trench; and removing the sacrificial layer after the deposition of the electrode layer. (Fig 2; [0036]) illustrates a sacrificial layer 200 is formed on the semiconductor substrate 110 according to a step S304 in FIG. 2).
Regarding Claim 23. The combination of (Hung, Chou and Nishida) the method according to claim 22, further teaches, (the method) further comprising:
forming a doped semiconductor layer (Chou [0036]) covering the sacrificial region on the first side of the substrate, wherein the doped semiconductor layer has an opposite doping type as the sacrificial region (Chou [0036] overlying layer 220 sequentially formed on the semiconductor substrate 110; 220 may include any dielectric, such as silicon dioxide, silicon nitride, another suitable dielectric material or a combination thereof.).
Regarding Claim 24. The combination of (Hung, Chou and Nishida) the method according to claim 18, further teaches, (the method) further comprising:
forming a floating node (120 of 1200; [0059]) proximate the first side of the substrate before forming the sacrificial region, wherein in a plan view after forming the gate electrode, the third gate portion underlies the floating node (120).
Regarding Claim 25. Hung teaches a method of manufacturing (block diagram 1800, in Fig 18) an image sensor, comprising (See the entire document Figs 18, 9-17 along with other figures and relevant disclosures, specifically; as cited below):
forming a pixel region (110a/110b of 900; Fig 9 [0051-0053] in steps 1802; Fig 18; [0067]) in a semiconductor substrate (104; first disclosed as semiconductor substrate [0023] );
performing a first etch (a first etch [0055] with certain depth of trenches, within bulk region 107 of 104. as 1004 of 1000, that does not penetrate doped pixel region 110a/110b of 104; Fig 10; [0055] in a first sub-step 1804; Fig 18; [0068]) into a first side (104f; [0055]) of the semiconductor substrate (104) to form a hole (1004 within 107) extending into the semiconductor substrate (bulk region 107 of 104);
performing a second etch (implied remaining etch [0055] within bulk region 110a/110b of 104. as 1004 of 1000, that make hole into doped pixel region 110a/110b of 104; Fig 10; [0055] in a second sub-step 1804; Fig 18; [0068]) into the semiconductor substrate, through the hole, (see below to undercut a portion of the semiconductor substrate) that separates the pixel region from the first side of the semiconductor substrate and to expose the pixel region (110a/110b);
forming a dielectric layer lining (113 of 1100; Fig 11 [0056] in part of steps 1806; Fig 18; [0069]) the hole; and
forming a gate electrode (1102 of 1100; Fig 11 [0057] in part of steps 1806; Fig 18; [0069]) filling a remainder of the hole over the dielectric layer (113).
As indicated above, the combination of (Hung and Chou) does not expressly disclose: for “to undercut a portion of the semiconductor substrate”)
However, in the another analogous art, Nishida teaches an imaging apparatus ([0001), wherein (Fig 8; [0036]) having a second width (of 103a) greater than the first width’ (of the first hole 103) as disclosed in [0088] as “when the semiconductor substrate 101 is viewed from above, the enlarged diameter portions 103a and 103b on the bottom surface side of the vertical gate electrodes 103-1 and 103-2 protrude from the transfer gate electrode 103-3 on the semiconductor substrate 101”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention, to incorporate the teaching of Nishida into Hung’s method so that the combination of (Hung and Nishida) have process steps having, at least, having for “to undercut a portion of the semiconductor substrate for the region that accommodates 103a), since this configuration, at least, by adopting a structure in which the bottom surface side of each of the vertical gate electrodes 103-1 and 103-2 is larger in diameter than the upper side, it is possible to increase the area of the surface (bottom surface) of the transfer gate 103 facing the photoelectric conversion unit 102 while securing the distance from the transfer gate electrode 103-3 to the floating diffusion region 105 and/or the ground contact 106, and thus it is possible to suppress deterioration in transfer efficiency while suppressing deterioration in image quality due to formation of the strong electric field (Nishida [0090)
Regarding Claims 26-28. The combination of (Hung and Nishida) as applied to the method according to claim 25, does not expressly disclose, (the method) further comprising: doping the semiconductor substrate to form a sacrificial region” in
For claim 26, doping the semiconductor substrate to form a sacrificial region” adjoining the pixel region (110a) in the step of
“doping the semiconductor substrate to form a sacrificial region adjoining the pixel region (110a) and spaced from the first side (104f) of the semiconductor substrate (104), wherein the second etch removes the sacrificial region to undercut the portion (Nishida the region that accommodates 103a) of the semiconductor substrate (104) and to expose the pixel region (110a)”.
For claim 27, doping the semiconductor substrate to form a sacrificial region adjoining the pixel region and at the first side of the semiconductor substrate; and
epitaxially depositing semiconductor material on the first side (104f) of the semiconductor substrate to increase a thickness of the semiconductor substrate (104) and to cover the sacrificial region on the first side (104f) of the semiconductor substrate (104), wherein the second etch removes the sacrificial region to undercut the portion (Nishida) of the semiconductor substrate and to expose the pixel region (110a).
For claim 28, “doping the semiconductor substrate before the first etch to form a floating node (120) at the first side of the semiconductor substrate (104), wherein the gate electrode (1102) is formed bordering the floating node”.
However, in the analogous art, Chou teaches a method of manufacturing a semiconductor device ([0001), wherein ([0029-0035], fig 2; [0036]) creating of the first trenches and the second trench includes steps of forming a sacrificial layer by doping the semiconductor substrate to form a sacrificial region adjoining the pixel region and spaced from the first side of the semiconductor substrate, wherein the second etch removes the sacrificial region is formed on the semiconductor substrate 110 according to a step S304 in FIG. 2
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention, to incorporate the process step S304 of Chou into (Hung and Nishida) method so that the combination of (Hung, Nishida and Chou) have process steps having, at least, “doping (Chou) the semiconductor substrate (104) to form a sacrificial region (Chou 200) with other steps as claimed, since this inclusion, at least, protects against contamination and functions as a buffer layer for mitigating stress at the interface between substrate and overlaying layer (Chou [0036]).
Regarding Claims 30. The combination of (Hung and Nishida) as applied to the method according to claim 25, further teaches, wherein the hole has an inverted T-shaped profile ((1102 of 1100; Fig 11 [0057] in view of Nishida Fig 8; [0036]) at completion of the second etch.
Regarding Claim 31. Hung teaches a method of manufacturing (block diagram 1800, in Fig 18) an image sensor, comprising (See the entire document Figs 18, 9-17 along with other figures and relevant disclosures, specifically; as cited below):
forming a pixel region (110a/110b of 900; Fig 9 [0051-0053] in steps 1802; Fig 18; [0067]) buried in a semiconductor substrate (104; first disclosed as semiconductor substrate [0023]);
But, Hung does not expressly disclose forming a sacrificial region and related process step in
“forming a sacrificial region buried in the substrate and bordering the pixel region;
performing a first etch into the substrate to form an opening exposing the sacrificial region;
performing a second etch into the substrate through the opening to remove the sacrificial region, wherein removing the sacrificial region laterally extends the opening at the pixel region; and
forming a gate electrode in the opening.”
However, in the analogous art, Chou teaches a method of manufacturing a semiconductor device ([0001), wherein ([0020, fig 2; [0036]) creating of the first trenches and the second trench includes steps of forming a sacrificial layer comprising a plurality of first openings and at least one second opening to expose portions of an upper surface of the substrate; etching the substrate through the first openings and the second opening to form the first trenches and the second trench; and removing the sacrificial layer after the deposition of the electrode layer. (Fig 2; [0036]) illustrates a sacrificial layer 200 is formed on the semiconductor substrate 110 according to a step S304 in FIG. 2.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention, to incorporate the process step S304 of Chou into Hung‘s method so that the combination of (Hung and Chou) have process steps having, at least, “forming a sacrificial region buried (Chou) in the substrate (107 of 104)) and bordering the pixel region (110a), since this inclusion, at least, protects against contamination and functions as a buffer layer for mitigating stress at the interface between substrate and overlaying layer (Chou [0036]).
The combination of (Hung and Chou) subsequently discloses:
performing a first etch (a first etch [0055] with certain depth of trenches, within bulk region 107 of 104. as 1004 of 1000, that does not penetrate doped pixel region 110a/110b of 104; Fig 10; [0055] in a first sub-step 1804; Fig 18; [0068]) into the substrate (104) to form an opening (1004 within 107) exposing the sacrificial region;
performing a second etch (implied remaining etch [0055] within bulk region 110a/110b of 104. as 1004 of 1000, that make hole into doped pixel region 110a/110b of 104; Fig 10; [0055] in a second sub-step 1804; Fig 18; [0068]) into the semiconductor substrate, through the hole, (see below for “to undercut a portion of the semiconductor substrate”) that separates the pixel region from the first side of the semiconductor substrate and to expose the pixel region (110a/110b);
forming a gate electrode (1102 of 1100; Fig 11 [0057] in part of steps 1806; Fig 18; [0069]) in the opening.
As indicated above, the combination of (Hung and Chou) does not expressly disclose: for “to undercut a portion of the semiconductor substrate”)
However, in the another analogous art, Nishida teaches an imaging apparatus ([0001), wherein (Fig 8; [0036]) having a second width (of 103a) greater than the first width’ (of the first hole 103) as disclosed in [0088] as “when the semiconductor substrate 101 is viewed from above, the enlarged diameter portions 103a and 103b on the bottom surface side of the vertical gate electrodes 103-1 and 103-2 protrude from the transfer gate electrode 103-3 on the semiconductor substrate 101”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention, to incorporate the teaching of Nishida into (Hung and Chou) method so that the combination of (Hung, Chou and Nishida) have process steps having, at least, having for “to undercut a portion of the semiconductor substrate for the region that accommodates 103a), since this configuration, at least, by adopting a structure in which the bottom surface side of each of the vertical gate electrodes 103-1 and 103-2 is larger in diameter than the upper side, it is possible to increase the area of the surface (bottom surface) of the transfer gate 103 facing the photoelectric conversion unit 102 while securing the distance from the transfer gate electrode 103-3 to the floating diffusion region 105 and/or the ground contact 106, and thus it is possible to suppress deterioration in transfer efficiency while suppressing deterioration in image quality due to formation of the strong electric field (Nishida [0090)
Regarding Claim 32. The combination of (Hung, Chou and Nishida) the method according to claim 31, further teaches, wherein the removing of the sacrificial region laterally extends the opening outward in multiple (construed from Nishida wherein (Fig 8; [0036]) having a second width (of 103a) greater than the first width’ (of the first hole 103) as disclosed in [0088] as “when the semiconductor substrate 101 is viewed from above, the enlarged diameter portions 103a and 103b on the bottom surface side of the vertical gate electrodes 103-1 and 103-2 protrude from the transfer gate electrode 103-3 on the semiconductor substrate 101”place holder of ) , opposite directions in a cross-sectional plane.
Regarding Claim 33. The combination of (Hung, Chou and Nishida) the method according to claim 31, further teaches, wherein the removing of the sacrificial region multiple (construed from Nishida wherein (Fig 8; [0036]) laterally extends the opening outward in a single direction in a cross- sectional plane.
Regarding Claim 34. The combination of (Hung, Chou and Nishida) the method according to claim 31, further teaches, further comprising:
doping the substrate (Chou [0036]) to form a passivation layer above the sacrificial region,
wherein the passivation layer has an opposite doping type as the sacrificial region, and wherein the first etch extends into the passivation layer (Chou [0036] overlying layer 220 sequentially formed on the semiconductor substrate 110; 220 may include any dielectric, such as silicon dioxide, silicon nitride, another suitable dielectric material or a combination thereof.).
Regarding Claim 29,35. The combination of (Hung, Chou and Nishida) the method according to claim 25 and/or 34, further teaches, (the method) further comprising:
doping the substrate to form a floating node(120 of 1200; [0059]) before the sacrificial region is formed, wherein the gate electrode is formed bordering the floating node, and wherein the passivation layer is formed after the floating node is formed and before the first etch.
Regarding Claim 36. The combination of (Hung, Chou and Nishida) the method according to claim 35, does not expressly disclose, (the method) further comprising:
doping the substrate to form a floating node (120 of 1200; [0059]) after the sacrificial region is formed, wherein the gate electrode is formed bordering the floating node.
Claim 37 is rejected under 35 U.S.C. 103 as being unpatentable over Hung; Feng-Chi. et al. (US 0210210532 A1) hereinafter referenced as Hung; in view of CHOU; YI-HSIEN (US 20210217864 A1); hereinafter referenced as Chou ; in further view of NISHIDA; Keiji et al (US 20250133847 A1); hereinafter referenced as Nishida and ITO; TAKUYA et al (US 20250120210 A1); hereinafter referenced as Ito
Regarding Claim 37. The combination of (Hung, Chou and Nishida) the method according to claim 35, does not expressly disclose, wherein the second etch comprises etching using a chlorine chemical etchant (Chou discloses RIE [0039) having an etch rate for the sacrificial region that is higher than an etch rate for the pixel region .
However, in the another analogous art, Ito teaches an imaging apparatus ([0001), wherein ([0020]) the etching condition of RIE when the first trench and the second trench are hollowed out may be set as follows, for example. [0201] Chamber internal pressure: 5 to 100 (millitorr (mTorr)) [0202] Source power: 500 to 2000 (watts (W)) [0203] Bias power: 100 to 1000 (W) [0204] Chlorine gas flow: 10 to 300 (cubic centimetre per minute (sccm) [0205] Oxygen gas flow: 1 to 50 sccm.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention, to incorporate the teaching of Ito into the combination of (Hungm Chou and Nishida) method so that the combination of (Hung, Chou, Nishida and Ito ) have process steps having, at least, he second etch comprises etching using a chlorine chemical etchant (Chou discloses RIE [0039) having an etch rate for the sacrificial region that is higher than an etch rate for the pixel region, Since chlorine (Cl)-based gases, are generally used during the dry etching. Like RIE in Chou
Conclusion
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/MOAZZAM HOSSAIN/Primary Examiner, Art Unit 2898
September 29, 2026
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