DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention II, claims 10-20 in the reply filed on 11/25/2025 is acknowledged. Non-elected claims 1-9 have been canceled. Claims 10-29 are currently pending.
Claim Objections
Claim 14 objected to because of the following informalities: “between under” in the last line of the claim. The last line of claim 14 is understood and interpreted as being the same as the last line of claim 15, namely, the last line of claim 14 should read:
an interface layer.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 22 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 22, the limitation “between the plurality of rows” in line 3 is unclear because there are more than two rows.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 10 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Park et. al., U.S. Pat. Pub. 2019/0067115, hereafter Park, in view of Koketsu et. al., U.S. Pat. 10,056,336, hereafter Koketsu.
Regarding claim 10, Park discloses a method, comprising:
forming (Figs. 1,2A,2B) a plurality of active fin structures [120] above a substrate [100] in an active device region (Park only shows an active device region) of a semiconductor device;
forming (Figs 1,2A, 2B) a shallow trench isolation (STI) region [200] above the substrate, wherein a first portion of the STI region is formed between the plurality of active fin structures [120] in the active device region;
forming (Figs 1, 2A, 2B) a first plurality of dummy gate structures [310],[320] above the first portion of the STI region [200] in the active device region, wherein the first plurality of dummy gate structures wrap around the plurality of active fin structures on at least three sides of the plurality of active fin structures (see Fig. 2A).
Park fails to explicitly disclose
wherein a second portion of the STI region is formed above the substrate in an alignment mark region of the semiconductor device;
forming a second plurality of dummy gate structures above the second portion of the STI region in the alignment mark region; and
etching the second plurality of dummy gate structures to form an alignment mark pattern in the alignment mark region.
However, Koketsu discloses (Fig. 9)
wherein a second portion of the STI region [P3] is formed above the substrate [1S] in an alignment mark region [ALIGNMENT MARK FORMATION REGION] of the semiconductor device;
forming a second plurality of dummy gate structures [P2] above the second portion of the STI region [P3] in the alignment mark region; and
etching (Fig. 14) the second plurality of dummy gate structures [P2] to form an alignment mark pattern [P2] in the alignment mark region.
It would have been obvious to one of ordinary skill in the art prior to effective filing date of the instant application to form alignment mark patterns and isolation structures in the same method step with forming gate electrode patterns and the isolation region in the active region because this simplifies the manufacturing process.
Regarding claim 21, Park discloses (Figs 1, 2A,2B) a method, comprising:
forming a plurality of active fin structures [120] above a substrate [100] in an active device region (Park does not disclose a region other than the active region) of a semiconductor device;
forming a first plurality of dummy gate structures [310],[320] in the active device region,
wherein the first plurality of dummy gate structures [310],[320] wrap around the plurality of active fin structures [120];
Park fails to explicitly disclose
forming a second plurality of dummy gate structures in an alignment mark region; and
etching the second plurality of dummy gate structures to form an alignment mark pattern in the alignment mark region.
However, Koketsu discloses (Fig. 9)
forming a second plurality of dummy gate structures [P2] above the second portion of the STI region [P3] in the alignment mark region; and
etching (Fig. 14) the second plurality of dummy gate structures [P2] to form an alignment mark pattern [P2] in the alignment mark region.
It would have been obvious to one of ordinary skill in the art prior to effective filing date of the instant application to form alignment mark patterns in the same method step with forming gate electrode patterns in the active region because this simplifies the manufacturing process.
Claims 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et. al., U.S. Pat. 9,823,574, hereafter Chen, in view of Yang et. al., U.S. Pat. 9,024,456, hereafter Yang.
Regarding claim 17, Chen discloses (Fig. 1, Col.3, lines 17-47) a method, comprising: receiving a substrate [110] with a photoresist layer(see the citation above, not shown in Fig 1) in an exposure tool [120]; and directing extreme ultraviolet (EUV) radiation from a radiation source [122] to the photoresist layer to form a patterned photoresist layer in an exposure operation, wherein a gate-based alignment mark pattern [114] (Col. 8, lines 36-47) in a gate-based alignment mark region is used to align the substrate for the exposure operation.
Chen fails to explicitly disclose a polysilicon-gate-based alignment mark in a polysilicon-gate-based alignment mark region.
However, Yang discloses (Col. 3, line 63-Col.4, line 2) a polysilicon-gate-based alignment mark in a polysilicon-gate-based alignment mark region.
It would have been obvious to one of ordinary skill in the art prior to effective filing date of the instant application to use polysilicon-gate-based alignment mark as taught by Yang because this material is commonly used for both gates and alignment marks.
Regarding claim 18, Chen in view of Yang discloses everything as applied above. Chen further discloses (Col. 8, lines 36-47) using a fin based alignment mark pattern in a fin based alignment mark region.
The limitation “wherein the exposure operation comprises a second exposure operation; and wherein the method further comprises: directing EUV radiation from the radiation source to another photoresist layer to form another patterned photoresist layer in a first exposure operation that is performed prior to the second exposure operation, wherein a fin based alignment mark pattern in a fin based alignment mark region is used to align the substrate for the first exposure operation” is further obvious over Chen because more than one exposure operations and multiple photoresist layers are routinely used in the photolithography process.
Regarding claim 19, Chen in view of Yang discloses everything as applied above. The limitation “wherein the fin based alignment mark region and the polysilicon-gate based alignment mark region are located in different regions of the substrate” is further obvious over Chen in view of Yang. Chen further teaches (Col. 8, lines 36-47) that the alignment marks [142],[144] (Fig. 4) which are located in different regions of the substrate, can be in active layer (or fin layer) and gate layer, for example. Yang discloses polysilicon-gate based layer alignment marks.
Regarding claim 20, Chen in view of Yang discloses everything as applied above. The limitation “wherein the polysilicon-gate based alignment mark region is located around a perimeter of the fin based alignment mark region” is further obvious over Chen (Col. 8, lines 36-47) in view of Yang, because, for example, [142] in Fig. 4 can be gate based layer alignment marks, and [144] fin based alignment marks surrounded by [142].
Allowable Subject Matter
Claims 11-16 and 23-29 and objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record is silent about the method of forming non-active fin structure and the dummy gate structure in the alignment mark region, to which claims 11-16 and 23-29 are directed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR V BARZYKIN whose telephone number is (571)272-0508. The examiner can normally be reached Monday-Friday, 9am-5pm.
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/VICTOR V BARZYKIN/ Examiner, Art Unit 2893
/Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893
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