Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/02/2025 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5, 8-11 and 14-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (Pub. No.: US20150270176) (hereinafter Xie) in view of Zhang (Pub. No.: US 2020/0335594) and further in view of German Patent No.: DE10101710363) (refer to Machine’s translation version) (hereinafter `363).
Re claim 1, Xie teaches a method, comprising:
providing a semiconductor structure that includes a gate structure (114B) and a source/drain contact (TS, Fig. 2A) over an active region, a selectivity metal layer (one of the top most layer 114B, note that “it (114B) may be comprised of one or more metal layers”, ¶ [0031]) over the gate structure (bottom most electrode layer 114B), and a self-aligned capping (SAC) layer (116) over the selectivity metal layer;
depositing an etch stop layer (ESL) (140, Fig. 2I) and a dielectric layer (166) over the SAC layer;
forming a gate contact opening (the openings which later on are filled with 124R/126R/150/162, Fig. 2I) through the dielectric layer (166), the ESL (140), and the SAC (116) to expose the selectivity metal layer (one of the top most layer 114B);
Xie fails to teach the limitations as shown right immediately below.
Zang teaches depositing a first glue layer (24, FIG. 7, ¶ [0015]) over the gate contact opening;
depositing a first metal fill layer (16) over the first glue layer;
etching back the first metal fill layer and the first glue layer (16/24, FIG. 3 → 4);
after the etching back, forming a source/drain contact (62, FIG. 11A) via opening (46 of FIG. 7A) through the dielectric layer (32) to expose the source/drain contact;
depositing a second glue layer (40, FIG. 11A) over the first metal fill layer (16) in the gate contact opening (38 of FIG. 5A) and the source/drain contact (62) via opening (46);
depositing a second metal fill layer (42) over the second glue layer (40); and
after the depositing of the second metal fill layer, planarizing the semiconductor structure (FIG. 11A, [0030]).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of preventing unwanted over-polishing of the gate caps or unwanted under-polishing of the gate caps as taught by Zang, [0003].
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Moreover, after the combining of Xie and Zang would teach after the etching back, forming a source/drain contact via opening through the dielectric layer and the ESL to expose the source/drain contact; and
depositing a first glue layer (24) over the gate contact opening (38 of Zang) to contact the selectivity metal layer (top most electrode layer 114B of Xie) over the gate structure (bottom most electrode layer 114B).
Additionally, Xie and Zang fails to teach after the depositing of the ESL and the dielectric layer, forming a gate contact opening through the dielectric layer, the ESL.
`363 teaches after the depositing of the ESL (76, FIG. 20 → 21) and the dielectric layer (78), forming a gate contact opening (90) through the dielectric layer, the ESL.
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of preventing metal gates can be short-circuited with the adjacent contact plugs of the source and drain regions as taught by `363, [0002].
Re claim 2, in the combination, Zang teaches the method of claim 1, wherein the depositing of the first metal fill layer comprises depositing the first metal fill layer (16 of FIG. 3A) until a top surface of the first metal fill layer is higher than a top surface of the SAC layer (32).
Re claim 3, in the combination, Zang teaches the method of claim 1, wherein, after the depositing of the first metal fill layer (16 of FIG. 4), the gate contact opening (38) is not completely filled (30 of FIG. 5).
Re claim 5, in the combination, Zang teaches the method of claim 1, wherein the etching back comprises etching the first metal fill layer until a top surface of the first metal fill layer (16, FIG. 4) is substantially coplanar with a top surface of the SAC layer (32).
Re claim 8/14, in the combination, Zang, FIG. 11A teaches the method of claim 1/10, wherein, after the depositing of the second glue layer (40), the second glue layer is in direct contact with a top surface of the first glue layer (24), a top surface of the first metal fill layer (16), the ESL, and the dielectric layer (32, note that 32 is equivalent to ESL 140 and dielectric layer 160 of Xie).
Re claim 9/15, in the combination, Zang, FIGS. 11A teaches the method of claim 1/10, wherein, after the depositing of the second metal fill layer (42), the second metal fill layer is spaced apart from a top surface of the first glue layer (24), a top surface of the first metal fill layer (16), the ESL, and the dielectric layer by the second glue layer (40).
Re claim 10, Xie, Fig. 2I teaches a method, comprising:
providing a semiconductor structure that includes a gate structure and a source/drain contact (TS) over an active region, a gate spacer (118) disposed between the gate structure (114B/116) and the source/drain contact (TS) a selectivity metal layer (one of the top most layer 114B) over the gate structure (bottom most electrode layer 114B), and a self-aligned capping (SAC) layer (116) over the selectivity metal layer and the gate spacer (118);
depositing an etch stop layer (ESL) (140, Fig. 2I) and a dielectric layer (166) over the SAC layer;
forming a gate contact opening (the openings which later on are filled with 124R/126R/150/162, Fig. 2I) through the dielectric layer (166), the ESL (140), and the SAC (116) to expose the selectivity metal layer;
Xie fails to teach the limitations as shown right immediately below.
Zang teaches depositing a first glue layer (24, FIG. 7, ¶ [0015]) over the gate contact opening;
depositing a first metal fill layer (16) over the first glue layer without completely filling the gate contact opening (38 as shown in FIG. 4A);
etching back the first metal fill layer (16) and the first glue layer (24, FIG. 3 → 4) until the top surface of the first metal fill layer is substantially coplanar with the top surface of the SAC layer (32);
after the etching back, forming a source/drain contact (62, FIG. 11A) via opening (46 of FIG. 7A) through the dielectric layer (32) to expose the source/drain contact;
depositing a second glue layer (40, FIG. 11A) over the first metal fill layer (16) in the gate contact opening (38 of FIG. 5A) and the source/drain contact (62) via opening (46);
depositing a second metal fill layer (42) over the second glue layer (40); and
after the depositing of the second metal fill layer, planarizing the semiconductor structure (FIG. 11A, [0030]).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of preventing unwanted over-polishing of the gate caps or unwanted under-polishing of the gate caps as taught by Zang, [0003].
Moreover, after the combining of Xie and Zang would teach after the etching back, forming a source/drain contact via opening through the dielectric layer and the ESL to expose the source/drain contact.
Additionally, Xie and Zang fails to teach the top surface of the first metal fill layer is lower than a top surface of the ESL but is higher than a top surface of the gate spacer.
`363 teaches the top surface of the first metal fill layer (74’, FIG. 21) is lower than a top surface of the ESL (76) but is higher than a top surface of the gate spacer (56).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of preventing metal gates can be short-circuited with the adjacent contact plugs of the source and drain regions as taught by `363, [0002].
Re claim 11, in the combination, `363 teaches the method of claim 10,
wherein the forming of the gate contact opening (90, FIG. 20 → 21) is performed after the depositing of the ESL (76) and the dielectric layer (78), and
wherein, after the depositing of the first metal fill layer (74’) the gate contact opening (90) is not completely filled (because of 94 of FIG. 22).
Re claim 16, Xie, Fig. 2I teaches a method, comprising:
providing a semiconductor structure that includes a gate structure and a source/drain contact (TS) over an active region, a selectivity metal layer (one of the top most layer 114B) over the gate structure (bottom most electrode layer 114B), and a self-aligned capping (SAC) layer (116) over the selectivity metal layer;
depositing an etch stop layer (ESL) (140, Fig. 2I) and a dielectric layer (166) over the SAC layer;
after the depositing of the ESL and the dielectric layer, forming a gate contact opening (the openings which later on are filled with 124R/126R/150/162/160, Fig. 2I) through the dielectric layer (166), the ESL (140), and the SAC (116) to expose the selectivity metal layer (top most electrode layer 144B) over the gate structure (bottom most electrode layer 114B);
Xie fails to teach the limitation as shown right immediate below.
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Zang teaches depositing a first metal fill layer (16) over the gate contact opening without completely filling the gate contact opening (38 as shown in FIG. 4A);
etching back the first metal fill layer (16, FIG. 3 → 4);
after the etching back, forming a source/drain contact (62, FIG. 11A) via opening (46 of FIG. 7A) through the dielectric layer (32) to expose the source/drain contact;
depositing a second metal fill layer (60/62/42, FIGS. 11/11A) over the first metal fill layer (16) in the gate contact opening (38 of FIG. 5A) and the source/drain contact (62) via opening (46); and
after the depositing of the second metal fill layer, planarizing the semiconductor structure (FIGS. 11/11A, [0030]).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of preventing unwanted over-polishing of the gate caps or unwanted under-polishing of the gate caps as taught by Zang, [0003].
Moreover, after the combining of Xie and Zang would teach after the etching back, forming a source/drain contact via opening through the dielectric layer and the ESL to expose the source/drain contact.
Additionally, Xie and Zang fails to teach after the depositing of the ESL and the dielectric layer, forming a gate contact opening through the dielectric layer, the ESL.
`363 teaches after the depositing of the ESL (76, FIG. 20 → 21) and the dielectric layer (78), forming a gate contact opening (90) through the dielectric layer, the ESL.
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of preventing metal gates can be short-circuited with the adjacent contact plugs of the source and drain regions as taught by `363, [0002].
Re claim 17, in the combination, Zang, FIGS. 11A teaches the method of claim 16, further comprising: before depositing the first metal fill layer (16), depositing a first glue layer (24) over the gate contact opening.
Re claim 18, in the combination, Zang, FIGS. 11 teaches the method of claim 16, further comprising: before depositing the second metal fill layer (42/60), depositing a second glue layer (40) over the first metal fill layer (16) and the source/drain contact (34) via opening.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Zhang/`363 and further in view of Shih (Patent No.: US 10163691).
Re claim 4, Xie/Zhang/`363 teaches all the limitation of claim 1.
Xie/Zhang/`363 fails to teach the limitation as shown right immediate below.
Shih teaches wherein the glue layer comprise cobalt (Co), tungsten (W), molybdenum (Mo), titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), or a combination thereof (902, FIG. 9, col. 12, lines 25-30).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of preventing the electron migration from the conductive material as taught by Shih.
Moreover, after the combining of Xie/Zhang and Lee would teach wherein the first glue layer and the second glue layer comprise cobalt (Co), tungsten (W), molybdenum (Mo), titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), or a combination thereof (902, FIG. 9, col. 12, lines 25-30).
Claim(s) 6-7, 12-13 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Zhang/`363 and further in view of Lee (Patent No.: US 10164032).
Re claims 6/7, Xie/Zhang/`363 teaches all the limitation of claim 1/10/16.
Xie/Zhang/`363 fails to teach the limitation of claim 6/7/12/13/19/20.
Lee teaches wherein the etching back comprises a dry etch process that uses oxygen, hydrogen, nitrous oxide, nitrogen, a fluorine-containing gas, or a chlorine-containing gas (col. 11, Lines 55-63) (claim 19), wherein the dry etch process comprises a radio frequency (RF) power of greater than 100W (anisotropic etch to remove 950, Figs. 9 → 11, col. 10, lines 21-30) (claim 6/12); and
wherein the dry etch process comprises a radio frequency (RF) power between about 100 W and about 300 W (claim 7/13/20) and a temperature between about 20°C and about 90°C (“at a temperature of less than 200° C. (e.g., 20-100° C.)” col. 11, Lines 55-63) (claim 13/20).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of enhancing the technique of etching the semiconductor layers as taught by Lee, col. 11, Lines 55-63.
In re claim 6/20, Lee differs from the claim invention by not disclosing a direct current (DC) bias between about 100 V and about 800 V.
However, Applicant has not disclosed that the ranges are for particular unobvious purpose, produce an unexpected result, or are otherwise critical. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to include the above said teaching, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages."); In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969) (Claimed elastomeric polyurethanes which fell within the broad scope of the references were held to be unpatentable thereover because, among other reasons, there was no evidence of the criticality of the claimed ranges of molecular weight or molar proportions.). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Laboratories Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997).
Response to Arguments
Applicant's arguments with respect to claims 1, 10 and 16 on the remarks filed on 12/02/2025 have been considered but are not persuasive. Please see the detail of rejections as listed above.
Conclusion
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/TONY TRAN/Primary Examiner, Art Unit 2893