Prosecution Insights
Last updated: October 22, 2026
Application No. 18/446,413

PACKAGE STRUCTURE HAVING DAM STRUCTURE

Non-Final OA §102§103
Filed
Aug 08, 2023
Examiner
BOYLE, ABBIGALE A
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
60%
Grant Probability
Moderate
1-2
OA Rounds
2m
Est. Remaining
72%
With Interview

Examiner Intelligence

Grants 60% of resolved cases
60%
Career Allowance Rate
213 granted / 356 resolved
-8.2% vs TC avg
Moderate +13% lift
Without
With
+12.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
13 currently pending
Career history
401
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
54.6%
+14.6% vs TC avg
§102
25.9%
-14.1% vs TC avg
§112
18.3%
-21.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 356 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claim 9 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 23 June 2026. Information Disclosure Statement The information disclosure statement filed 27 September 2024 fails to comply with 37 CFR 1.98(a)(3)(i) because it does not include a concise explanation of the relevance, as it is presently understood by the individual designated in 37 CFR 1.56(c) most knowledgeable about the content of the information, of each reference listed that is not in the English language. It has been placed in the application file, but the information referred to therein has not been considered. Drawings The drawings are objected to because: The sheets of drawings should be numbered in consecutive Arabic numerals, starting with 1. The drawing sheet numbering must be clear and larger than the numbers used as reference characters to avoid confusion. The number of each sheet should be shown by two Arabic numerals placed on either side of an oblique line, with the first being the sheet number and the second being the total number of sheets of drawings, with no other marking. See Page(s) 1-12. The drawings comprise at least one figure comprising two or more independent figures requiring individual designation as separate features and therefore the drawings require a numbering change to the figures. Otherwise, if the multiple figures designated as one should be properly identified as an exploded view using brackets as already objected to supra. For numbering figures, the different views must be numbered in consecutive Arabic numerals, starting with 1, independent of the numbering of the sheets and, if possible, in the order in which they appear on the drawing sheet(s). Refer to 37 CFR 1.84(u). See Figure(s) 5 and 11. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: The following title is suggested: Package Structure Having Lid with Dam Hermetically Sealing Semiconductor Device from Passive Devices. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1-3 and 5-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (U.S. 2020/0161275). Regarding Claim 1, Lin et al., Figure 5b-1 discloses a package structure, comprising: a packaging substrate (substrate 52); a semiconductor device disposed on and electrically connected to the packaging substrate (semiconductor device 50); passive components disposed on the packaging substrate, wherein the semiconductor device is surrounded by the passive components (passive components 53); a lid disposed on the packaging substrate, the lid covering the semiconductor device and the passive components (lid 70); and a dam structure disposed between the packaging substrate and the lid, wherein the dam structure is laterally spaced apart from the passive components and laterally encloses the semiconductor device (dam structure 62). Regarding 2, Lin et al., Figure 5b-1 further discloses the package structure as claimed in claim 1, wherein the semiconductor device comprises: an interposer wiring substrate disposed on and electrically connected to the packaging substrate (wiring substrate 18); at least one semiconductor die disposed on and electrically connected to the interposer wiring substrate (die 10); and an insulating encapsulant disposed on the interposer wiring substrate and the laterally encapsulating the at least one semiconductor die (encapsulant 16). Regarding 3, Lin et al., Figure 5b-1 further discloses the package structure as claimed in claim 1 further comprising a thermal interface material disposed between the semiconductor device and the lid (TIM 64, [0040]). Regarding 5, Lin et al., Figure 5b-1 further discloses the package structure as claimed in claim 3, wherein the thermal interface material comprises a metallic thermal interface material, and the metallic thermal interface material covers a top surface and sidewalls of the semiconductor device (TIM 64). Regarding 6, Lin et al., Figure 5b-1 further discloses the package structure as claimed in claim 5, wherein the metallic thermal interface material is in contact with the dam structure (TIM 64, dam 62). Claim(s) 1 and 7-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Loo et al. (U.S. 2011/0018125). Regarding Claim 1, Loo et al., Figures 6-8 and 15 discloses a package structure, comprising: a packaging substrate (substrate 10); a semiconductor device disposed on and electrically connected to the packaging substrate (semiconductor device 12); passive components disposed on the packaging substrate, wherein the semiconductor device is surrounded by the passive components (passive components 40); a lid disposed on the packaging substrate, the lid covering the semiconductor device and the passive components (lid 18); and a dam structure disposed between the packaging substrate and the lid, wherein the dam structure is laterally spaced apart from the passive components and laterally encloses the semiconductor device (dam structure 60 or 70 or 102). Regarding 7, Loo et al., Figures 6-8 and 15 further discloses the package structure as claimed in claim 1, wherein a cavity between the packaging substrate and the lid comprises: an inner region between the semiconductor device and the dam structure (inner region 62); and an outer region between the dam structure and the lid (outer region 108). Regarding 8, Loo et al., Figures 6-8 and 15 further discloses the package structure as claimed in claim 7, wherein the inner region is an air-tight region, the outer region is an open region, and the inner region is spaced apart from the outer region by the dam structure (inner region 62, dam structure 60 or 70 or 102, outer region 108). Claim(s) 1-2 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (U.S. 2018/0342466). Regarding Claim 1, Lin et al., Figures 5 and 6a-d, discloses a package structure, comprising: a packaging substrate (substrate 10); a semiconductor device disposed on and electrically connected to the packaging substrate (device 20); passive components disposed on the packaging substrate, wherein the semiconductor device is surrounded by the passive components (passive components 28); a lid disposed on the packaging substrate, the lid covering the semiconductor device and the passive components (lid 46. [0034]); and a dam structure disposed between the packaging substrate and the lid, wherein the dam structure is laterally spaced apart from the passive components and laterally encloses the semiconductor device (dam structure 30 or 30/32). Regarding 2, Lin et al., Figures 5 and 6a-d, further discloses the package structure as claimed in claim 1, wherein the semiconductor device comprises: an interposer wiring substrate disposed on and electrically connected to the packaging substrate (interposer 22); at least one semiconductor die disposed on and electrically connected to the interposer wiring substrate (die 21); and an insulating encapsulant disposed on the interposer wiring substrate and the laterally encapsulating the at least one semiconductor die (insulating encapsulant 25). Regarding 7, Lin et al., Figures 5 and 6a-d, further discloses the package structure as claimed in claim 1, wherein a cavity between the packaging substrate and the lid comprises: an inner region between the semiconductor device and the dam structure (inner region containing 26); and an outer region between the dam structure and the lid (outer region between 30 and 40). Claim(s) 10-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (U.S. 2018/0342466). Regarding Claim 10, Lin et al., Figures 5 and 6a-d, discloses a package structure, comprising: a packaging substrate (substrate 10); a semiconductor device disposed on and electrically connected to the packaging substrate (device 20); a lid disposed on the packaging substrate, the lid covering the semiconductor device (lid 46/40, [0034]); and a dam structure disposed between the packaging substrate and the lid, wherein the dam structure comprises (dam structure 30/23): main portions extending along sidewalls of the semiconductor device (main portions 30); and extension portions connecting ends of the main portions, wherein the main portions and the extension portions laterally enclose the semiconductor device (extension portions 32). Regarding 11, Lin et al., Figures 5 and 6a-d, further discloses the package structure as claimed in claim 10, wherein a first minimum distance between the main portions and the sidewalls of the lid is greater than a second minimum distance between the extension portions and the sidewalls of the lid (sidewall 40, extension portion 32, main portion 32). Regarding 12, Lin et al., Figures 5 and 6a-d, further discloses the package structure as claimed in claim 10 further comprising passive components disposed on the packaging substrate, wherein the semiconductor device is surrounded by the passive components, and the main portions extend between the semiconductor device and the passive components (main portion 30, passive components 28, semiconductor device 20). Regarding 13, Lin et al., Figures 5 and 6a-d, further discloses the package structure as claimed in claim 12, wherein the passive components comprise groups of passive components, and a first group among the groups of passive components is laterally spaced apart from a second group among the groups of passive components by one of the extension portions (passive components 28, extensions 32). Regarding 14, Lin et al., Figures 5 and 6a-d, further discloses the package structure as claimed in claim 12, wherein the passive components are distributed outside regions surrounded by the extension portions (passive components 28, extension portions 32). Regarding 15, Lin et al., Figures 5 and 6a-d, further discloses the package structure as claimed in claim 10, wherein regions surrounded by the extension portions are distributed in proximity to corners of the semiconductor device and/or midpoints of the sidewalls of the semiconductor device (semiconductor device 20, extension portions 32). Claim(s) 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (U.S. 2018/0342466). Regarding Claim 16, Lin et al., Figures 5 and 6a-d, discloses a package structure, comprising: a packaging substrate (substrate 10); a semiconductor device disposed on and electrically connected to the packaging substrate (semiconductor device 20); a lid disposed on the packaging substrate, the lid covering the semiconductor device (lid 46/40, [0034]); and a dam structure disposed between the packaging substrate and the lid, wherein the dam structure comprises (dam 30/32): main portions each extending along sidewalls of the semiconductor device (main portions 30); and extension portions laterally extending from ends of the main portions toward inner sidewalIs of the lid (extensions 32). Regarding 17, Lin et al., Figures 5 and 6a-d, further discloses the package structure as claimed in claim 16 further comprising groups of passive components disposed on the packaging substrate, wherein the semiconductor device is surrounded by the passive components, and the main portions extend between the semiconductor device and the groups of passive components (passive components 28, main portions 30). Regarding 18, Lin et al., Figures 5 and 6a-d, further discloses the package structure as claimed in claim 17, wherein a first group among the groups of passive components is laterally spaced apart from a second group among the groups of passive components by one of the extension portions (extension portion 32, passive components 28). Regarding 19, Lin et al., Figures 5 and 6a-d, further discloses the package structure as claimed in claim 17, wherein regions surrounded by the extension portions are free of the groups of passive components (extension portions 32). Regarding 20, Lin et al., Figures 5 and 6a-d, further discloses the package structure as claimed in claim 16, wherein a first minimum distance between the main portions and the sidewalls of the lid is greater than a second minimum distance between the extension portions and the sidewalls of the lid (sidewall 40, extension portion 32, main portion 32). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (U.S. 2020/0161275 as applied to claim 3 above, and further in view of Eid et al. (U.S. 2020/0194335). Regarding 4, Lin et al. further discloses that the thermal interface material comprises solder (Lin et al., [0040]), but does not explicitly disclose a backside metal layer disposed between the thermal interface material and the semiconductor device. In the same field of endeavor, Eid et al. discloses that solder thermal interface material requires a backside metal layer in order to adhere to the backside of the die (Eid et al., [0003]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a backside metal late r disposed between the thermal interface material and the semiconductor device in order to allow the TIM to wet the back surface of the die (Eid et al., [0003]). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Hung (U.S. 2014/0252634) discloses a semiconductor device and passive devices under a lid and separated by a dam structure. Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Abbigale Boyle whose telephone number is 571-270-7919. The Examiner can normally be reached from 11 A.M to 7 P.M., Monday through Friday. If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Zandra Smith, can be reached at 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance form a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. Abbigale Boyle Examiner, Art Unit 2899 /ABBIGALE A BOYLE/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Aug 08, 2023
Application Filed
Oct 05, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
60%
Grant Probability
72%
With Interview (+12.6%)
3y 5m (~2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 356 resolved cases by this examiner. Grant probability derived from career allowance rate.

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