Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on May 14, 2026 has been entered.
Response to Amendment
Applicant’s Amendment filed May 14, 2026 has been fully considered and entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 8-25 are rejected under 35 U.S.C. 103(a) as being unpatentable over Stephens et al. (US 2014/0363120 A1) in view of Uhland et al. (US 2007/0254411 A1).
Regarding claims 8-12, 16-18 and 21-24, Stephens discloses a method of fabricating a semiconductor package (10 in Fig. 1), comprising:
forming a first die (15) and a second die (14), wherein each of the first die and the second die comprises:
a semiconductor substrate (32 in Fig. 2);
an integrated circuit (39; paragraph 0022) formed on the semiconductor substrate;
a top surface of the integrated circuit; a bottom surface of the semiconductor substrate, the top surface being opposite to the bottom surface; and a side surface substantially perpendicular to the bottom surface and the top surface (see Fig. 2);
a conductive region (paragraph 0021 discloses dies 12-15 including edge connectors and/or contacts used to provide electric connections within each die to the backplane die 11) disposed in a dielectric region (paragraph 0023 discloses each integrated circuit comprising dielectric layers) of the integrated circuit, each conductive region being electrically coupled to an interconnect structure (paragraph 0021 discloses each die may be formed with through-silicon vias to provide vertical signal conductors for the die stack) disposed in the integrated circuit;
bonding the top surface of the first die to the bottom surface of the second die to form a first die group (paragraph 0021 discloses the dies 12-15 may be implemented as a die stack rather than separated dies); and
forming a base substrate structure (11 in Fig. 1), the base substrate structure characterized by a top surface that includes a first conductive region and a second conductive region disposed in a dielectric region of the base substrate structure, the first conductive region and the second conductive region being electrically coupled to an interconnect structure of the base substrate structure (paragraph 0021 discloses backplane 11 including dielectric layers formed to cover interconnect features, and dies 12-15 including edge connectors and/or contacts used to provide electric connections to respective slots 16a-16d on the top surface of the backplane);
bonding, sideways, the first die group to the base substrate structure, the side surface of the first die being bonded to the top surface of the base substrate structure, with the conductive region of the first die being bonded to the first conductive region of the base substrate structure, and the side surface of the second die being bonded to the top surface of the base substrate structure, with the conductive region of the second die being bonded to the second conductive region of the base substrate structure (paragraph 0021 discloses each of the dies 12-15 having contacts to provide electrical connection to circuit conductors or electrically conductive devices such as solder balls or flip-chip conductors in the backplane 11); and
wherein the first die provides an electrical coupling to the second die through the top surface of the first die and an electrical coupling to the base substrate structure through the side surface of the first die (paragraph 0021 discloses the dies 12-15 may be implemented as a die stack rather than separated dies, and dies 12-15 include edge connectors and/or contacts used to provide electric connections within each die to the backplane die 11).
Still regarding claims 8-12, 16-18 and 21-24, Stephens further discloses an optical TSV structure (305 in Figs. 22-31) within the substrate (301). Stephens teaches the claimed invention except for a except for a photonic device in the semiconductor substrate of the first die. Uhland discloses a semiconductor package (100 in Fig. 1; 1100 in Fig. 12), comprising a first die (1118) and a second die (1116) stacked and bonded together so as to provide electrical coupling from the first die to the second die, wherein the first die includes a photonic device (1118 must include a photonic device which couples with waveguide 1162; paragraph 0081 discloses 1112-1119 include optical components) in the semiconductor substrate and comprising: an optical interface structure (1162) for coupling to an optical fiber at a bottom surface (“bottom” merely depends on the orientation of the device, 1162 would be at the bottom surface is the device in Fig. 12 was flipped upside down) of the die (paragraph 0093 discloses waveguide 1162 coupling to external optical components; paragraph 0096 discloses positioning optical fibers that couple with 1118); and a waveguide section (core portion 1196 in Fig. 16) configured to facilitate transmission of an optical signal through the optical interface; and cladding layers (portions 1198 surrounding core) surrounding the waveguide section. Since all of the inventions relate to semiconductor packages, one having ordinary skill in the art at the time of the invention would have found it obvious to use a photonic device as disclosed by Uhland in the package of Stephens for the purpose of providing optical connection to an external device.
Still regarding claims 8-12, 16-18 and 21-24, the proposed combination of Stephens and Uhland teaches the claimed invention except for specifically stating the photonic device configured to receive or transmit an optical signal through the optical interface structure at the bottom surface of the first die. However, Stephens at paragraph 0064 further discloses optical signals received through optical interface opening 321 in a transmission path perpendicular to the lateral plane of the semiconductor wafer structure. Since the die is implemented as a die stack with another die disposed on the top (first) surface, one having ordinary skill in the art would have found it obvious to form the optical interface structure at a bottom (second) surface opposite to the first surface, for the purpose of allowing for optical connection to an external device without increasing the size of the device. Further, one of ordinary skill in the art before the effective filing date of the claimed invention would also have found it obvious to couple the optical fiber to any region of the semiconductor package including through the bottom surface of the first die for the purpose of enabling coupling from a wider range of locations and angles to any of the optical components within the semiconductor package, increasing the versatility of the device while producing a compact and robust device.
Regarding claims 13 and 20, Stephens further discloses electrically conductive devices such as solder balls used to connect the dies 12-15 with the backplane 11 in paragraph 0021. The proposed combination of Stephens and Uhland teaches the claimed invention except for specifically stating hybrid bonding. However, hybrid bonding is well-known and commonly used in the art of semiconductor devices and as such, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use hybrid bonding to bond the dielectric regions in addition to the conductive regions for the purpose of enhancing the bond.
Regarding claims 14 and 19, Stephens further discloses removing a portion (312) of the first substrate from a back side of the first die to expose a waveguide section (Figs. 23-31; paragraphs 0052-0056 disclose “backside optical TSV structure” 305). The proposed combination teaches the waveguide section at the bottom surface of the first die as detailed above.
Regarding claim 15, Stephens discloses the bottom surface of the first die and the top surface of the second die are substantially perpendicular to the top surface of the base substrate structure in Fig. 1. id crystal moleculesand specifically stating the exposure voltage greater than a
Regarding claim 25, proposed combination of Stephens and Uhland teaches the claimed invention except for specifically stating the shape of the optical interface structure. However, Uhland at paragraph 0096 discloses fabricating grooves for positioning optical fibers and as such, one having ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to form the shape of the optical interface structure in a stepped manner such that the size of the optical interface structure tapers gradually from an end configured to receive the optical fiber towards the waveguide section in order to securely retain the optical fiber.
Response to Arguments
Applicant's arguments, filed May 14, 2026, with respect to claims have been considered but are moot in view of the new grounds of rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRIS H CHU whose telephone number is (571)272-8655. The examiner can normally be reached on Mon-Fri 9AM-5PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached on 571-272-239797. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Any inquiry of a general or clerical nature should be directed to the Technology Center 2800 receptionist at telephone number (571) 272-1562.
Chris H. Chu
/CHRIS H CHU/Primary Examiner, Art Unit 2874 September 2, 2026
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