DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on April 30, 2026 has been entered.
Response to Arguments
Claims 8, 20, and 25 stand rejected under Section 102 in view of Kato. Claims 1, 4, and 23 stand rejected under Section 103 in view of Yamada and Kato. Claims 8, 10, 15, and 16 stand rejected under Section 103 in view of Yamada. Claims 1, 4, 5, 7, 8, 10, 15, 21, 22, and 24 stand rejected under Section 103 in view of Nagano and Kato. Claims 12 and 13 stand rejected under Section 103 in view of Kato, or Nagano and Kato, and further in view of Augendre. Claim 11 stands rejected under Section 103 in view of Kato, Yamada in view of Kato, or Nagano in view of Kato, and further in view of Wiatr. Claims 7 and 17-20 stand rejected under Section 112(a) for failing to meet the written description requirement. Claims 1, 4, 5, 7, 8, 10-13, and 15-25 stand rejected under Section 112(b). Claims 1, 4, 5, 7, 8, 10-13, 15, 16, and 21-25 stand objected to for informalities. Claims 17-20 stand withdrawn by the Office for being directed to a different invention than that which was originally presented. Claims 2, 3, 6, 9, and 14 were previously canceled.
Applicants amended claim 1, 5, 7, 8, 11, 12, 15-17, 21, 22, and 25. Applicants argue that the application is in condition for allowance.
Claim objections: Applicants’ amendments address the previously noted claim objections and are accepted and entered. No new matter has been added. The previously noted claim objections are withdrawn.
Section 112(b) rejections: Applicants’ amendments overcome all the Section 112(b) rejections with the exception of the rejections of claims 17-20. The Section 112(b) rejections of all claims except claims 17-20 are withdrawn. The Section 112(b) rejections of claims 17-20 are updated and re-stated.
Section 112(a) (written description) rejections: Applicants’ amendments overcome the Section 112(a) written description rejection of claim 7, but not the Section 112(a) written description rejections of claims 17-20. The Section 112(a) written description rejections of claim 7 is withdrawn, and the Section 112(a) written description rejections of claims 17-20 are updated and re-stated.
The Office offers this review of Figure 4F compared with claim 17’s language to demonstrate why claim 17 is not supported by the originally filed disclosure.
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For purposes of the first comparison, top and upper are considered to be top and upper in Figure 4F and bottom is considered to be bottom in Figure 4F. (The second comparison uses Figure 4F, but upside down.) In each comparison, top means top throughout the claim, upper means upper throughout the claim, and bottom means bottom throughout the claim.
First comparison:
Regarding claim 17: Figure 4F shows a semiconductor structure (300) comprising:
a first semiconductor layer (220 in region 202b) over a semiconductor substrate (202), the first semiconductor layer (220 in region 202b) has a first upper surface;
a first isolation feature (224) over the semiconductor substrate (202), wherein a first sidewall, a first bottom surface, and a second sidewall opposing the first sidewall are each defined by the first isolation feature (224), the first bottom surface interfaces the first upper surface of the first semiconductor layer (not supported by Figure 4F because the first upper surface of the first semiconductor layer is on the opposite side of the first isolation feature’s first bottom surface);
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a second isolation feature (217) over the semiconductor substrate (202), wherein the second isolation feature (217) includes a second bottom surface and an uppermost surface, wherein the uppermost surface includes a first portion spaced a first distance from the second bottom surface, a second portion spaced a second distance from the second bottom surface, and a third portion spaced the first distance from the second bottom surface, the second distance less than the first distance and the second portion interposing the first and third portions, and the second bottom surface interfaces the first upper surface of the first semiconductor layer (not supported by Figure 4F because the second bottom surface is on the opposite side of the first upper surface of the first semiconductor layer) and is coplanar with the first bottom surface;
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a first transistor (250) disposed in a second semiconductor layer (220 in region 202a) extending between the first portion and the third portion of the uppermost surface of the second isolation feature (217) and over the second portion of the uppermost surface of the second isolation feature (217) (not supported by Figure 4F because this language appears to place a second semiconductor layer in the same location as the first semiconductor layer);
and a second transistor (260) in the first semiconductor layer (220 in region 202b) adjacent the first isolation feature (224) providing a source/drain feature (262) of the second transistor (260) interfacing the first isolation feature (224).
Second comparison:
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Regarding claim 17: Figure 4F, flipped upside down, shows a semiconductor structure (300) comprising:
a first semiconductor layer (220 in region 202b) over a semiconductor substrate (202), the first semiconductor layer (220 in region 202b) has a first upper surface;
a first isolation feature (224) over the semiconductor substrate (202), wherein a first sidewall, a first bottom surface, and a second sidewall opposing the first sidewall are each defined by the first isolation feature (224), the first bottom surface interfaces the first upper surface of the first semiconductor layer (not supported by Figure 4F because the first upper surface of the first semiconductor layer is on the opposite side of the first isolation feature’s first bottom surface);
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a second isolation feature (217) over the semiconductor substrate (202), wherein the second isolation feature (217) includes a second bottom surface and an uppermost surface, wherein the uppermost surface includes a first portion spaced a first distance from the second bottom surface, a second portion spaced a second distance from the second bottom surface, and a third portion spaced the first distance from the second bottom surface, the second distance less than the first distance and the second portion interposing the first and third portions, and the second bottom surface interfaces the first upper surface of the first semiconductor layer (220 in region 202b) and is coplanar with the first bottom surface;
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a first transistor (250) disposed in a second semiconductor layer (220 in region 202a) extending between the first portion and the third portion of the uppermost surface of the second isolation feature (217) and over the second portion of the uppermost surface of the second isolation feature (217) (not supported by Figure 4F because the second semiconductor layer (220 in region 202a) does not extend along the uppermost surface but along the second bottom surface, and because this language appears to place a second semiconductor layer in the same location as the first semiconductor layer);
and a second transistor (260) in the first semiconductor layer (220 in region 202b) adjacent the first isolation feature (224) providing a source/drain feature (262) of the second transistor (260) interfacing the first isolation feature (224).
Section 102 rejections: Applicants’ amendments do not overcome the previously cited prior art that was used to reject claims 8, 10, and 25. Applicants argue that the Office used element 109 in the bulk region for the second isolation feature. This is incorrect. The second isolation feature is element 109 on the far right, which is within the SOI region. See the annotated Kato Figure 3, below:
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Section 103 rejections: The Section 103 rejections of claim 1 and its dependent claims are withdrawn. Applicants arguments are persuasive. As for the Section 103 rejections of claims 11-13, 15, and 16, the Section 103 rejections of claims 11-13 are maintained while the Section 103 rejections of claims 15 and 16 are withdrawn.
Restriction: The restriction requirement is re-stated in light of the discussion regarding claim 17 and its dependent claims.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 17-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 17: The Office incorporates by reference the discussion above. Claim 17 is not supported by Figure 4F because claim requirement that the first bottom surface interface the first upper surface of the first semiconductor layer is not supported by Figure 4F because the first upper surface of the first semiconductor layer is on the opposite side of the first isolation feature’s first bottom surface), and/or because claim requirement that the second bottom surface interface the first upper surface of the first semiconductor layer (220 in region 202b) is not supported by Figure 4F because the second bottom surface is on the opposite side of the first upper surface of the first semiconductor layer. Furthermore, the claim language places the first and second semiconductor layers in the second isolation structure. See annotated figures above. Because claim 17 is not supported by the originally filed disclosure, claim 17 is rejected for failing to meet the written description requirement.
Claims 18-20 are rejected for depending from rejected base claim 17.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 17-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 17: This claim requires:
A semiconductor structure comprising:
a first semiconductor layer over a semiconductor substrate, the first semiconductor layer has a first upper surface;
a first isolation feature over the semiconductor substrate, wherein a first sidewall, a first bottom surface, and a second sidewall opposing the first sidewall are each defined by the first isolation feature, the first bottom surface interfaces the first upper surface of the first semiconductor layer;
a second isolation feature over the semiconductor substrate, wherein the second isolation feature includes a second bottom surface and an uppermost surface, wherein the uppermost surface includes a first portion spaced a first distance from the second bottom surface, a second portion spaced a second distance from the second bottom surface, and a third portion spaced the first distance from the second bottom surface, the second distance less than the first distance and the second portion interposing the first and third portions, and the second bottom surface interfaces the first upper surface of the first semiconductor layer and is coplanar with the first bottom surface;
a first transistor disposed in a second semiconductor layer extending between the first portion and the third portion of the uppermost surface of the second isolation feature and over the second portion of the uppermost surface of the second isolation feature;
and a second transistor in the first semiconductor layer adjacent the first isolation feature providing a source/drain feature of the second transistor interfacing the first isolation feature.
(emphasis added).
This claim is rejected because the second bottom surface is defined as being associated with the second isolation feature. If the second bottom surface of the second isolation feature is coplanar with the first bottom surface, then the second bottom surface is on the opposite side of the first upper surface of the first semiconductor layer. For these reasons, claim 17 is rejected as indefinite.
Claims 18-20 are rejected for depending from rejected base claim 17.
Election/Restrictions
Newly submitted claims 17-20 directed to an invention that is independent or distinct from the invention originally claimed for the following reasons: The original claims were directed to a semiconductor layer with a transistor on a semiconductor substrate and surrounded by a dielectric feature or isolation feature, along with a semiconductor layer with a transistor within a trench on the upper surface of the dielectric feature or isolation feature. Claim 17 is directed to an embodiment, which the Office believes is not supported by the originally filed disclosure, but if it is, the embodiment has the semiconductor layer and transistor in a space underneath the dielectric feature or isolation feature, not in a trench on the upper surface of the dielectric feature or isolation feature.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 17-20 are withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 8, 10, and 25 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Kato, U.S. Pat. Pub. No. 2007/0194383, Figure 3.
Kato, Figure 3:
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Regarding claim 8: Kato Figure 3 discloses a semiconductor structure comprising: a first isolation feature (109, left, middle, in SOI Region; 103, left, right) over a substrate (101), wherein the first isolation feature (109, left, middle, in SOI Region; 103, left, right) includes a first portion (109, left, in SOI Region) having a first upper surface and a second portion (109, middle, in SOI Region) having a second upper surface, wherein the first upper surface and the second upper surface are substantially planar, and wherein the first isolation feature (109, left, middle, in SOI Region; 103, left, right) further comprising a third portion (103, left), contiguous with the first portion (109, left, in SOI Region) and the second portion (109, middle, in SOI Region), wherein the third portion (103, left) is disposed between the first portion (109, left, in SOI Region) and the second portion (109, middle, in SOI Region), and wherein the third portion (103, left) has a third upper surface, wherein the third upper surface is closer the substrate (101) than the first upper surface; a first transistor (120) disposed in a first semiconductor region (middle: 105, 123, 124) above the third upper surface; a second semiconductor region (right: 105, 133, 134) extending from a sidewall of the second portion (109, middle, in SOI Region) of the first isolation feature (109, left, middle, in SOI Region; 103, left, right), over and interfacing a fourth upper surface (at (103, right)) of the first isolation feature (109, left, middle, in SOI Region; 103, left, right) extending from the sidewall, wherein the fourth upper surface is coplanar with the third upper surface, the second semiconductor region (right: 105, 133, 134) contiguously extending to a sidewall of a second isolation feature (109, right, SOI Region); the second isolation feature (109, right, SOI Region) having a fifth upper surface coplanar with the first upper surface and a bottommost surface of the second isolation feature (109, right, SOI Region) is coplanar with a bottommost surface of each of the first, second and third portions (109, left, middle, right, in SOI Region; 103, left) of the first isolation feature (109, left, middle, in SOI Region; 103, left, right). Kato specification ¶¶ 76-87.
Regarding claim 10, which depends from claim 8: Kato discloses the first isolation feature (109, left, middle, in SOI Region; 103, left, right) comprises an oxide. Id. ¶¶ 77, 80 (SiO2).
Regarding claim 25, which depends from claim 8: Kato discloses a first source/drain region (123) of the first transistor (120) interfaces the first portion (109, left, in SOI Region) of the first isolation feature (109, left, middle, in SOI Region; 103, left, right) and a second source/drain region (124) of the first transistor (120) interfaces the second portion (109, middle, in SOI Region) of the first isolation feature (109, left, middle, in SOI Region; 103, left, right) and a third source/drain region (134) of a second transistor (130) interfaces the second isolation feature (109, right, in SOI Region).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Kato, and further in view of Wiatr, U.S. Pat. Pub. No. 2009/0111223.
Wiatr Figure 2g:
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Regarding claim 11, which depends from claim 8: Kato is silent as to an interlayer dielectric (ILD) on the first upper surface of the first isolation feature.
Wiatr Figure 2g, directed to similar subject matter, discloses an interlayer dielectric (ILD) (240, 241), (ILD (240) comprises etch stop layer (241), id.), on the first upper surface of the first isolation feature (middle left 221, middle right, 221, middle 204, and right-center 204 between middle right 221 and right-most 221), and directly covering an uppermost surface of the second semiconductor region (at transistor element (233B)) contiguously extending from the sidewall of the second isolation feature (right-most isolation feature (221)) to the sidewall of the second portion (middle right 221) of the first isolation feature. Wiatr specification ¶¶ 40, 41. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Kato to incorporate the interlayer dielectric on the first upper surface of the isolation feature because the modification would permit the deposition of contacts (226) to make electrical contact with the first transistor. Id.
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Kato, and further in view of Augendre, U.S. Pat. Pub. No. 2022/0148908, Figure 10.
Augendre, Figure 10:
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Regarding claim 12, which depends from claim 8: Kato is silent as to whether the first isolation feature is disposed in an RF device region of the substrate. Kato discloses that the first isolation feature is in an SOI region of the substrate. Kato specification ¶¶ 77, 79-81.
Augendre Figure 10, which incorporates features of an RF device discussed in Figures 2-9, in Region A, discloses Region A is an SOI region and is separated by STI trenches from Region B, which is a logic region. See Augendre specification ¶¶ 117-122; 81-116; 1-6 (directed to RF devices). One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Kato to include an RF device in the isolation feature because the modification would have involved the substitution of an equivalent known for the same purpose.
Regarding claim 13, which depends from claim 8: Kato is silent as to whether the first transistor is an RF device. Kato discloses that the first isolation feature is in an SOI region of the substrate. Kato specification ¶¶ 77, 79-81.
Augendre Figure 10, which incorporates features of an RF transistor discussed in Figures 2-9, in Region A, discloses Region A is an SOI region with the RF transistor and is separated by STI trenches from Region B, which is a logic region. See Augendre specification ¶¶ 117-122; 81-116; 1-6 (directed to RF devices). One having ordinary skill in the art at a time before the effective filing date would be motivated to replace the first transistor in Kato with an RF transistor because the modification would have involved the substitution of an equivalent known for the same purpose.
Allowable Subject Matter
Claims 1, 4, 5, 7, and 21-24 are allowed.
Claims 15 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With regard to claim 1: The claim has been found allowable because the prior art of record does not disclose “wherein each of the first, second, third and fourth upper boundaries are a contiguous single dielectric material”, in combination with the remaining limitations of the claim.
With regard to claims 4, 5, 7, and 21-24: The claims have been found allowable due to their dependency from claim 1 above.
With regard to claim 15: The claim has been found allowable because the prior art of record does not disclose “wherein the second semiconductor region extends to a top of the substrate”, in combination with the remaining limitations of the claim.
With regard to claim 16: The claim has been found allowable due to its dependency from claim 15 above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTORIA KATHLEEN HALL whose telephone number is (571)270-7567. The examiner can normally be reached Monday-Friday, 8 a.m.-5 p.m.
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/Victoria K. Hall/Primary Examiner, Art Unit 2897
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