DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Claims 1-4, 6, 8, 10, 14, 15, 17, and 19 stand rejected under Section 102 in view of Yamada. Claims 1-8, 10, 14, 15, 17, 19, and 20 stand rejected under Section 102 in view of Nagano. Claims 12, 13, 16, and 18 stand rejected under Section 103 in view of Nagano and Augendre. Claim 9 stands rejected under Section 103 in view of Nagano and Rahman. Claim 11 stands rejected under Section 103 in view of Yamano or Nagano, and further in view of Waitr. Claims 15 and 16 stand objected to for an informality. The specification stands objected to.
Applicants amended claims 1, 4, 5, 7, 8, 10, 11, 12, 13, and 15-17, 19, and 20, canceled claims 2, 3, 6, 9, and 14, and added new claims 21-25. Applicants provided amendments to the specification. Applicants argue that the application is in condition for allowance.
Turning first to the specification: Applicants’ amendments address the previously noted specification objections and are accepted and entered. No new matter has been added. The previously noted specification objections are withdrawn.
Claim objections: Applicants’ amendments to the claims render moot the claim objections. The claim objections are withdrawn as moot.
Section 102 rejections: Applicants’ amendments overcome the previously noted Section 102 rejections. These rejections are withdrawn. However, the previously cited prior art used in the Section 102 rejections can be used as primary references in Section 103 rejections, as noted below. Furthermore, a new reference, Kato, has been identified which provides a basis for Section 102 rejections of claim 8 and some of its dependent claims, as discussed below.
Section 103 rejections: Applicants’ amendments overcome the previously noted Section 103 rejections. However, these rejections have been updated to reflect the changes to the claims, and by adding Kato as a secondary reference, to reject independent claims, as discussed below.
Claim Objections
Claims 1, 4, 5, 7, 8, 10-13, 15, 16, and 21-25 are objected to because of the following informalities:
Claim 1, line 8, defines “an uppermost surface” of the third dielectric structure. Lines 16-17 refer to “the uppermost surface of a single dielectric material”. The second reference to “the uppermost surface” lacks antecedent basis because the uppermost surface is associated with the third dielectric structure, not the single dielectric material. For this reason, claim 1 is objected to.
Claim 1, line 22: Change “structure” to “structures”.
Claims 4, 5, 7, and 21-24 are objected to for depending from objected to base claim 1.
Claim 7, line 2: Claim 5, line 2, defines a first sidewall of the second dielectric structure. Claim 7, which depends from claim 5, also defines a first sidewall of the second dielectric structure. Please review the second definition of the first sidewall of the second dielectric structure in claim 7.
Claim 8: Line 9 defines “a semiconductor region”, followed by line 10, which also defines “a semiconductor region”. Claim 8 later refers to “the semiconductor region” in lines 12-13 without specifying which semiconductor region is being referred to. Because the semiconductor region has been defined twice, claim 8 is objected to.
Claims 10-13, 15, 16, and 25 are objected to for depending from objected-to base claim 8.
Claim 12, line 2: Regarding the term “deposed”—did applicants intend this word or “disposed”?
Claim 25: Lines 1-2 define “a first transistor”. However, claim 8, which claim 25, depends from, also defines “a first transistor”, in line 9. Because a first transistor has been defined twice, claim 25 is objected to.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 7 and 17-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 7, which depends from claim 5, which depends from claim 1: Claim 7 has been amended to require “a second source/drain region of the first transistor interface[] a first sidewall of the second dielectric structure.” However, claim 5 was also amended, and reads “wherein a first source/drain region of the first transistor interfaces a first sidewall of the second dielectric structure.” The originally filed disclosure does not disclose a first transistor which has its first and second source/drain regions interfacing with the same first sidewall of the second dielectric structure. Because this embodiment is not supported by the originally filed disclosure, claim 7 is rejected for failing to meet the written description requirement. For purposes of examination, claim 7 is interpreted consistent with the disclosure, that, is “wherein a second source/drain region of the first transistor interfaces with a first sidewall of the first dielectric structure.”
Regarding claim 17: Claim 17 has been amended to require the following:
a first semiconductor layer over a semiconductor substrate, the first semiconductor layer has a first upper surface; a first isolation feature over the semiconductor substrate, wherein a first sidewall, a first bottom surface, and a second sidewall opposing the first sidewall of the first semiconductor layer is defined by the first isolation feature, the first bottom surface interfaces the first upper surface of the first semiconductor layer;….
This language is confusing, and subject to a Section 112(b) rejection, see below, but to the extent that the claim language is intended to define the structure of the first isolation feature, this feature would have two sidewalls and a bottom surface, the bottom surface being in contact with a first upper surface of the first semiconductor layer. The claim later requires that a second transistor be in the first semiconductor layer adjacent the first isolation feature. This is interpreted to mean that the first semiconductor layer and the first transistor are under the first isolation feature, suggesting that the first semiconductor layer and the first transistor are within a space created by the two sidewalls and the bottom surface of the first isolation feature. This embodiment is not disclosed in the originally filed application and is rejected under Section 112(a) for failing to meet the written description requirement.
Claims 18-20 are rejected for depending from rejected base claim 17.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 4, 5, 7, 8, 10-13, and 15-25 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1: Line 8 defines an uppermost surface of the third dielectric structure. However, lines 16-17 associate the uppermost surface with a single dielectric material. The uppermost surface is defined as associated with the third dielectric structure, not the single dielectric material. As currently written, there is no definition of the third dielectric material as a single dielectric material. Because the language is confusing, claim 1 is rejected as indefinite.
Claims 4, 5, 7, and 21-24 are rejected for depending from rejected base claim 1.
Regarding claim 7, which depends from claim 5, which depends from claim 1: Claim 5 defines a first sidewall of the second dielectric structure in lines 2-3. Claim 7, which depends from claim 5, also defines a first sidewall of the second dielectric structure in lines 2-3. Because the first sidewall of the second dielectric structure has been defined twice, claim 7 is rejected as indefinite.
Regarding claim 8: Line 9 of claim 8 defines “a semiconductor region”, which is followed by line 10, which also defines “a semiconductor region”. Furthermore, claim 8, lines 12-13 refers to “the semiconductor region”. Because the semiconductor region has been defined twice, and because the language is unclear which semiconductor region is being referred to in lines 12-13, claim 8 is rejected as indefinite.
Claims 10-13, 15, 16, and 25 are rejected as indefinite.
Regarding claim 15, which depends from claim 8: As discussed above, claim 8 defines “a semiconductor region” twice. Claim 15 requires that semiconductor region to extend to a top of the substrate. However, claim 15 is unclear which semiconductor region defined in claim 8 that claim 15 is referring to. Because claim 15 is vague on this point, claim 15 is rejected as indefinite.
Claim 16 is rejected for depending from rejected base claim 15.
Regarding claim 16, which depends from claim 15: As discussed above, claim 8 defines “a semiconductor region” twice. Claim 16 requires “the semiconductor region interposing the first isolation feature and the second isolation feature to be free of a transistor”. However, claim 16 is unclear which of the two semiconductor regions defined in claim 8 that claim 16 is referring to. For these reasons, claim 16 is rejected as indefinite.
Regarding claim 25, which depends from claim 8: Claim 8 defines “a first transistor” in line 9. Claim 25 also defines “a first transistor” in lines 1-2. Because claim 25 defines a first transistor for the second time, claim 25 is rejected as indefinite.
Regarding claim 17: Claim 17 has been amended to require the following:
a first semiconductor layer over a semiconductor substrate, the first semiconductor layer has a first upper surface; a first isolation feature over the semiconductor substrate, wherein a first sidewall, a first bottom surface, and a second sidewall opposing the first sidewall of the first semiconductor layer is defined by the first isolation feature, the first bottom surface interfaces the first upper surface of the first semiconductor layer;….
(emphasis added).
This language is confusing because the language associates the first sidewall with the first semiconductor layer, suggesting that the first bottom surface and the second sidewall are also associated with the first semiconductor layer, even though the claim requirements are in the clause defining the first isolation feature. Then, the claim requires the first bottom surface—which is interpreted to be the first bottom surface of the semiconductor layer—interfaces with the first upper surface of the first semiconductor layer. However, the upper surface and bottom surface of the first semiconductor layer should be on opposite sides of the first semiconductor layer, and thus could not interface. Because the language does not make sense, claim 17 is rejected as indefinite.
Claims 18-20 are rejected for depending from rejected base claim 17.
Election/Restrictions
Newly amended claims 17-20 are directed to an invention that is independent or distinct from the invention originally claimed for the following reasons: The original claims were directed to a semiconductor layer with a transistor on a semiconductor substrate and surrounded by a dielectric feature or isolation feature, along with a semiconductor layer with a transistor within a trench on the upper surface of the dielectric feature or isolation feature. Claim 17 is directed to an embodiment, which the Office believes is not supported by the originally filed disclosure, but if it is, the embodiment has the semiconductor layer and transistor in a space underneath the dielectric feature or isolation feature, not in a trench on the upper surface of the dielectric feature or isolation feature.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 17-20 are withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 8, 10, and 25 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Kato, U.S. Pat. Pub. No. 2007/0194383, Figure 3.
Kato, Figure 3:
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Regarding claim 8: Kato Figure 3 discloses a semiconductor structure comprising: a first isolation feature (109, left, middle, in SOI Region; 103, left, right) over a substrate (101), wherein the first isolation feature (109, left, middle, in SOI Region; 103, left, right) includes a first portion (109, left, in SOI Region) having a first upper surface and a second portion (109, middle, in SOI Region) having a second upper surface, wherein the first upper surface and the second upper surface are substantially planar, and wherein the first isolation feature (109, left, middle, in SOI Region; 103, left, right) further comprising a third portion (103, left), contiguous with the first portion (109, left, in SOI Region) and the second portion (109, middle, in SOI Region), wherein the third portion (103, left) is disposed between the first portion (109, left, in SOI Region) and the second portion (109, middle, in SOI Region), and wherein the third portion (103, left) has a third upper surface, wherein the third upper surface is closer the substrate (101) than the first upper surface; a first transistor (120) disposed in a semiconductor region (105, 123, 124) above the third upper surface; a semiconductor region (105, 133, 134) extending from a sidewall of the second portion (109, middle, in SOI Region) of the first isolation feature (109, left, middle, in SOI Region; 103, left, right), over and interfacing a fourth upper surface (at (103, right)) of the first isolation feature (109, left, middle, in SOI Region; 103, left, right) extending from the sidewall, wherein the fourth upper surface is coplanar with the third upper surface, the semiconductor region (105, 133, 134) contiguously extending to a second isolation feature (109, right, SOI Region); the second isolation feature (109, right, SOI Region) having a fifth upper surface coplanar with the first upper surface and a bottommost surface of the second isolation feature (109, right, SOI Region) is coplanar with a bottommost surface of each of the first, second and third portions (109, left, middle, right, in SOI Region; 103, left) of the first isolation feature (109, left, middle, in SOI Region; 103, left, right). Kato specification ¶¶ 76-87.
Regarding claim 10, which depends from claim 8: Kato discloses the first isolation feature (109, left, middle, in SOI Region; 103, left, right) comprises an oxide. Id. ¶¶ 77, 80 (SiO2).
Regarding claim 25, which depends from claim 8: Kato discloses a first source/drain region (123) of a first transistor (120) interfaces the first portion (109, left, in SOI Region) of the first isolation feature (109, left, middle, in SOI Region; 103, left, right) and a second source/drain region (124) of the first transistor (120) interfaces the second portion (109, middle, in SOI Region) of the first isolation feature (109, left, middle, in SOI Region; 103, left, right) and a third source/drain region (134) of a second transistor (130) interfaces the second isolation feature (109, right, in SOI Region).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Section 103 rejections based on Yamada as primary reference
Claims 1, 4, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Yamada, U.S. Pat. Pub. No. 2003/0057487, Figure 2, and further in view of Kato, U.S. Pat. Pub. No. 2007/0194383, Figure 3.
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Yamada Figure 2 (annotated):
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Regarding claim 1: Yamada Figure 2 discloses a semiconductor structure (10), comprising: a semiconductor substrate (21) having a first region (Bulk Device Region) and a second region (SOI Device Region); a first semiconductor layer (26) over the semiconductor substrate (21) in the first region (Bulk Device Region); a first dielectric structure (35a) and a second dielectric structure (35a) in the first region (Bulk Device Region) over the semiconductor substrate (21) and extending through the first semiconductor layer (26) (see Yamada specification ¶¶ 58, 59 (“second isolation may reach through to the silicon base substrate 21 as long as it is substantially as deep as the first isolation 35a…” )), wherein the first dielectric structure (35a) is rectangular-shape in a cross-sectional view; a third dielectric structure (35b, 22) over the semiconductor substrate (21) and located in the second region (SOI Device Region), the third dielectric structure (35b, 22) having an uppermost surface comprising a first upper boundary lower than an upper surface of the first semiconductor layer (26), a second upper boundary coplanar with the upper surface of the first dielectric structure (35a), a third upper boundary coplanar with the first upper boundary, and a fourth upper boundary coplanar with the second upper boundary, the first upper boundary being disposed between the second and third upper boundaries and the fourth upper boundary being between the first and third upper boundaries in the cross-sectional view, wherein each of the first, second, third and fourth upper boundaries are connected to each other to form the uppermost surface of a dielectric material; a second semiconductor layer portion (23, 40b) located over the third dielectric structure (22, 35b) and disposed over and interfacing the first upper boundary and extending between the second upper boundary and the fourth upper boundary; a first transistor (44) over the first semiconductor layer (26) and located in the first region (Bulk Device Region) between the first and second dielectric structure (35a); and a second transistor (45) over the second semiconductor layer portion (23, 40b) and located in the second region (SOI Device Region). Yamada specification ¶¶ 52-59, 68, 69.
Yamada does not disclose that each of the first, second, third and fourth upper boundaries are connected to each other to form the uppermost surface of a single dielectric material. However, this is directed to the process by which the third dielectric structure is made. The process limitation of how a layer is formed has no patentable weight in claims drawn to structure. Note that a product-by-process claim is directed to the product per se, not the process by which the product is made. In re Hirao, 190 USPQ 15 at 17 n. 3 (CCPA 1976). See also In re Brown, 173 USPQ 685, 688 (CCPA 1972); In re Luck, 177 USPQ 523, 525 (CCPA 1973); In re Fessman, 180 USPQ 324, 325-26 (CCPA 1974); In re Avery, 186 USPQ 161, 166-67 (CCPA 1975); In re Wertheim, 191 USPQ 90, 103 (CCPA 1976); and In re Marosi, 218 USPQ 289, 292-93 (Fed. Cir. 1983), all of which make it clear that it is the patentability of the final product per se which must be determined in a product-by-process claim, and not the patentability of the process, and that an old or obvious product by a new method is not patentable as a product, whether claimed in product-by-process claims or not. Note that the applicant has the burden of proof in such cases, according to case law.
To the extent that “a single dielectric material” refers to the type of material instead of a monolithic dielectric material, Kato Figure 3, directed to similar subject matter, discloses a semiconductor structure, comprising: a semiconductor substrate (101) having a first region (Bulk Region) and a second region (SOI Region); a first semiconductor layer (107) over the semiconductor substrate (101) in the first region (Bulk Region); a first dielectric structure (109, left, Bulk Region) and a second dielectric structure (109, right, Bulk Region) in the first region (Bulk Region) over the semiconductor substrate (101) and extending partly through the first semiconductor layer (107), wherein the first dielectric structure (109, left, Bulk Region) is rectangular-shape in a cross-sectional view; a third dielectric structure (109, left, middle, right, in SOI Region; 103) over the semiconductor substrate (101) and located in the second region (SOI Region), the third dielectric structure (109, left, middle, right, in SOI Region; 103) having an uppermost surface comprising a first upper boundary (at 103, left, in SOI Region) lower than an upper surface of the first semiconductor layer (107), a second upper boundary (at 109, left, SOI Region) coplanar with the upper surface of the first dielectric structure (109, left; 109, right, in Bulk Region), a third upper boundary (at 103, right, SOI Region) coplanar with the first upper boundary (at 103, left, SOI Region), and a fourth upper boundary (at 109, middle, SOI Region) coplanar with the second upper boundary (at 109, left, SOI Region), the first upper boundary (at 103, left, SOI Region) being disposed between the second and third upper boundaries (at 109, left, SOI Region; at 103, right, SOI Region) and the fourth upper boundary (at 109, middle, SOI Region) being between the first and third upper boundaries (at 103, left, SOI Region; at 103, right, SOI Region) in the cross-sectional view, wherein each of the first, second, third and fourth upper boundaries are connected to each other to form the uppermost surface of a single dielectric material (SiO2); a second semiconductor layer portion (105, 123, 124) located over the third dielectric structure (109, left, middle, right, in SOI Region; 103) and disposed over and interfacing the first upper boundary (at 103, left, SOI Region) and extending between the second upper boundary (at 109, left, SOI Region) and the fourth upper boundary (at 109, middle, SOI Region); a first transistor (110) over the first semiconductor layer (107) and located in the first region (Bulk Region) between the first and second dielectric structure (109, left; 109; right, in Bulk Region); and a second transistor (120) over the second semiconductor layer portion (105, 123, 124) and located in the second region (SOI Region). Kato specification ¶¶ 76-87. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Yamada to use a single dielectric material, SiO2, because the modification would have involved a selection of a known material based on its suitability for its intended use.
Regarding claim 4, which depends from claim 1: Yamada discloses the first dielectric structure (35a) has an upper boundary substantially level with the upper surface of the first semiconductor layer (26) and the second upper boundary of the third dielectric structure (22, 35b). See Yamada Figure 2; Yamada specification ¶ 55.
Regarding claim 23, which depends from claim 1: Yamada discloses a semiconductor region (portion of semiconductor layer (26); 47) extends from a sidewall of the first dielectric structure (35a) to the third upper boundary of the third dielectric structure (22, 35b). See Yamada Figure 2.
Claims 8, 10, 15, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Yamada, U.S. Pat. Pub. No. 2003/0057487, Figure 2.
Regarding claim 8: Yamada Figure 2 discloses a semiconductor structure (10) comprising: a first isolation feature (22, 35b) over a substrate (21), wherein the first isolation feature (22, 35b) includes a first portion (35b, right) having a first upper surface and a second portion (35b, left) having a second upper surface, wherein the first upper surface and the second upper surface are substantially planar, and wherein the first isolation feature (22, 35b) further comprising a third portion (22), contiguous with the first portion (35b, right) and the second portion (35b, left), wherein the third portion (22) is disposed between the first portion (35b, right) and the second portion (35b, left), and wherein the third portion (22) has a third upper surface, wherein the third upper surface is closer the substrate (21) than the first upper surface; a first transistor (45) disposed in a semiconductor region (23, 40b) above the third upper surface; a semiconductor region (23) extending from a sidewall of the second portion (35b, left) of the first isolation feature (35b, 22), over and interfacing a fourth upper surface of the first isolation feature (22, 35b) extending from the sidewall, wherein the fourth upper surface is coplanar with the third upper surface, the semiconductor region (23) contiguously extending to a second isolation feature (47); the second isolation feature (47) having a fifth upper surface close to being coplanar with the first upper surface and a bottommost surface of the second isolation feature (47) is coplanar with a bottommost surface of each of the first, second and third portions (35b, 22) of the first isolation feature (35b, 22). Yamada specification ¶¶ 52-59. Yamada does not disclose that the fifth upper surface is coplanar with the first upper surface. However, claim 8 is an obvious variant over Yamada because the difference is due to the shape of the upper surface. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also MPEP § 2144.04(IV)(B). Also, this is directed to the process by which the fifth upper surface is formed. The process limitation of how a layer is formed has no patentable weight in claims drawn to structure. Note that a product-by-process claim is directed to the product per se, not the process by which the product is made. In re Hirao, 190 USPQ 15 at 17 n. 3 (CCPA 1976). See also In re Brown, 173 USPQ 685, 688 (CCPA 1972); In re Luck, 177 USPQ 523, 525 (CCPA 1973); In re Fessman, 180 USPQ 324, 325-26 (CCPA 1974); In re Avery, 186 USPQ 161, 166-67 (CCPA 1975); In re Wertheim, 191 USPQ 90, 103 (CCPA 1976); and In re Marosi, 218 USPQ 289, 292-93 (Fed. Cir. 1983), all of which make it clear that it is the patentability of the final product per se which must be determined in a product-by-process claim, and not the patentability of the process, and that an old or obvious product by a new method is not patentable as a product, whether claimed in product-by-process claims or not. Note that the applicant has the burden of proof in such cases, according to case law.
Regarding claim 10, which depends from claim 8: Yamada discloses that the first isolation feature (22, 35b) comprises an oxide. Id. ¶ 52.
Regarding claim 15, which depends from claim 8: Yamada Figure 2 discloses the semiconductor region (23) extends to a top of the substrate (21). Id. ¶ 52.
Regarding claim 16, which depends from claim 15: Yamada Figure 2 discloses the semiconductor region (23) interposing the first isolation feature (35b, 22) and the second isolation feature (47) is free of a transistor. See Yamada Figure 2.
Section 103 rejections based on Nagano as primary reference
Claims 1, 4, 5, 7, 8, 10, 15, 21, 22, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Nagano, U.S. Pat. Pub. No. 2003/0122191, Figure 16, and further in view of Kato, U.S. Pat. Pub. No. 2007/0194383, Figure 3.
Nagano, Figure 16:
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Regarding claim 1: Nagano Figure 16 discloses a semiconductor structure, comprising: a semiconductor substrate (60) having a first region (Silicon region, including up to half way through the middle STI) and a second region (SOI region, from half way through middle STI); a first semiconductor layer (63) over the semiconductor substrate (50) in the first region (Silicon region); a first dielectric structure (STI, left) and a second dielectric structure (left half of middle STI) in the first region (Silicon region) over the semiconductor substrate (60) and extending through the first semiconductor layer (63), wherein the first dielectric structure (STI, left) is rectangular-shape in a cross-sectional view; a third dielectric structure (right half of middle STI, 61, 64) over the semiconductor substrate (60) and located in the second region (SOI region), the third dielectric structure (right half of middle STI, 61, 64) having an uppermost surface comprising a first upper boundary (at 61) lower than an upper surface of the first semiconductor layer (63), a second upper boundary (at right half of middle STI) coplanar with the upper surface of the first dielectric structure (STI, left), and a fourth upper boundary (at 64) coplanar with the second upper boundary (at right half of middle STI), the first upper boundary (at 61) being disposed between the second and fourth upper boundaries (at right half of middle STI, at 64), wherein each of the first, second, and fourth upper boundaries are connected to each other to form the uppermost surface of a dielectric material; a second semiconductor layer portion (62, 65B, 66B) located over the third dielectric structure (right half of middle STI, 61, 64) and disposed over and interfacing the first upper boundary (at 61) and extending between the second upper boundary (at right half of middle STI) and the fourth upper boundary (at 64); a first transistor (TR1) over the first semiconductor layer (63) and located in the first region (Silicon region) between the first and second dielectric structure (STI, left; left half of middle STI); and a second transistor (TR2) over the second semiconductor layer portion (62, 65B, 66B) and located in the second region (SOI region). Nagano specification ¶¶ 130-136.
Nagano is silent as to a third upper boundary coplanar with the first upper boundary, the first upper boundary being disposed between the second and third upper boundaries and the fourth upper boundary being between the first and third upper boundaries in the cross-sectional view, wherein each of the first, second, third and fourth upper boundaries are connected to each other to form the uppermost surface of a single dielectric material.
Kato Figure 3, directed to similar subject matter, discloses a semiconductor structure, comprising: a semiconductor substrate (101) having a first region (Bulk Region) and a second region (SOI Region); a first semiconductor layer (107) over the semiconductor substrate (101) in the first region (Bulk Region); a first dielectric structure (109, left, Bulk Region) and a second dielectric structure (109, right, Bulk Region) in the first region (Bulk Region) over the semiconductor substrate (101) and extending partly through the first semiconductor layer (107), wherein the first dielectric structure (109, left, Bulk Region) is rectangular-shape in a cross-sectional view; a third dielectric structure (109, left, middle, right, in SOI Region; 103) over the semiconductor substrate (101) and located in the second region (SOI Region), the third dielectric structure (109, left, middle, right, in SOI Region; 103) having an uppermost surface comprising a first upper boundary (at 103, left, in SOI Region) lower than an upper surface of the first semiconductor layer (107), a second upper boundary (at 109, left, SOI Region) coplanar with the upper surface of the first dielectric structure (109, left; 109, right, in Bulk Region), a third upper boundary (at 103, right, SOI Region) coplanar with the first upper boundary (at 103, left, SOI Region), and a fourth upper boundary (at 109, middle, SOI Region) coplanar with the second upper boundary (at 109, left, SOI Region), the first upper boundary (at 103, left, SOI Region) being disposed between the second and third upper boundaries (at 109, left, SOI Region; at 103, right, SOI Region) and the fourth upper boundary (at 109, middle, SOI Region) being between the first and third upper boundaries (at 103, left, SOI Region; at 103, right, SOI Region) in the cross-sectional view, wherein each of the first, second, third and fourth upper boundaries are connected to each other to form the uppermost surface of a single dielectric material (SiO2); a second semiconductor layer portion (105, 123, 124) located over the third dielectric structure (109, left, middle, right, in SOI Region; 103) and disposed over and interfacing the first upper boundary (at 103, left, SOI Region) and extending between the second upper boundary (at 109, left, SOI Region) and the fourth upper boundary (at 109, middle, SOI Region); a first transistor (110) over the first semiconductor layer (107) and located in the first region (Bulk Region) between the first and second dielectric structure (109, left; 109; right, in Bulk Region); and a second transistor (120) over the second semiconductor layer portion (105, 123, 124) and located in the second region (SOI Region). Kato specification ¶¶ 76-87. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Nagano to include the Kato third upper boundary because the modification would have involved the substitution of an equivalent known for the same purpose. Furthermore, one having ordinary skill in the art at a time before the effective filing date would be motivated to modify Nagano to use a single dielectric material, SiO2, as in Kato, because the modification would have involved a selection of a known material based on its suitability for its intended use. Lastly, to the extent that the claim is intended to require a monolithic third dielectric structure, this requirement is directed to the process by which the third dielectric structure is made. The process limitation of how a layer is formed has no patentable weight in claims drawn to structure. Note that a product-by-process claim is directed to the product per se, not the process by which the product is made. In re Hirao, 190 USPQ 15 at 17 n. 3 (CCPA 1976). See also In re Brown, 173 USPQ 685, 688 (CCPA 1972); In re Luck, 177 USPQ 523, 525 (CCPA 1973); In re Fessman, 180 USPQ 324, 325-26 (CCPA 1974); In re Avery, 186 USPQ 161, 166-67 (CCPA 1975); In re Wertheim, 191 USPQ 90, 103 (CCPA 1976); and In re Marosi, 218 USPQ 289, 292-93 (Fed. Cir. 1983), all of which make it clear that it is the patentability of the final product per se which must be determined in a product-by-process claim, and not the patentability of the process, and that an old or obvious product by a new method is not patentable as a product, whether claimed in product-by-process claims or not. Note that the applicant has the burden of proof in such cases, according to case law.
Regarding claim 4, which depends from claim 1: Nagano discloses the first dielectric structure (left STI) has an upper boundary substantially level with the upper surface of the first semiconductor layer (63) and the second upper boundary (right half of middle STI) of the third dielectric structure (right half of middle STI, 61, 64). See Nagano Figure 16.
Regarding claim 5, which depends from claim 1: Nagano discloses a first source/drain region (65A) of the first transistor (TR1) interfaces a first sidewall (left sidewall) of the second dielectric structure (left half, middle STI). See id.
Regarding claim 7,1 which depends from claim 5: Nagano discloses a second source/drain region (66A) of the first transistor (TR1) interfaces a first sidewall (left sidewall) of the first dielectric structure (left STI). See Nagano Figure 16; Nagano specification ¶¶ 130-133.
Regarding claim 21, which depends from claim 1: Nagano discloses a source/drain region (65B) of the second transistor (TR2) interfaces a first sidewall of the third dielectric structure (right half of middle STI, 61, 64), wherein the first sidewall extends between the second upper boundary (at right half of middle STI) and the first upper boundary (at 61). See Nagano Figure 16; Nagano specification ¶ 135.
Regarding claim 22, which depends from claim 1: Nagano discloses another source/drain region (66B) of the second transistor (TR2) interfaces a second sidewall of the third dielectric structure (right half of middle STI, 61, 64), wherein the second sidewall extends between the fourth upper boundary (at 64) and the first upper boundary (at 61). See Nagano Figure 16; Nagano specification ¶ 135.
Regarding claim 24, which depends from claim 1: Nagano discloses a bottommost surface of each of the first dielectric structure (STI, left, Silicon region), the second dielectric structure (left half of middle STI, Silicon region) and the third dielectric structure ((right half of middle STI, SOI region) of third dielectric structure (right half of middle STI, 61, 64)) are coplanar in the cross-sectional view. See Nagano Figure 16.
Regarding claim 8: Nagano Figure 16 discloses a semiconductor structure comprising: a first isolation feature (right half of middle STI, 61, 64) over a substrate (60), wherein the first isolation feature (right half of middle STI, 61, 64) includes a first portion (right half of middle STI) having a first upper surface and a second portion (64) having a second upper surface, wherein the first upper surface and the second upper surface are substantially planar, and wherein the first isolation feature (right half of middle STI, 61, 64) further comprising a third portion (61), contiguous with the first portion (right half of middle STI) and the second portion (64), wherein the third portion (61) is disposed between the first portion (right half of middle STI) and the second portion (64), and wherein the third portion (61) has a third upper surface, wherein the third upper surface is closer the substrate (60) than the first upper surface; a first transistor (TR2) disposed in a semiconductor region (62, 65B, 66B) above the third upper surface. Nagano specification ¶¶ 130-136. Nagano does not disclose a semiconductor region extending from a sidewall of the second portion of the first isolation feature, over and interfacing a fourth upper surface of the first isolation feature extending from the sidewall, wherein the fourth upper surface is coplanar with the third upper surface, the semiconductor region contiguously extending to a second isolation feature; the second isolation feature having a fifth upper surface coplanar with the first upper surface and a bottommost surface of the second isolation feature is coplanar with a bottommost surface of each of the first, second and third portions of the first isolation feature.
As discussed in the Section 102 rejection of claim 8 in view of Kato, which is incorporated by reference, Kato, directed to similar subject matter, discloses a first transistor (120) disposed in a semiconductor region (105, 123, 124) above the third upper surface; a semiconductor region (105, 133, 134) extending from a sidewall of the second portion (109, middle, in SOI Region) of the first isolation feature (109, left, middle, in SOI Region; 103, left, right), over and interfacing a fourth upper surface (at (103, right) of the first isolation feature (109, left, middle, in SOI Region; 103, left, right) extending from the sidewall, wherein the fourth upper surface is coplanar with the third upper surface, the semiconductor region (105, 133, 134) contiguously extending to a second isolation feature (109, right, SOI Region); the second isolation feature (109, right, SOI Region) having a fifth upper surface coplanar with the first upper surface and a bottommost surface of the second isolation feature (109, right, SOI Region) is coplanar with a bottommost surface of each of the first, second and third portions (109, left, middle, right, in SOI Region; 103, left) of the first isolation feature (109, left, middle, in SOI Region; 103, left, right). Kato specification ¶¶ 76-87. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Nagano to include the Kato additional isolation features and the semiconductor region because the modification would have involved the substitution of an equivalent known for the same purpose.
Regarding claim 10, which depends from claim 8: Nagano discloses the first isolation feature (middle STI, 61, 64) comprises an oxide. Id. ¶¶ 131, 133.
Regarding claim 15, which depends from claim 8: Nagano discloses the semiconductor region (63) extends to a top of the substrate (60). Id. ¶¶ 131, 132.
Further Section 103 rejections based on Kato, Nagano, and/or Yamada as primary references
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Kato, or Nagano and Kato, and further in view of Augendre, U.S. Pat. Pub. No. 2022/0148908, Figure 10.
Augendre, Figure 10:
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Regarding claim 12, which depends from claim 8: Nagano and Kato are silent as to whether the first isolation feature is deposed in an RF device region of the substrate. Kato, and Nagano in view of Kato, disclose that the first isolation feature is in an SOI region of the substrate. Kato specification ¶¶ 77, 79-81; Nagano specification ¶¶ 130-136.
Augendre Figure 10, which incorporates features of an RF device discussed in Figures 2-9, in Region A, discloses Region A is an SOI region and is separated by STI trenches from Region B, which is a logic region. See Augendre specification ¶¶ 117-122; 81-116; 1-6 (directed to RF devices). One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Kato, or Nagano in view of Kato, to include an RF device in the isolation feature because the modification would have involved the substitution of an equivalent known for the same purpose.
Regarding claim 13, which depends from claim 8: Kato and Nagano are silent as to whether the first transistor is an RF device. Kato, and Nagano in view of Kato, disclose that the first isolation feature is in an SOI region of the substrate. Kato specification ¶¶ 77, 79-81; Nagano specification ¶¶ 130-136.
Augendre Figure 10, which incorporates features of an RF transistor discussed in Figures 2-9, in Region A, discloses Region A is an SOI region with the RF transistor and is separated by STI trenches from Region B, which is a logic region. See Augendre specification ¶¶ 117-122; 81-116; 1-6 (directed to RF devices). One having ordinary skill in the art at a time before the effective filing date would be motivated to replace the first transistor in Kato, or Nagano in view of Kato, with an RF transistor because the modification would have involved the substitution of an equivalent known for the same purpose.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Kato, Yamada in view of Kato, or Nagano in view of Kato, and further in view of Wiatr, U.S. Pat. Pub. No. 2009/0111223.
Wiatr Figure 2g:
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Regarding claim 11, which depends from claim 8: Kato, Yamada in view of Kato, and Nagano in view of Kato, are silent as to an interlayer dielectric (ILD) on the first upper surface of the first isolation feature.
Wiatr Figure 2g, directed to similar subject matter, discloses an interlayer dielectric (ILD) (240) on the first upper surface of the first isolation feature (221, 204). Wiatr specification ¶¶ 40, 41. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Kato, Yamada in view of Kato, or Nagano in view of Kato, to incorporate the interlayer dielectric on the first upper surface of the isolation feature because the modification would permit the deposition of contacts (226) to make electrical contact with the first transistor. Id.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Victoria K. Hall/Primary Examiner, Art Unit 2897
1 See discussion in Section 112(a) rejection regarding claim 7’s interpretation.