Detailed Action
This office action is in response to the amendment filed on March 9th, 2026. Claims 1-2, 4-6, 8-14, 16-18, 20-22, and 24-25 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed March 9th, 2026, have been fully considered but they are not persuasive.
Applicant argues (pgs. 7-11, “Remarks”) that Aggarwal and the other cited references fail to teach the limitations presented in amended Claims 1, 9, and 16.
However, as seen below, Claim 1 is now rejected by the combination of Aggarwal, Jiang, and Chang. Claim 9 is now rejected by the combination of Rizzolo, Jiang, and Chang. Claim 16 is now rejected by the combination and new interpretation of Wang, Jiang, and Rizzolo
Therefore, applicant’s arguments are not persuasive and are moot view of the new grounds of rejection.
Applicant’s amendments have overcome the 35 U.S.C. 112(a) rejections of the previous office action.
Claim Objections
Claim 13 is objected to because of the following informalities:
The claim recites the limitation “barrier layer a third via hole” in line 2. The limitation will be interpreted as “barrier layer in a third via hole”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 13 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 recites the limitation "the depositing another barrier layer" in line 13. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the limitation will be interpreted as “depositing another barrier layer”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate that the corresponding limitations are addressed with a secondary reference/embodiment in an obviousness analysis.
Claims 1, 4-6, 8, and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Aggarwal et al. (2021/0083174 A1; hereinafter Aggarwal) in view of Jiang et al. (2016/0351792 A1; hereinafter Jiang) and of Chang et al. (2019/0067559 A1; hereinafter Chang).
Regarding Claim 1, Aggarwal (figs. 4A-I) teaches a method, comprising:
forming a first via hole ([0041], trench where 152 are formed in layer VX, see fig. 4B) in a first dielectric layer ([0041], 300, 310 formed in layer VX, see fig. 4A);
forming a first barrier layer ([0041], 320 formed in layer VX) in the first via hole (see fig. 4B);
forming a first conductive layer ([0041], 152 formed in layer VX, see fig. 4B) over the first barrier layer (320 in VX) and in the first via hole (see fig. 4B);
depositing a magnetic tunnel junction (MTJ) stack ([0042], 240’, 250’, 260’, see fig. 4C) over the first conductive layer (152 in VX), the first barrier layer (320 in VX), and the first dielectric layer (300, 310 in VX), wherein the MTJ stack (210) is electrically connected (see fig. 4C) to the first conductive layer (152 in VX);
providing a hard mask layer ([0043], 265’, see fig. 4C) on the MTJ stack (210);
patterning ([0043]-[0044], see figs. 4C-D) the MTJ stack (240’, 250’, 260’) and hard mask layer (265’ becomes 265, see fig. 4D), resulting in a patterned MTJ stack ([0044], 210);
depositing a dielectric spacer ([0044], 350, see fig. 4D) over sidewalls of the patterned MTJ stack (210) and the hard mask layer (265);
depositing a protective spacer over the dielectric spacer, wherein the protective spacer comprises a first magnetic material and extends laterally adjacent to the hard mask layer providing a direct contact between the protective spacer and a sidewall of the hard mask layer in a cross-sectional view;
depositing a second dielectric layer ([0047], 300 formed over layer VX and 210, see fig. 4E) over the patterned MTJ stack (210) and the hard mask layer (265);
performing a planarization process ([0048], see fig. 4G) to provide a planar surface (topmost surface of layer MX+1, see fig. 4G) of the hard mask layer (265), the protective spacer, and the second dielectric layer (300 formed over VX and in MX+1, see fig. 4G):
forming a second via hole ([0049], 152’, 154’ formed in VX+1 and MX+2, see fig. 4H) in a third dielectric layer ([0049], 300, 310 formed in VX+1 and MX+2, see fig. 4H) disposed over the second dielectric layer (300 in MX+1);
forming a second barrier layer ([0050], 320 formed in VX+1 and MX+2, see annotated fig. 4I) in the second via hole (152’, 154’) and on the hard mask layer (265); and
forming a second conductive layer ([0050], 152, 154 formed in VX+1 and MX+2, see fig. 4I) over the second barrier layer (320 in VX+1 and MX+2) and in the second via hole (152’, 154’), wherein the second conductive layer (152, 154 formed in VX+1 and MX+2) is electrically connected (see fig. 4I) to the patterned MTJ stack (210), wherein
at least one of the first barrier layer (320 in VX), the first conductive layer (152 in VX), the second barrier layer (320 in VX+1 and MX+2), and the second conductive layer (152, 154 in VX+1 and MX+2) includes a second magnetic material ([0036], 320 may be cobalt).
Aggarwal doesn’t teach depositing a protective spacer over the dielectric spacer, wherein the protective spacer comprises a first magnetic material and extends laterally adjacent to the hard mask layer providing a direct contact between the protective spacer and a sidewall of the hard mask layer in a cross-sectional view.
However, Chang (fig. 14) teaches depositing a protective spacer ([0018], 118) over the dielectric spacer ([0021], 132), wherein the protective spacer (118) comprises a first magnetic material ([0018], silicon nitride) and extends laterally adjacent (118 extends laterally above hard mask 814) to the hard mask layer ([0040], 814) providing a direct contact (118 directly contacts the top of the sidewalls of 814) between the protective spacer (118) and a sidewall of the hard mask layer (814) in a cross-sectional view. Chang also teaches that the protective layer may act as an etch stop ([0046]) and therefore protects layers underneath during subsequent etching.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Aggarwal to include the protective spacer of Chang to protect the device from subsequent etching.
Chang doesn’t teach the protective spacer comprises a first magnetic material.
However, Jiang (fig. 5b) teaches the protective spacer ([0095], 595) comprises a first magnetic material ([0045]). Jiang also teaches that this material protects the MTJ from external and local magnetic fields ([0045]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Aggarwal and Chang to include the material of Jiang to protect the MTJ from magnetic fields.
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Annotated Figure 4I
Regarding Claim 4, Aggarwal (figs. 4A-I) teaches the method of claim 1, wherein prior to depositing the second dielectric layer (300 over VX and in MX+1, see fig. 4D) over the patterned MTJ stack (210) forming a metal via ([0040], 152 formed in VX-1, see fig. 4A) and a metal line ([0040], 154 formed in MX, see fig. 4A) in a logic region ([0039], 110) of a substrate ([0040], 300 below M1, see fig. 3), wherein the patterned MTJ stack (210) is disposed in a memory region ([0039], 120) of the substrate (300 below M1).
Regarding Claim 5, Aggarwal (figs. 4A-I) teaches the method of claim 4, wherein the depositing the second dielectric layer (300 over VX and in MX+1) includes depositing the second dielectric layer (300 over VX and in MX+1) over (see fig. 4D) the metal via (152 in VX-1) and the metal line (154 in MX) in the logic region (110).
Regarding Claim 6, Aggarwal (figs. 4A-I) teaches the method of claim 5 further comprising: forming a third via hole ([0048], 154’ over VX, see fig. 4F) in the second dielectric layer (300 over VX and in MX+1) in the logic region (110); forming the second barrier layer ([0048], 320 in MX+1, see fig. 4G) in the third via hole (154’ over VX); and forming the second conductive layer ([0048], 154 in MX+1, see fig. 4g) over the second barrier layer (320 in MX+1) in the third via hole (154’ over VX).
Regarding Claim 8, Chang (fig. 14) teaches the method of claim 1, wherein the depositing the protective spacer (118) includes depositing the protective spacer (118) along a sidewall (118 is deposited along the sidewall of 814 through 132)) of the hard mask layer (814).
Regarding Claim 21, the combination of Aggarwal (figs. 4A-I) and Chang (fig. 14) teaches the method of claim 1, wherein the depositing the second barrier layer (Aggarwal, 320 in VX+1 and MX+2, see annotated fig. 4I) includes providing the second barrier layer laterally adjacent (Aggarwal, 320 is formed laterally adjacent to 210 and 350) to the protective spacer (Chang, 118) along a horizontal plane (Aggarwal, 320 is formed on the horizontal plane above 210 and 350).
Regarding Claim 22, Aggarwal (figs. 4A-I) teaches the method of claim 21, wherein the second barrier layer (320 in VX+1 and MX+2) is the second magnetic material ([0036], 320 may be cobalt).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Aggarwal, Chang, and Jiang as applied to Claim 1 above, and further in view of Dutta et al. (10707413 B1; hereinafter Dutta).
Regarding Claim 2, Aggarwal (figs. 4A-I) teaches the method of claim 1, wherein the first magnetic material and the second magnetic material each include Co ([0036]). Jiang does teach that the first magnetic material may be Ni, Fe, NiFe and that other suitable materials may also be useful ([0045]).
Dutta teaches that cobalt and iron are equivalent magnetic materials (Col. 8, Lines 22-23). One of ordinary skill in the art could have substituted the cobalt of Dutta for the iron of Jiang as they are equivalent magnetic materials.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the cobalt of Dutta for the iron of Jiang, since simple substitution of magnetic materials for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Claims 9-13 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Rizzolo et al. (2020/0127194 A1; hereinafter Rizzolo) in view of Jiang and Chang.
Regarding Claim 9, Rizzolo (figs. 11-14) teaches a method, comprising:
forming a bottom electrode ([0041], 540, 542) over a substrate ([0041], layer containing 510, 520) wherein the forming the bottom electrode (540, 542) includes:
depositing a first barrier layer (540) in a first via hole (hole where 540, 542 are formed); and
depositing a first conductive layer (542) over the first barrier layer (540) and in the first via hole (hole where 540, 542 are formed);
forming a magnetic tunnel junction (MTJ) stack ([0042], 550A, 552A, 554A) over the first conductive layer (542);
depositing a protective spacer ([0043], 546, see fig. 12) over sidewalls of the MTJ stack (550A, 552A, 554A) wherein the protective spacer includes magnetic material;
forming an upper electrode ([0045], 564, 562, see fig. 14) over the MTJ stack (550A), wherein the forming the upper electrode (564, 562) includes:
forming a second via hole ([0044], hole 555 where 564, 562 are formed, see fig. 13) having sidewalls directly defined by the protective spacer (546) and a bottom surface (bottom of 555) defined by an upper surface of the MTJ stack (upper surface of 554A, see fig. 13);
depositing a second barrier layer (562) in the second via hole (555) along the sidewalls and the bottom surface of the second via hole (555), wherein the second barrier layer (562) includes magnetic material ([0046], may be cobalt); and
forming a second conductive layer (564) over the second barrier layer (562) and in the second via hole (555).
Rizzolo doesn’t teach that the protective spacer includes a magnetic material.
However, Jiang (fig. 5b) teaches the protective spacer ([0095], 595) comprises a first magnetic material ([0045]). Jiang also teaches that this material protects the MTJ from external and local magnetic fields ([0045]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Rizzolo to include the protective spacer of Jiang to protect the MTJ from magnetic fields.
Rizzolo doesn’t teach forming a second via hole having sidewalls directly defined by the protective spacer.
However, Chang (fig. 14) teaches forming a second via hole ([0048]) having sidewalls directly defined by the protective spacer ([0018], 118). One of ordinary skill in the art could have substituted the formation of the second via hole of Chang for the formation of the second via hole of Rizzolo and yielded the predictable results of forming a via that etches through a hard mask to reach an MTJ for subsequent electrode contact.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the formation of the second via hole of Chang for the formation of the second via hole of Rizzolo, since simple substitution of via hole formation for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Regarding Claim 10, Rizzolo (figs. 11-14) teaches the method of claim 9, further comprising: forming a dielectric spacer ([0043], 538, see fig. 12) on the sidewalls of the MTJ stack (550A, 552A, 554A) prior to ([0043], 546 is formed around 538; see figs. 6-7 and similar features 446 and 438) depositing the protective spacer (546) conformally along the dielectric spacer (538).
Regarding Claim 11, Rizzolo (figs. 11-14) teaches the method of claim 10, further comprising: forming another dielectric spacer ([0043], 560) over the protective spacer (546).
Regarding Claim 12, Rizzolo (figs. 11-14) teaches the method of claim 10, wherein the second via hole (555) sidewalls are defined entirely (sidewalls of 555 are defined by 538 which is defined entirely by 546, see fig. 13) by the protective spacer (546), and wherein the depositing the second barrier layer (562) provides the second barrier layer (562) directly physically interfacing the protective spacer (546, see fig. 14).
Regarding Claim 13, Rizzolo doesn’t teaches the method of claim 9, wherein the depositing another barrier layer a third via hole in a logic region of the substrate.
However, Chang (annotated fig. 2) teaches the depositing another barrier layer ([0031], 214) a third via hole (third via hole, see annotated fig. 2) in a logic region ([0029], 204) of the substrate ([0030], 208). Chang also teaches this another barrier layer is a diffusion barrier for additional wires needed to form conductive paths ([0031]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Rizzolo to include the another barrier layer of Chang to provide a diffusion barrier to the additional wires needed for conductive pathing.
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Annotated Figure 2
Regarding Claim 25, Rizzolo (figs. 11-14) teaches the method of claim 9, wherein the depositing the second barrier layer (562) in the second via hole (hole 555 where 564, 562 are formed) formings a direct interface (562 directly contacts a top surface of 546) between the second barrier layer (562) and the protective spacer (546).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Rizzolo, Jiang, and Chang as applied to Claim 9 above, and further in view of Wang et al. (CN 114335068 A; hereinafter Wang).
Regarding Claim 14, Rizzolo doesn’t teach the method of claim 9, further comprising: forming a third via hole, and wherein the third via hole extends from the MTJ stack to another MTJ stack.
However, Wang (fig. 6) teaches: forming a third via hole ([0059]-[0060], hole where 72 is formed, 72 may include a barrier layer that is not shown in the figures), and wherein the third via hole (hole where 72 is formed) extends from the MTJ stack ([0054], 52) to another MTJ stack ([0054], 54). One of ordinary skill in the art would have found it obvious to try and interconnect multiple MTJ stacks and yielded the predictable results of forming a functional memory device.
Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to interconnect multiple MTJ stacks since this limitation is one of a finite number of identified, predictable potential solutions. This is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Claims 16-18, 20, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Jiang and Rizzolo.
Regarding Claim 16, Wang (fig. 6) teaches a method of semiconductor device fabrication ([0049], MRAM cell), the method comprising:
forming a first electrode ([0052], left 32) and a second electrode (right 32) over a substrate ([0049], 12);
forming a first magnetic tunneling junction (MTJ) element ([0054], 52, 50 over 52) over the first electrode (left 32) and a second MTJ element ([0054], 54, 50 over 54) over the second electrode (right 32);
forming a sidewall spacer ([0055], 56) abutting the first MTJ element (52, 50) and the second MTJ element (54, 50), wherein the sidewall spacer (56) contiguously extends (see fig. 6) from a sidewall of the first MTJ element (52, 50) to a sidewall of the second MTJ element (54, 50) wherein the sidewall spacer includes a magnetic material;
forming a via hole ([0061], hole where 72 is formed), wherein the via hole includes a first portion (portion where left 80 is formed) exposing an upper surface of the first MTJ element (upper surface of 50 over 52) and having sidewalls defined by the sidewall spacer and a second portion (portion where right 80 is formed) exposing an upper surface of the second MTJ element (upper surface of 50 over 54) wherein the forming the via hole exposes the sidewall spacer to directly define an edge of each of the first portion and the second portion; and
forming a second electrode ([0061], 72) contacting the exposed upper surface of the first MTJ element (upper surface of 50 over 52 in contact with 72) and the second MTJ element (upper surface of 50 over 54 in contact with 72), wherein the forming the second electrode (72) includes
depositing at least one magnetic material ([0061], barrier material) along sidewalls defined by the sidewall spacer to directly contact the sidewall spacer and
depositing the at least one magnetic material (barrier material) along a bottom of the via hole (hole where 72 is formed) defined by the first MTJ element (52, 50) and the second MTJ element (54, 50).
Wang doesn’t teach the sidewall spacer includes a magnetic material.
However, Jiang (fig. 5b) teaches the sidewall spacer ([0095], 182, 595) comprises a first magnetic material ([0045]). Jiang also teaches that this material protects the MTJ from external and local magnetic fields ([0045]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Wang to include the sidewall spacer of Jiang to protect the MTJ from magnetic fields.
Wang doesn’t teach the via hole includes a first portion having sidewalls defined by the sidewall spacer and wherein the forming the via hole exposes the sidewall spacer to directly define an edge of each of the first portion and the second portion.
However, Rizzolo (fig. 13) teaches the via hole ([0044]-[0045], 555, 1302) includes a first portion (555, 1302) having sidewalls (sidewalls of 555) defined by the sidewall spacer ([0043], 538, 546) and wherein the forming the via hole (555, 1302) exposes the sidewall spacer (538, 546) to directly define an edge (bottom edge of 1302) of each of the first portion (555, 1302) and the second portion. Rizzolo also teaches this recessed portion allows the top contact to be self-aligned to the via hole ([0045]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Wang to include the via hole formation of Rizzolo to allow for a self-aligned top contact. Furthermore, the via hole formation of Rizzolo would be applied to the second portion of Wang, and thus the combination of Wang and Rizzolo also teaches the sidewall spacer defines an edge of the second portion.
Wang doesn’t teach forming the second electrode includes depositing at least one magnetic material along sidewalls defined by the sidewall spacer to directly contact the sidewall spacer.
However, Rizzolo (fig. 14) teaches forming the second electrode ([0045], 562, 564) includes depositing at least one magnetic material ([0046], 562 may be cobalt) along sidewalls defined by the sidewall spacer ([0043], 538, 546) to directly contact the sidewall spacer (562 directly contacts a top surface of 538, 546). One of ordinary skill in the art would have found it obvious to try and use cobalt as a barrier material and yielded the predictable results of a functioning contact.
Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to use cobalt as a barrier material since this limitation is one of a finite number of identified, predictable potential solutions. This is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Regarding Claim 17, Rizzolo (fig. 14) teaches the method of claim 16, wherein the forming the second electrode (562, 564) includes depositing a barrier layer (562) of the magnetic material including at least one of cobalt ([0046]), iron, or nickel.
Regarding Claim 18, Jiang (fig. 5b) teaches the method of claim 16, wherein the forming the sidewall spacer (182, 595) includes depositing a protection layer (595) of the magnetic material ([0045]) over a first dielectric spacer (182), the first dielectric spacer (182) being covered with the protection layer (595).
Regarding Claim 20, Rizzolo (fig. 14) teaches the method of claim 16, wherein the depositing the magnetic material (cobalt in 562) deposits the magnetic material directly on the MTJ element ([0042], 550A, 552A, 554A).
Regarding Claim 24, Wang (fig. 6) teaches the method of claim 16, further comprising: providing another dielectric layer ([0061], 58) over the sidewall spacer (56), wherein the another dielectric layer (58) fills a space (see fig. 6) between the sidewall spacer (56) on the first MTJ element (52, 50) and the sidewall spacer (56) on the second MTJ element (54, 50).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.H./
Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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