Prosecution Insights
Last updated: July 17, 2026
Application No. 18/446,656

MOUNTING STRUCTURES FOR EDGE-EMITTING SEMICONDUCTOR DEVICES

Non-Final OA §103
Filed
Aug 09, 2023
Examiner
IQBAL, HAMNA FATHIMA
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
CreeLED Inc.
OA Round
1 (Non-Final)
80%
Grant Probability
Favorable
1-2
OA Rounds
3m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allowance Rate
12 granted / 15 resolved
+12.0% vs TC avg
Strong +25% interview lift
Without
With
+25.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
38 currently pending
Career history
57
Total Applications
across all art units

Statute-Specific Performance

§103
95.9%
+55.9% vs TC avg
§102
1.2%
-38.8% vs TC avg
§112
2.9%
-37.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 15 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statements (IDS) submitted on 10/19/2023 and 05/26/2026 are being considered by the examiner. Election/Restrictions Applicant's election with traverse of Species II and Sub-Species VI in the reply filed on 06/03/2026 is acknowledged. The traversal is on the grounds that: The Election/Restriction Requirement fails to show or allege the existence of Species/Sub-Species that are both independent and distinct. The differences between Species/Sub-species would not cause a search/examination burden and a search for one of the Species/Sub-species would likely result in finding art pertinent to the other Species/Sub-species. The first argument is not persuasive. According to MPEP § 802.02, “Restriction is the practice of requiring an applicant to elect a single claimed invention (e.g., a combination or sub-combination invention, a product or process invention, a species within a genus) for examination when two or more independent inventions and/or two or more distinct inventions are claimed in an application” (emphasis added). However, the second argument is persuasive. Therefore, the restriction requirement is withdrawn and all Claims are examined. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Rejection note: Italicized claim limitations are limitations not explicitly disclosed in the primary reference but disclosed in the secondary reference(s). Claims 1-5, 7, 9, 10, 15-17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (CN 114388483 A) in view of Miller et al. (US 20100032703 A1). Regarding Claim 1, Liu et al. teaches a light-emitting diode (LED) device comprising: an edge-emitting LED chip 106 (Fig. 1: 106, page 4, lines 22-25 in English Translation of Liu et al.) comprising: an n-type layer, an active layer, and a p-type layer; and a first edge and an opposing second edge, the active layer extending lengthwise between the first edge and the second edge; and a submount 100 with a recess 104 (Fig. 1: 100, 104, page 4, lines 15-25 in English Translation of Liu et al.), the edge-emitting LED chip 106 residing at least partially within the recess 104 such that the edge-emitting LED chip 106 is mechanically supported and electrically coupled to the submount 100 within the recess 104 (Fig. 1: 100, 104, 106, page 4, lines 15-25 in English Translation of Liu et al.). Note that LED chip 106 are electrically coupled to the submount 100 via the contacts 1054, 1055 and the connecting black portions 1052, 1053 (see Fig. 1: 1052, 1053, 1054, 1055, page 6, lines 18-40 in English Translation of Liu et al.) Miller et al. teaches a light-emitting diode (LED) device comprising the following limitations not disclosed in Liu et al.: an edge-emitting LED chip 100 comprising: an n-type layer 135, an active layer 120, and a p-type layer 110 (Fig. 1: 110, 120, 135, paragraph 0018, 0019); and a first edge 145 and an opposing second edge (opposite to 145) (Fig. 1: 145, paragraph 0021), the active layer 120 extending lengthwise between the first edge 145 and the second edge (opposite to 145) (see Fig. 1: 145); Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of Liu et al. and Miller et al. in order to have an edge-emitting LED chip in the submount of Liu et al. comprising an n-type layer, an active layer, and a p-type layer, and a first edge and an opposing second edge, the active layer extending lengthwise between the first edge and the second edge. By doing so, the edge-emitting LED chip can improve light extraction in the recess by directing more of the generated light into the desired optical path while having a n-type layer, an active layer, and a p-type layer can enable efficient electron-hole recombination for high light generation. Regarding Claim 2, the combination of Liu et al. and teaches the LED device of claim 1, wherein: the edge-emitting LED chip 100 further comprises an n-contact 140 on the n-type layer 135 and a p- contact 105 on the p-type layer 110 (as taught by Miller et al., see Fig. 1: 140, 105, 110, 135, paragraph 0021); and the n-contact and the p-contact are electrically coupled to the submount 100 within the recess 104. Note that in Liu et al., the contacts 1054, 1055 are electrically coupled to the submount 100 via the connecting black portions 1052, 1053 (see Fig. 1: 1052, 1053, 1054, 1055, page 6, lines 18-40 in English Translation of Liu et al.). Therefore, a person of ordinary skill in the art would have recognized that when the edge-emitting LED chip of Miller et al. is disposed in the LED device of Liu et al., the n-contact and the p-contact of Miller et al. can similarly be electrically coupled to the submount 100 within the recess 104 of Liu et al. Regarding Claim 3, the combination of Liu et al. and teaches the LED device of claim 2, further comprising a first electrical connection 1052 and a second electrical connection 1053 on sidewalls of the recess 104, wherein the p-contact is electrically coupled to the first electrical connection and the n-contact is electrically coupled to the second electrical connection (see Liu et al., Fig. 1: 1052, 1053, 1054, 1055, page 6, lines 18-40 in English Translation of Liu et al.). Note that in Liu et al., the contacts 1054, 1055 are electrically coupled to the first electrical connection and second electrical connections 1052, 1053 on sidewalls of the recess 104 (see Fig. 1: 1052, 1053, 1054, 1055, page 6, lines 18-40 in English Translation of Liu et al.). Therefore, a person of ordinary skill in the art would have recognized that when the edge-emitting LED chip of Miller et al. is disposed in the LED device of Liu et al., the n-contact and the p-contact of Miller et al. can similarly be electrically coupled to the first electrical connection and the second electrical connection respectively of Liu et al. Regarding Claim 4, Liu et al. and teaches the LED device of claim 3, wherein portions 107 of the first electrical connection 1052 and portions 108 of the second electrical connection 1053 extend on a top surface of the submount 100 and away from the recess 104 to form contact pads (see Fig. 1: 1052, 1053, 1054, 1055, page 6, lines 18-40 in English Translation of Liu et al.). Note that the electrodes pads 107, 108 are coupled to the electrical connections 1052, 1053 in Fig. 1 and are therefore interpreted together as the first and second electrical connections. Regarding Claim 5, Liu et al. teaches the LED device of claim 3, further comprising vias (vias on the left of the circuit layer 102 of Fig. 1) that provide electrically conductive paths for the first electrical connection 1052 and the second electrical connection 1053 to a bottom surface of the submount 100 (see Fig. 1: 102, 1052, 1053, page 8, lines 33-36 in English Translation of Liu et al.). Regarding Claim 7, Liu et al. teaches the LED device of claim 1, wherein the second edge is spaced from a floor of the recess 104 (see Fig. 1). Note that the bottom edge of the LED 106 is spaced apart from a floor of the recess 104 in Fig. 1. Regarding Claim 9, Liu et al. teaches the LED device of claim 7, further comprising a reflective material 105 between the second edge (bottom edge of LED chip 106) and the floor of the recess 104 (see Fig. 1: 105, 106, 104, page 4, lines 21-25 in English Translation of Liu et al.. Regarding Claim 10, Liu et al. teaches the LED device of claim 7, wherein the floor of the recess 104 is curved (see Fig. 1: 104). Regarding Claim 15, Liu et al. teaches a light-emitting diode (LED) device comprising: a submount 100 comprising a top surface, a first recess 104 that extends into the submount 100 from the top surface, and a second recess 104 that extends into the submount 100 from the top surface (Fig. 8: 100, 104, page 4, lines 15-25 in English Translation of Liu et al.); a first edge-emitting LED chip 1063 at least partially within the first recess 104 (Fig. 8: 1063, 104, page 10, lines 8-13); and a second edge-emitting LED chip 1064 at least partially within the second recess 104 (Fig. 8: 1063, 104, page 10, lines 8-13). While Liu et al. fails to explicitly teach the LED chips 1063, 1064 are edge-emitting LED chips, Miller et al. teaches a light-emitting diode (LED) device comprising an edge-emitting LED chip 100 (Fig. 1: 100, paragraph 0018). Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of Liu et al. and Miller et al. in order to have edge-emitting LED chips in the submount of Liu et al. By doing so, the edge-emitting LED chips can improve light extraction in the recess by directing more of the generated light into the desired optical path. Regarding Claim 16, Liu et al. teaches the LED device of claim 15, wherein the first edge-emitting LED chip 1063 is mechanically supported and electrically coupled to the submount 100 within the first recess 104, and the second edge-emitting LED chip 1064 is mechanically supported and electrically coupled to the submount 100 within the second recess 104 (see Fig. 8: 1052, 1053, 1054, 1055, 1063, 1064, page 6, lines 18-40 in English Translation of Liu et al.). Note that LED chip 1063, 1064 are electrically coupled to the submount 100 via the contacts 1054, 1055 and the connecting black portions 1052, 1053 (see Fig. 8: 1052, 1053, 1054, 1055, 1063, 1064, page 6, lines 18-14 in English Translation of Liu et al.). Regarding Claim 17, Liu et al. teaches the LED device of claim 15, wherein the first recess 104 comprises a different lateral width than the second recess 104 (i.e., width of first recess = 2R1 and width of second recess = 2R2) (see Fig. 8: R1, R2, page 10, lines 11-13 in English Translation of Liu et al.). Regarding Claim 19, Liu et al. teaches the LED device of claim 15, wherein the submount comprises material that is transparent to light from the first edge-emitting LED chip 1063 and the second edge-emitting LED chip 1064. Note that according to page 10, lines 9-10 in English Translation of Liu et al., the LED chips 1063, 1064 emit visible light and according to page 13, lines 8-9 in English Translation of Liu et al., the submount is made of glass, which is a well-known transparent material to visible light. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (CN 114388483 A) in view of Miller et al. (US 20100032703 A1), as applied to Claim 1 above, further in view of Park et al. (US 20120153334 A1). Regarding Claim 6, Liu et al. fails to explicitly teach the LED device of claim 1, wherein the second edge is in contact with a floor of the recess. However, Park et al. teaches a LED device, wherein the second edge (bottom edge of the LED chip 10) is in contact with a floor of the recess 31 (see Fig. 1: 10, 31, paragraph 0040). Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of Liu et al., Miller et al. and Park et al. in order to have the second edge in contact with a floor of the recess. Doing so would improve heat dissipation through the submount. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (CN 114388483 A) in view of Miller et al. (US 20100032703 A1), as applied to Claim 7 above, further in view of Park et al. (US 20120153334 A1). Regarding Claim 8, Liu et al. fails to teach the LED device of claim 7, wherein sidewalls of the recess are angled such that the floor of the recess has a smaller lateral dimension than a lateral dimension of the recess at a top surface of the submount. However, Park et al. teaches a LED device, wherein sidewalls of the recess 31 are angled such that the floor of the recess 31 has a smaller lateral dimension than a lateral dimension of the recess 31 at a top surface of the submount 30 (Fig. 1, Fig. 3A: 30, 31, paragraph 0040, 0041). Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of Liu et al., Miller et al. and Park et al. in order to have sidewalls of the recess angled such that the floor of the recess has a smaller lateral dimension than a lateral dimension of the recess at a top surface of the submount. Doing so would diffuse and evenly emit the light generated from the LED chip, as recognized by Park et al. (paragraph 0041). Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Pang et al. (US 20200176643 A1) in view of Miller et al. (US 20100032703 A1). Regarding Claim 11, Pang et al. teaches a light-emitting diode (LED) device comprising: a plurality of edge-emitting LED chips 44 (Fig. 5: 44, paragraph 0107), each edge-emitting LED chip 44 comprising: an n-type layer, an active layer, and a p-type layer (not shown in Figures, see paragraph 0098, 0099); and a first edge (edge closer to base of recess 42 in Fig. 5) and an opposing second edge (edge away from the base of recess 42 in Fig. 5) , the active layer extending lengthwise between the first edge and the second edge; and a submount 40 with a recess 42, the plurality of edge-emitting LED chips 44 residing at least partially within the recess 42 (Fig. 5: 40, 42, 44, paragraph 107). Miller et al. teaches a light-emitting diode (LED) device comprising the following limitations not disclosed in Pang et al.: an edge-emitting LED chip 100 comprising: the active layer 120 extending lengthwise between the first edge 145 and the second edge (opposite to 145) (see Fig. 1: 145); Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of Pang et al. and Miller et al. in order to have edge-emitting LED chips in the submount of Pang et al. with each edge-emitting LED chip having an active layer extending lengthwise between the first edge and the second edge. By doing so, the edge-emitting LED chip can improve light extraction in the recess by directing more of the generated light into the desired optical path. Regarding Claim 12, the combination of Pang et al. and Miller et al. teaches the LED device of claim 11, wherein the plurality of edge-emitting LED chips 44 comprises a first edge-emitting LED chip and a second edge-emitting LED chip within the recess 42, wherein the first edge-emitting LED chip is configured to provide a different emission wavelength than the second edge-emitting LED chip (as taught by Pang et al., see Fig. 5: 42, 44, paragraph 0096). Regarding Claim 13, the combination of Pang et al. and Miller et al., teaches the LED device of claim 11, further comprising a common first electrical connection 712a and a common second electrical connection 712b in the recess 716b for each edge-emitting LED chip 714b of the plurality of edge-emitting LED chips 714b (as taught by Pang et al., see Fig. 57-58: 712a, 712b, paragraph 0152). Note that while Fig. 57-58 shows only one LED chip 714b in the recess 716b, paragraph 0008 states one or more LED chips can be arranged within the recess. Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Pang et al. (US 20200176643 A1) in view of Miller et al. (US 20100032703 A1, as applied to Claim 11 above, further in view of Place et al. (US 20150228876 A1). Regarding Claim 14, the combination of Pang et al. and Miller et al. fails to teach the LED device of claim 11, further comprising a common first electrical connection and multiple second electrical connections in the recess for each edge-emitting LED chip of the plurality of edge-emitting LED chips. However, Place et al. teaches an LED device comprising a common first electrical connection 416 and multiple second electrical connections 418, 422, 426, 430 for each LED chip of the plurality of LED chips 402, 404, 406, 408 (Fig. 5: 416, 418, 422, 426, 430, 402, 404, 406, 408, paragraph 0070). Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of Pang et al., Miller et al. and Place et al. in order to have a common first electrical connection and multiple second electrical connections in the recess for each edge-emitting LED chip of the plurality of edge-emitting LED chips of Pang et al. Doing so would allow the LED chips to be individually controlled while sharing a common electrical connection, reducing wiring complexity and saving space. Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (CN 114388483 A) in view of Miller et al. (US 20100032703 A1), as applied to Claim 15 above, further in view of Lee et al. (US 20220367765 A1). Regarding Claim 8, the combination of Liu et al. and Miller et al. fails to teach the LED device of claim 15, wherein the top surface of the submount comprises a black surface. However, Lee et al. teaches a LED device, wherein the top surface of the submount 221 comprises a black surface 630 (Fig. 6: 221, 630, paragraph 0118). Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of Liu et al., Miller et al. and Lee et al. in order to have the top surface of the submount comprise a black surface. Doing so would enhance outdoor visibility by enhancing the contrast ratio and visibility of black color of the LED device by addressing a problem due to reflection of external light, as recognized by Lee et al. (paragraph 0118). Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (CN 114388483 A) in view of Miller et al. (US 20100032703 A1), as applied to Claim 19 above, further in view of Ying et al. (CN 107680960 A). Regarding Claim 20, the combination of Liu et al. and Miller et al. fails to teach the LED device of claim 19, wherein recess floors of the first recess and the second recess are open through a bottom surface of the submount. However, Ying et al. teaches and LED device, wherein recess floor of the recess 3 are open through a bottom surface of the submount 2 (Fig. 1: 2, 3, page 10, lines 34-36, page 11, lines 1-12 in English Translation of Ying et al.). Note that the submount 2 does not extend below the bottom of the recess 3 and thus the recess is open through the bottom surface of the submount 2. Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of Liu et al., Miller et al. and Ying et al. in order to have recess floors of the first recess and the second recess of Liu et al. open through a bottom surface of the submount. Doing so would minimize absorption of light by the submount. Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (CN 114388483 A) in view of Miller et al. (US 20100032703 A1), as applied to Claim 15 above, further in view of Lee et al. (US 20220367765 A1). Regarding Claim 21, the combination of Liu et al. and Miller et al. fails to teach the LED device of claim 15, wherein the top surface of the submount comprises light-scattering materials. However, Lee et al. teaches a LED device, wherein the top surface of the submount 221 comprises light-scattering materials 830 (Fig. 9: 221, 830, paragraph 0133). Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of Liu et al., Miller et al. and Lee et al. in order to have the top surface of the submount comprise light-scattering materials. Doing so would scatter the light emitted from the Led chip towards the desired optical path, as recognized by Lee et al. (paragraph 0133). Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Pang et al. (US 20200176643 A1) in view of Miller et al. (US 20100032703 A1, as applied to Claim 11 above, further in view of Lin et al. (US 20220059610 A1). Regarding Claim 22, the combination of Pang et al. and Miller et al. fails to teach the LED device of claim 11, further comprising a separate first electrical connection and a separate second electrical connection in the recess for each edge- emitting LED chip of the plurality of edge-emitting LED chips. However, Lin et al. teaches an LED device comprising a separate first electrical connection and a separate second electrical connection (shaded grey portions in Fig. 17) in the recess 30 for each LED chip 710, 720, 730 of the plurality of LED chips 710, 720, 730 (see Fig. 2: 30, Fig. 17: 710, 720, 730, paragraph 0059, 0030). Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of Pang et al., Miller et al. and Lin et al. in order to have a separate first electrical connection and a separate second electrical connection in the recess for each edge-emitting LED chip of the plurality of edge-emitting LED chips. Doing so would allow the LED chips to be individually controlled. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAMNA F IQBAL whose telephone number is 571-272-1587. The examiner can normally be reached M-F: 8.30 am - 5.30 pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham, can be reached at 571-272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HAMNA FATHIMA IQBAL/Examiner, Art Unit 2817 06/16/2026 /Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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Prosecution Timeline

Aug 09, 2023
Application Filed
Aug 28, 2023
Response after Non-Final Action
Jul 02, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
80%
Grant Probability
99%
With Interview (+25.0%)
3y 2m (~3m remaining)
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