DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
2. The Remarks filed October 6th, 2025 in response to the Non-Final Office Action mailed 06/06/2025 are noted.
3. Claims 1-20 are now canceled; Claims 21-40 remain pending in the application.
4. Claims 21-40 have been fully considered in examination.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 21-26 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng (U.S. PG Pub No US2019/0157420A1) (of record) in view of Xie (U.S. PG Pub No US2019/0305104A1) (of record).
Regarding claim 21, Cheng teaches a device (70) fig. 14 [0047] comprising:
a first semiconductor layer (upper 21) fig. 14 [0046, 0033] and a second semiconductor layer (lower 21) fig. 14 [0046, 0033];
a gate (50) fig. 14 [0052] that is disposed between a central portion of the first semiconductor layer (upper 21) and a central portion of the second semiconductor layer (lower 21), wherein the gate wraps (“all-around”) [0052, 0004-0005] the central portion of the first semiconductor layer (upper 21) and the central portion of the second semiconductor layer (lower 21);
a first epitaxial source/drain (left 34) fig. 14 [0050] disposed between a first (left) end portion of the first semiconductor layer (upper 21) and a first (left) end portion of the second semiconductor layer (lower 21);
a second epitaxial source/drain (right 34) fig. 14 [0050] disposed between a second (right) end portion of the first semiconductor layer (upper 21) and a second (right) end portion of the second semiconductor layer (lower 21);
a first inner spacer structure (left 62) fig. 14 [0052] and a second inner spacer (right 62) fig. 14 [0052] structure disposed between the first semiconductor layer (upper 21) and the second semiconductor layer (lower 21), wherein the first inner spacer structure (left 62) is between the first epitaxial source/drain (left 34) and the gate (50) and the second inner spacer structure (right 62) is between the second epitaxial source/drain (right 34) and the gate (50); and
wherein each of the first inner spacer structure (left 62) and the second inner spacer structure (right 62) has:
a first dielectric portion (DP1), a second dielectric portion (DP2) that (at least partially) wraps the first dielectric portion (DP1), and wherein the first dielectric portion (DP1) and the second dielectric portion (DP2) interface with the first epitaxial source/drain (left 34) or the second epitaxial source/drain (right 34) (respectively).
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Annotated figure 14 of Cheng designating first (DP1) and second (DP2) dielectric portions
However, Cheng does not explicitly disclose wherein a first composition of the first dielectric portion (DP1) is different than a second composition of the second dielectric portion (DP2) (same layer).
Xie teaches a device (1000) fig. 10 [see title, 0090] wherein a first composition of the first dielectric portion (328) fig. 10 [0090] (comprising oxygen/ “air” [0090]) is different than a second composition of the second dielectric portion (324) fig. 10 [0090] (SiN [0088] comprising silicon).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the GAA FET of Cheng such that the silicon oxide spacer material between the gate and source/drain(s) is replaced by a silicon nitride liner with airgap(s) [0088, 0090] – thereby altering the material composition of the dielectric portion(s) - in order to enhance the reduction of parasitic capacitance [0043, 0090] in the transistor(s), as taught by Xie.
Regarding claim 22, Cheng teaches the device (70) fig. 14 [0047] of claim 21. Cheng also teaches wherein the second dielectric portion (DP2) [see annotated fig. 14 above] is a dielectric layer (62) fig. 14 [0052] (comprising silicon oxide) [0037].
However, Cheng does not explicitly disclose wherein the first dielectric portion (DP1) is an airgap.
Xie teaches a device (1000) fig. 10 [see title, 0090] wherein the first dielectric portion (328) fig. 10 [0090] is an air gap [0090].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the GAA FET of Cheng such that the silicon oxide spacer material between the gate and source/drain(s) is replaced by a silicon nitride liner with airgap(s) [0088, 0090] – thereby altering the material composition of the dielectric portion(s) - in order to enhance the reduction of parasitic capacitance [0043, 0090] in the transistor(s), as taught by Xie.
Regarding claim 23, Cheng teaches the device (70) fig. 14 [0047] of claim 21. Cheng also teaches wherein each of the first inner spacer structure (left 62) fig. 14 [0052] and the second inner spacer structure (right 62) fig. 14 [0052] has:
an upper portion (upper third) formed by a first portion (upper third) of the second dielectric portion (DP2) [see annotated fig. 14 above];
a lower portion (lower third) formed by a second portion (lower third) of the second dielectric portion (DP2);
a middle portion (middle third) formed by a third portion (middle third) of the second dielectric portion (DP2) and the first dielectric portion (DP1); and
wherein the upper portion is disposed (directly) on the first semiconductor layer (upper 21) fig. 14 [0046, 0033] and the lower portion is disposed (directly) on the second semiconductor layer (lower 21) fig. 14 [0046, 0033].
Regarding claim 24, Cheng teaches the device (70) fig. 14 [0047] of claim 23. Cheng also teaches wherein:
each of the first inner spacer structure (left 62) fig. 14 [0052] and the second inner spacer structure (right 62) fig. 14 [0052] has a total (horizontal) thickness between the gate (50) fig. 14 [0052] and the first epitaxial source/drain (left 34) fig. 14 [0050] or the second epitaxial source/drain (right 34) fig. 14 [0050];
each of the first portion of the second dielectric portion (DP2) [see annotated fig. 14 above] forming the upper portion (comprising uppermost surface of 62) and the second portion of the second dielectric portion forming the lower portion (comprising lowermost surface of 62) has a first thickness, wherein the first thickness is equal to the total thickness; and
the third portion of the second dielectric portion (DP2) forming the middle portion has a second thickness (= total thickness – DP1 thickness), the first dielectric portion (DP1) [see annotated fig. 14 above] forming the middle portion has a third thickness (= total thickness – DP2 thickness), and a sum of the second thickness and the third thickness is equal to the total thickness (62s have uniform thicknesses).
Regarding claim 25, Cheng teaches the device (70) fig. 14 [0047] of claim 21. Cheng also teaches wherein each of the first inner spacer structure and the second inner spacer structure has:
a total (vertical) length between the first semiconductor layer (upper 21) fig. 14 [0046, 0033] and the second semiconductor layer (lower 21) fig. 14 [0046, 0033];
a gate interfacing portion formed by a (innermost side) first portion of the second dielectric portion (DP2) [see annotated fig. 14 above] having a first length that is equal to the total length; and
an epitaxial source/drain interfacing portion formed by the first dielectric portion (DP1) [see annotated fig. 14 above] disposed between a second portion (outermost side of DP2 above DP1) of the second dielectric portion (DP2) and a third portion (outermost side of DP2 below DP1) of the second dielectric portion (DP2), wherein:
the first dielectric portion (DP1) has a second length (2nd length defined to be about 2.9 nm, which is less than total vertical length of spacer, 6-20 nm long [0034]), the second portion of the second dielectric portion has a third length (= total length – third portion length– 2nd length), and the third portion of the second dielectric portion has a fourth length (= total length – 3rd length – 2nd length), and a sum of the second length, the third length, and the fourth length is equal to the total length (62s have uniform thicknesses).
Regarding claim 26, Cheng teaches the device (70) fig. 14 [0047] of claim 21. Cheng also teaches wherein the second length (side length of DP1, defined to be about 2.9 nm, which is less than total vertical length of spacer, 6-20 nm long [0034]) is less than about 3 nm.
Claims 27-31 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng (U.S. PG Pub No US2019/0157420A1) (of record) in view of Sung (U.S. PG Pub No US2017/0005176A1) (of record) and Xie (U.S. PG Pub No US2019/0305104A1) (of record).
Regarding claim 27, Cheng teaches a device (70) fig. 14 [0047] comprising:
a first semiconductor layer (upper 21) fig. 14 [0046, 0033] and a second semiconductor layer (lower 21) fig. 14 [0046, 0033];
a gate structure having a gate (50) fig. 14 [0052] disposed between gate spacers (comprising 38, 48) fig. 14 [0044], wherein the gate (50) wraps (“all-around”) [0052, 0004-0005] the first semiconductor layer (upper 21) and the second semiconductor layer (lower 21) and the gate (50) is disposed between the first semiconductor layer (upper 21) and the second semiconductor layer (lower 21);
an epitaxial source/drain (34) fig. 14 [0050] that wraps an (left/right) end of the first semiconductor layer (upper 21) and an (left/right) end of the second semiconductor layer (lower 21), wherein:
the end of the first semiconductor layer (upper 21) includes a first top surface extending along a first (horizontal) direction, a first bottom surface extending along the first (horizontal) direction, and a first sidewall surface that extends from the first top surface to the first bottom surface (see annotated fig. 14 of Cheng below),
the end of the second semiconductor layer (lower 21) includes a second top surface extending along a first (horizontal) direction, a second bottom surface extending along the first (horizontal) direction, and a second sidewall surface that extends from the second top surface to the second bottom surface (see annotated fig. 14 of Cheng below), and
the epitaxial source/drain (34) has a lateral extending portion (between upper and lower 21s) that extends under one of the gate spacers (comprising 38), wherein the lateral extending portion of the epitaxial source/drain (34) is disposed between and extends over (in contact with) the first bottom surface of the first end of the first semiconductor layer (upper 21) and the second top surface of the second end of the second semiconductor layer (lower 21); and
a dielectric structure (62) fig. 14 [0052] disposed between the gate (50) fig. 14 [0052] and the lateral extending portion (between upper and lower 21s) of the epitaxial source/drain (34), wherein the dielectric structure (62) is disposed between the first semiconductor layer (upper 21) and the second semiconductor layer (lower 21).
[AltContent: arrow][AltContent: arrow][AltContent: textbox (Bottom surface)][AltContent: textbox (Top surface)]
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Annotated fig. 14 of Cheng designating top, bottom, and side surface(s) of channels 21
However, Cheng does not explicitly disclose and a sidewall surface of the first semiconductor layer (upper 21) extends along a second (vertical) direction,
a sidewall surface of the second semiconductor layer (lower 21) extends along a second (vertical) direction,
wherein the second (vertical) direction is orthogonal to the first (horizontal) direction,
and the dielectric structure (62) includes a U-shaped dielectric layer and an air gap, wherein the air gap is disposed between the U-shaped dielectric layer and the lateral extending portion of the epitaxial source/drain (34).
Sung teaches a device (300) fig. 3I [see title, 0037] wherein a sidewall surface of the first semiconductor layer (upper 306) fig. 3I [0027, 0037] extends along a second (vertical) direction,
a sidewall surface of the second semiconductor layer (lower 306) fig. 3I [0027, 0037] extends along a second (vertical) direction,
wherein the second (vertical) direction is orthogonal to the first (horizontal) direction.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor channel layers of Cheng to adopt a rectangular or octagonal cross-sectional shape [0027] instead of a hexagonal shape [0027], thereby introducing vertically-extending sidewalls [0027] to the nanostructure channels [0027], in order to potentially help improve the accessibility of etching material which is intended to be removed [0003] so as to reduce undesirable material damage [0003, 0018-0019], as taught by Sung. However, the modification is achieved by a mere change of geometry [0027] of the channel structure which is obvious absent persuasive evidence of the special significance of a particular shape of the nanostructures (rectangular vs hexagonal vs octagonal [0027 Sung]). (See MPEP 2144.04, IV, C).
However, Cheng in view of Sung does not explicitly disclose and the dielectric structure (62) includes a U-shaped dielectric layer and an air gap, wherein the air gap is disposed between the U-shaped dielectric layer and the lateral extending portion of the epitaxial source/drain (34).
Xie teaches a device (1000) fig. 10 [see title, 0090] and the dielectric structure (comprising 324, 328) fig. 10 [0090] includes a U-shaped dielectric layer (324) [0088, 0090] and an air gap (328) [0090], wherein the air gap (328) is disposed between (laterally between) the U-shaped dielectric layer (324) and the lateral extending portion of the epitaxial source/drain (330) fig. 10 [0090].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the GAA FET of Cheng in view of Sung such that the silicon oxide spacer material between the gate and source/drain(s) of Cheng is replaced by a silicon nitride liner with airgap(s) [0088, 0090] – thereby altering the material composition of the dielectric portion(s) - in order to enhance the reduction of parasitic capacitance [0043, 0090] in the transistor(s), as taught by Xie.
Regarding claim 28, Cheng teaches the device (70) fig. 14 [0047] of claim 27. Cheng also teaches wherein the dielectric structure (62) fig. 14 [0052] and the lateral extending portion (between upper and lower 21s) of the epitaxial source/drain (34) fig. 14 [0050] are disposed underneath the one of the gate spacers (38) fig. 14 [0044].
Regarding claim 29, Cheng teaches the device (70) fig. 14 [0047] of claim 27. Cheng in view of Sung and Xie (with reference to Xie) also teaches wherein:
the U-shaped dielectric layer (comprising 324) fig. 10 [0088, 0090] forms a top of the dielectric structure (comprising 324, 328) fig. 10 [0088, 0090] that is disposed along the first semiconductor layer (312C) fig. 10 [0097] and a bottom of the dielectric structure (comprising 324, 328) that is disposed along the second semiconductor layer (312B) fig. 10 [0097]; and
the U-shaped dielectric layer (324) and the air gap (328) form a middle of the dielectric structure (comprising 324, 328).
Regarding claim 30, Cheng teaches the device (70) fig. 14 [0047] of claim 27. Cheng in view of Sung and Xie (with reference to Xie) also teaches wherein the air gap (328) fig. 10 [0090] has a rectangular shape (see fig. 10).
Regarding claim 31, Cheng teaches the device (70) fig. 14 [0047] of claim 27. Cheng also teaches wherein:
a spacing is between the first semiconductor layer (upper 21) and the second semiconductor layer (lower 21) along the second (vertical) direction; and
and a length of the air gap along the second (vertical) direction is less than about 3 nm (about 0nm).
Claims 32-40 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng (U.S. PG Pub No US2019/0157420A1) (of record) in view of Bhuwalka (U.S. PG Pub No US2020/0066725A1) (of record) and Yang (U.S. PG Pub No US2020/0052086A1) (of record).
Regarding claim 32, Cheng a semiconductor device (70) fig. 14 [0047], comprising:
a substrate (24) fig. 14 [0033];
a first source/drain feature (left 34) fig. 14 [0050] and a second source/drain feature (right 34) fig. 14 [0050] over the substrate (24);
a first semiconductor layer (upper 21) fig. 14 [0046, 0033] and a second semiconductor layer (lower 21) fig. 14 [0046, 0033] extending lengthwise along a first (horizontal) direction between the first source/drain feature (left 34) and the second source/drain feature (right 34);
a gate (50) fig. 14 [0052] between the first source/drain feature (left 34) and the second source/drain feature (right 34), a second (in/out of page) direction, a portion of the gate (50) is between the first semiconductor layer (upper 21) and the second semiconductor layer (lower 21), and top surfaces and bottom surfaces of the first semiconductor layer (upper 21) and the second semiconductor layer (lower 21) extend a lateral distance along the first (horizontal) direction beyond sidewalls of the portion of the gate (50) (see annotated fig. 14 below); and
a first inner spacer (left 62) fig. 14 [0052] and a second inner spacer (right 62) fig. 14 [0052], wherein:
the first inner spacer (left 62) is between the first semiconductor layer (upper 21) and the second semiconductor layer (lower 21) along the a third (vertical) direction that is orthogonal to the first (horizontal) direction and the second (in/out of page) direction,
the first inner spacer (left 62) is between the portion of the gate (50) and a portion of the first source/drain feature (left 34), wherein the portion of the first source/drain feature (left 34) is between the first semiconductor layer (upper 21) and the second semiconductor layer (lower 21) along the third (vertical) direction and a maximum thickness of the first inner spacer (62) along the first (horizontal) direction is less than the lateral distance (see annotated fig. 14 below),
[AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox (Max thickness of spacer )][AltContent: textbox (Lateral Distance )][AltContent: connector][AltContent: connector][AltContent: connector][AltContent: connector]
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Annotated fig. 14 of Cheng designating directions of the channels 21
However, Cheng does not explicitly disclose wherein the gate extends lengthwise along a second (in/out of page) direction that is orthogonal to than the first (horizontal) direction,
the first inner spacer (left 62) has a U-shaped profile, and the second inner spacer (right 62) is between the first inner spacer (left 62) and the portion of the first source/drain feature (left 34).
Bhuwalka teaches a semiconductor device [see title, 0017-0018] wherein the gate (GN) fig. 4 [0019, 0029] extends lengthwise [see fig. 1] along a second (in/out of page in cross-section of fig. 4 – y direction) direction that is orthogonal to than the first (horizontal/ x-) direction [0026].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the gate electrodes of the GAA-FET of Cheng to explicitly extend [0019] in/out of the page of a cross-sectional view [0019] in order to increase the amount of gate material brought into contact with adjacent structures [0021-0023, 0028-0031], as taught by Bhuwalka. Further, Bhuwalka evidences that this directional arrangement is typical for a logic cell [0019].
However, Cheng in view of Bhuwalka does not explicitly disclose the first inner spacer (left 62) has a U-shaped profile, and the second inner spacer (right 62) is between the first inner spacer (left 62) and the portion of the first source/drain feature (left 34).
Yang teaches a device [0062, 0005-0009] wherein the first inner spacer (33) fig. 3B [0063-0064] has a U-shaped profile, and the second inner spacer (comprising 35 with 37) fig. 3B [0063-0064] is between the first inner spacer (33) and the portion of the first source/drain feature (50) [0054] (see placement in fig. 2A, fig. 13A).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the GAA FET of Cheng in view of Bhuwalka such that the silicon oxide spacer material between the gate and source/drain(s) is replaced by SiOCN layer [0067] having airgap, thereby forming u-shaped insulating material [0062-0063], in order to decrease capacitance between [0048] the gate from the source/drain without using extra low-k insulator material [0063-0065], as taught by Yang.
Regarding claim 33, Cheng teaches the device (70) fig. 14 [0047] of claim 32. Cheng in view of Yang also teaches wherein the first inner spacer (left 62) fig. 14 [0052] includes a first portion (right side) on one of the sidewalls of the portion of the gate (50) fig. 14 [0052], a second portion that partially covers (extends over) the bottom surface of the first semiconductor layer (upper 21) fig. 14 [0046, 0033], and a third portion that partially covers (extends over) the top surface of the second semiconductor layer (lower 21) fig. 14 [0046, 0033],
wherein the first portion has a first surface (right side) opposing (parallel) the one of sidewalls of the portion of the gate (50), the second portion has a second surface (top side) opposing (parallel) the bottom surface of the first semiconductor layer (upper 21), and the third portion has a third surface (bottom side) opposing the top surface of the second semiconductor layer (lower 21),
wherein a fourth surface (right side) of the portion of the first source/drain feature (left 34) is spaced away from the first surface of the first portion (right side of 62),
and wherein the second inner spacer (comprising 35 with 37 from Yang) fig. 3B [0063-0064 Yang] is defined by (has boundaries defined by) the first surface (right side) of the first portion, the second (top) surface of the second portion, the third (bottom) surface of the third portion, and the fourth surface (right) of the portion of the first source/drain feature (left 34).
Regarding claim 34, Cheng teaches the device (70) fig. 14 [0047] of claim 32. Cheng in view of Yang (with reference to Yang) also teaches wherein the second inner spacer (comprising 37) fig. 3B [0063-0064 Yang] is an air gap (37) [0063-0064].
Regarding claim 35, Cheng teaches the device (70) fig. 14 [0047] of claim 32. Cheng in view of Yang (with reference to Yang) also teaches wherein the second inner spacer (comprising 35) fig. 3B [0063-0064 Yang] includes an oxide material (SiOCN [0117]).
Regarding claim 36, Cheng teaches the device (70) fig. 14 [0047] of claim 32. Cheng in view of Yang (with reference to Yang) also teaches wherein the second inner spacer (comprising 35) fig. 3B [0063-0064 Yang] includes a nitride material (SiOCN [0117]).
Regarding claim 37, Cheng teaches the device (70) fig. 14 [0047] of claim 32. Cheng in view of Yang (with reference to Yang) also teaches wherein the second inner spacer (comprising 35 with 37) fig. 3B [0063-0064 Yang] has a rectangle profile.
Regarding claim 38, Cheng teaches the device (70) fig. 14 [0047] of claim 32. Cheng in view of Yang (with reference to Yang) wherein:
the first inner spacer (33) fig. 3B [0063-0064 Yang] has a first (horizontal) thickness along the first (horizontal) direction, the second inner spacer (comprising 35 with 37) fig. 3B [0063-0064 Yang] has a second thickness along the first (horizontal) direction, and the second thickness is less than the first thickness.
Regarding claim 39, Cheng teaches the device (70) fig. 14 [0047] of claim 32. Cheng in view of Yang (with reference to Yang) wherein the portion of the first source/drain feature (left 50) [0054] (see placement in fig. 2A, fig. 13A) includes a (right) sidewall, a first section of the sidewall interfaces with the first inner spacer (33) fig. 3B [0063-0064 Yang], and a second section of the sidewall interfaces with the second inner spacer (comprising 35 with 37) fig. 3B [0063-0064 Yang].
Regarding claim 40, Cheng teaches the device (70) fig. 14 [0047] of claim 32. Cheng in view of Yang (with reference to Yang) wherein the second inner spacer (comprising 37) fig. 3B [0063-0064 Yang] has a first dimension (= thickness of 20 – 2 * thickness of 33) [see fig. 1A, fig. 3B, 0076, 0066] and a second dimension (Wa), wherein the first dimension is less than about 3 nm along the third (vertical) direction (height of airgap 37 could be 5nm [0076] – 1.5*2 nm [0066] = about 2nm), and the second dimension is about 2 nm to 6 nm along the first (horizontal) direction (could be about 2nm [0064]).
Response to Arguments
Applicant's arguments filed 10/06/2025 have been fully considered but they are not persuasive.
With respect to Applicant’s argument(s) of independent claims 21, 27, and 32 that “The Office Action on pages 3-5 arbitrarily divides Cheng's inner spacers 62 (i.e., oxide material formed by oxidizing silicon germanium layers 22 (see Cheng at paragraphs [0037], [0040]-[0042], [0047], and [0050])) into "inner rectangle portion[s]" and "remaining portion[s] of 62's outside" of the inner rectangular portions to meet the claimed "first dielectric portion" and "second dielectric portion," respectively, of the first inner spacer structure and the second inner spacer structure” it is noted that one of ordinary skill in the art would recognize that the term “portion” is broad, and that two “portions” of a single object can be reasonably identified in any number of ‘arbitrary’ ways. That being said, the first and second dielectric portions of Cheng are defined in a way that corresponds to all of the structural requirements claimed in the independent claims, such as “… a second dielectric portion (DP2) that (at least partially) wraps the first dielectric portion (DP1), and wherein the first dielectric portion (DP1) and the second dielectric portion (DP2) interface with the first epitaxial source/drain (left 34) or the second epitaxial source/drain (right 34) (respectively)” --- the only missing limitation in Cheng concerns the difference in relative compositions between said first and second dielectric portions due to the presence of an air gap.
With respect to Applicant’s argument(s) of secondary reference Xie, introduced to remedy this deficiency, that “However, Xie does not disclose replacing a portion of an oxide material, such as Cheng's inner spacers 62, to form its air gap spacers 328, as asserted by the Office Action. Instead, Xie teaches completely removing its oxide fill 326 to form its air gap spacers 328…” --- it is noted that the entirety of the inner spacers in both Cheng and Xie is defined as comprising all dielectric material in the divots, vertically between the channels.
Other arguments with respect to Cheng in view of Xie for claims 21 and 27 are rendered largely-moot on two grounds:
-First, it is emphasized that the claimed invention is directed to a finished product, not a method. The process(es) referenced by applicant is/are essentially not relevant to the product/device of claims 21 and 27. In other words, because the claims are directed to a product, it is the patentability of the final product that must be determined and not a process used to acquire the final product; the difference in intermediate processing steps described by Applicant do not bear weight on assessing the patentability of the claimed device.
-Second, the 35 U.S.C. 103 motivation statement has been slightly reinterpreted such that the modification is directed towards total replacement of the silicon oxide spacers 32 of Cheng rather than partial removal, such that the silicon oxide spacers are replaced by a silicon-nitride + air-gap combination. Doing so would realize the benefit of enhanced reduction of parasitic capacitance [0043, 0090] in the transistor(s), as taught by Xie. Therefore, claim 21 is held unpatentable under a same grounds of rejection; Claim 21 remains rejected under 35 U.S.C. 103 by Cheng (U.S. PG Pub No US2019/0157420A1) (of record) in view of Xie (U.S. PG Pub No US2019/0305104A1) (of record), and Claim 27 remains rejected under 35 U.S.C. 103 by Cheng (U.S. PG Pub No US2019/0157420A1) (of record) in view of Sung (U.S. PG Pub No US2017/0005176A1) (of record) and Xie (U.S. PG Pub No US2019/0305104A1) (of record).
Similarly, arguments with respect to Cheng in view of Yang for claim 32 are rendered largely-moot on two grounds:
-First, it is emphasized that the claimed invention is directed to a finished product, not a method. The process(es) referenced by applicant is/are essentially not relevant to the product/device of claims 32. In other words, because the claims are directed to a product, it is the patentability of the final product that must be determined and not a process used to acquire the final product; the difference in intermediate processing steps described by Applicant do not bear weight on assessing the patentability of the claimed device.
-Second, the 35 U.S.C. 103 motivation statement has been slightly reinterpreted such that the modification is directed towards total replacement of the silicon oxide spacers 32 of Cheng rather than partial removal, such that the silicon oxide spacers are replaced by a SiOCN + air-gap combination. Doing so would realize the benefit of a decrease in detrimental capacitance between [0048] the gate from the source/drain without using extra low-k insulator material [0063-0065], as taught by Yang. Therefore, claim 32 is held unpatentable under a same ground of rejection; Claim 32 remains rejected under 35 U.S.C. 103 by Cheng (U.S. PG Pub No US2019/0157420A1) (of record) in view of Bhuwalka (U.S. PG Pub No US2020/0066725A1) (of record) and Yang (U.S. PG Pub No US2020/0052086A1) (of record).
Lastly, it noted that both Xie [0043, 0090], as applied to independent claims 21 and 27, and Yang [0048], as applied to claim 32, explicitly teach the same motivation - a reduction in parasitic capacitance - associated with the modification of introducing an air gap into the sidewall spacer of a GAA-FET nano-structure. Therefore, one of ordinary skill in the art would recognize that this structural modification is common in the art, as it provides the well-established benefit of improved capacitance characteristics to the transistor device, and that the incorporation of an air gap into a base GAA-FET structure, such as that of Cheng, does not constitute a novel patentable difference over the status of prior art.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Remaining references made available on the PTO-892 form (of record) disclose epitaxial source/drain features extending underneath channels in GAA-FETs.
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 01/17/2026
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892