DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10, 12-14, 21- 26 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al (US Publication No. 2020/0044048) in view of Tsai et al (US Publication No. 2020/0105589) and Yeong et al (US Publication No. 2020/0381289).
Regarding claim 1, Yu discloses a semiconductor device comprising: a recess between fins in a substrate Fig 3; a dielectric layer Fig 7, 60 over the fins Fig 7, 52 and in the recess Fig 7, a bottom seed structure Fig 8, 63 in the recess; and a dummy gate material Fig 11, 63’ extending from the bottom seed structure to a top of the recess Fig 11 ¶0030-0031. Yu discloses all the limitations except for the specific thickness of the dielectric layer and the arrangement of the dielectric layer. Whereas Tsai discloses a semiconductor device comprising: a recess between fins in a substrate Fig 5;a dielectric layer Fig 5, 140 over the fins and along a bottom of the recess Fig 5,a bottom seed structure Fig 6, 150 at the bottom of the recess directly on the dielectric layer Fig 6; and a dummy gate material extending from the bottom seed structure to a top of the recess ¶0028. While Yeong discloses wherein the dielectric layer has a first thickness over the fins and a second thickness different from the first thickness at the bottom of the recess Fig 2A-2B ¶0033-0035. Yu, Tsai and Yeong are analogous art because they are directed to FinFET devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of Yu because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the dielectric layer of Yu and incorporate the teachings of Tsai and Yeong to provide additional isolation and insulation of the neighboring structures.
Regarding claim 2, Yu discloses wherein the bottom seed structure is a silicon film ¶0025.
Regarding claim 3, Yu discloses wherein the dielectric layer is SiO ¶0024.
Regarding claim 4, Yu discloses wherein the dummy gate material is absent of any voids from the bottom seed structure to the top of the recess Fig 11-12.
Regarding claim 5, Yeong discloses wherein the recess has an aspect ratio in a range of 3:1 to 9:1 ¶0054 and 0077.
Regarding claim 6, Yu discloses wherein the dummy gate material has a first concentration of impurities ¶0027 and the bottom seed structure has a second concentration of impurities, the second concentration of impurities being in a range of o% to 2% of the first concentration of impurities ¶0030-0031.
Regarding claim 7, Yu discloses wherein, wherein the second concentration of impurities comprises hydrogen ¶0027-0031.
Regarding claim 8, Yu discloses a semiconductor device comprising: a trench between fins in a semiconductor substrate Fig 3;a gate dielectric material Fig 7, 60 over the fins Fig 7, 52, a first silicon material Fig 8, 63 over the gate dielectric material Fig 8, 60; and a second silicon material Fig 11, 63’ over the first silicon material Fig 11, 63, wherein the second silicon material completely fills the trench without any voids in the second silicon material Fig 11 ¶0030-0031. Yu discloses all the limitations except for the specific thickness of the dielectric layer and the arrangement of the dielectric layer.
Whereas Tsai discloses a semiconductor device comprising: a recess between fins in a substrate Fig 5;a gate dielectric material Fig 5, 140 along a bottom of the trench and the fins Fig 5. While Yeong discloses wherein a gate dielectric material Fig 2A at a bottom of the trench Fig 2A and over the fins Fig 2A-2B; the dielectric layer has a first thickness over the fins and a second thickness different from the first thickness in the recess Fig 2A-2B ¶0033-0035. Yu, Tsai and Yeong are analogous art because they are directed to FinFET devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of Yu because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the dielectric layer of Yu and incorporate the teachings of Tsai and Yeong to provide additional isolation and insulation of the neighboring structures.
Regarding claim 9, Yu discloses wherein an interface between the first silicon material and the second silicon material is seamless Fig 11-12.
Regarding claim 10, Yu discloses wherein the first silicon material is a silicon film ¶0025.
Regarding claim 12, Yu discloses wherein the first silicon material has a first concentration of impurities and the second silicon material has a second concentration of impurities, the first concentration of impurities being in a range of o% to 2% of the second concentration of impurities¶0027-0031.
Regarding claim 13, Yu discloses wherein the first concentration of impurities comprises hydrogen¶0027-0031.
Regarding claim 14, Yeong discloses wherein the trench has an aspect ratio in a range of 3:1 to 9:1 ¶0054 and 0077.
Regarding claim 21, Yu discloses a semiconductor device comprising: a structure having a trench extending into the structure from an upper surface of the structure Fig 3; a dielectric material layer along sidewalls Fig 7; a first silicon material layer Fig 8, 63 over the dielectric material layer Fig 8, 60; and a second silicon material layer Fig 11, 63’ over the first silicon material layer Fig 11, 63, wherein the second silicon material layer completely fills remaining portions of the trench without any voids in the second silicon material layer Fig 11-12. Yu discloses all the limitations except for the specific thickness of the dielectric layer and the arrangement of the dielectric layer.
Whereas Tsai discloses a semiconductor device comprising: a structure having a trench extending into the structure from an upper surface of the structure Fig 5;a gate dielectric material layer Fig 5, 140 along sidewalls and along a bottom of the trench Fig 5. While Yeong discloses a gate dielectric material layer along sidewalls Fig 2A and along a bottom of the trench Fig 2A, wherein the gate dielectric material layer has a first thickness at the bottom of the trench and a second thickness over the upper surface of the structure Fig 2A-2B ¶0033-0035, wherein the first thickness is different from the second thickness Fig 2A-2B ¶0033-0035. Yu, Tsai and Yeong are analogous art because they are directed to FinFET devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of Yu because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the dielectric layer of Yu and incorporate the teachings of Tsai and Yeong to provide additional isolation and insulation of the neighboring structures.
Regarding claim 22, Yu discloses wherein a concentration of impurities in the first silicon material layer is within o% to 2% of a concentration of impurities in the second silicon material layer¶0027-0031.
Regarding claim 23, Yu discloses wherein the impurities comprise hydrogen ¶0027-0031.
Regarding claim 24, Yu discloses wherein the structure includes two fin structures, wherein the trench is between the two fin structures, wherein the dielectric material layer, the first silicon material layer, and the second silicon material layer form a dummy gate structure Fig 11-12.
Regarding claim 26, Yu discloses wherein the first silicon material layer has a thickness along the bottom of the trench between 0.5 nm and 50 nm ¶0029.
Regarding claim 27, Yu discloses, wherein the first silicon material layer is thinner along the sidewalls of the trench than along a bottom of the trench Fig 10.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et al (US Publication No. 2020/0044048) in view of Tsai et al (US Publication No. 2020/0105589) , Yeong et al (US Publication No. 2020/0381289) in further view of Toh et al (US Publication No. 2014/0048865).
Regarding claim 11, Yu discloses all the limitations except for the material used for the dielectric layer. Whereas Toh discloses wherein the gate dielectric material comprises SiON ¶0025. Yu and YToh are analogous art because they are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of Yu because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the dielectric layer of Yu and incorporate the teachings of Toh since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of design choice. In re Leshin, 125 USPQ 416 (1960).
Response to Arguments
Applicant’s arguments with respect to claims 1-14, 21-26 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTINE A ENAD whose telephone number is (571)270-7891. The examiner can normally be reached Monday-Friday, 7:30 am -4:30 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571 272 1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHRISTINE A ENAD/Primary Examiner, Art Unit 2811