DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This Office Action responds to the Application filed on 8/9/2023. Claims 1-20 are pending.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-8 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-10 of U.S. Patent No. 11,775,725 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the present claims obvious variations of the patented claims, reciting similar steps/operations of determining a power parameter and in response to the determined power parameter exceeding a design criterion, perform a modification of the IC layout diagram which comprises the modification comprising at least one of altering a placement of the cell in the IC layout diagram or modifying a power delivery path to the cell ; wherein the power parameter comprises at least one of a power density of a tile containing the cell, a voltage drop of the tile containing the cell, or a voltage drop of the cell as recited in the patented claims are specific power process parameters which the present claims cover; and wherein the power parameters is performed before a routing operation in the IC layout diagram as recited in the present claims are covered by the patented claim 3, in which the routing in the IC layout is performed after the modification of the IC layout diagram which is performed after the determination of the power parameter as recited claim 1, from which the claims depend; thus, this step/operation of determining the power parameter is performed before the routing step/operation; wherein as per present claims 1-8, the claims are directed to a method whereas the patented claims are directed to a system. It would have been further obvious to one of ordinary skilled in the art at the time of the effective filing date of the invent to derive the steps from the system and vice versa because it is known in the art of computer-aided circuit design, a computer-implemented method are performed by the computer system.
Claims 9-15 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-10 of U.S. Patent No. 11,775,725 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the present claims obvious variations of the patented claims, reciting similar steps/operations of determining a power density of a tile and in response to the determined power density exceeding a design criterion, perform a modification of the IC layout diagram to obtain a modified IC layout diagram; and performing routing to the plurality of cells in the modified IC layout diagram; wherein the modification of the IC layout diagram comprising at least one of altering a placement of at least one cell of the tile, or modifying a power delivery path to at least one cell of the tile, as recited in the patented claims, are covered by the present claims.
Claims 16-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 18 of U.S. Patent No. 11,775,725 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims are obvious variations of each other, performing similar operations of determining voltage drop, and in response to the determined voltage drop exceeding a design criterion, perform a modification of the IC layout diagram by adding a further interconnection to connect the cell to the true power rail; except that the patented claims further recites the additional operations of the operation of determining cell power of a cell and an effective resistance of the interconnection configured to deliver power supply from the true power rail to the cell, from which the voltage drop is determined, which is obvious subset of operations/steps to determine the voltage drop as presently claimed, being obvious to one of ordinary skilled in the art at the time of the effective filing date of the invention, based on the teachings of the patented claims, to arrive at the present claims without undue experimentation; and the operation of adding a further interconnection to connect the cell…without altering a placement of the cell in the IC layout diagram as further recited in the patented claims are obvious subset of the step/operation of adding a further interconnection to connect the cell to the true power which the present claims cover.
Claims 1-8 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,205,032 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the present claims obvious variations of the patented claims, reciting similar steps/operations of determining a power parameter and in response to the determined power parameter exceeding a design criterion, perform a modification of the IC layout diagram which comprises the modification comprising at least one of altering a placement of the cell in the IC layout diagram or modifying a power delivery path to the cell ; except that patented claims further recites the steps of determining a cell loading from which the power parameter is determined, which is an obvious subset of the step of determining a power parameter of the present claims, which the present claims cover; and wherein at least one of the determining the cell loading, the determining of the power parameter, the altering the placement of the cell, or the modifying the power delivery path is executed by a processor as recited in the patented claims, are covered by the method executed at least partially by a processor as recited by the present claims.
It is noted that the prohibition under 35 USC 121 due the parent case (16/592,200) was originally restricted does not apply because the present claims are generic to the two groups of the inventions of the originally restricted, wherein the determined “power parameters” of the present claim, would cover all of the specific power parameters of the original claims (i.e., cell loading, power density of a tile) and the present claims are patently distinct from the third group of invention as originally restricted (i.e., the present claims do not recites the determination of the effective resistance of the interconnection, the voltage drop of the cell and in response to the voltage drop exceeding the design criterion).
Allowable Subject Matter
Claims 1-20 would be allowable if the obviousness double patenting rejections under 35 USC 101 as set forth in this Office Action are overcome.
The following is a statement of reasons for the indication of allowable subject matter:
As per claims 1-8, the independent claim 1, from which the claims depend, recites the method comprising a combination of inventive steps of in response to the determined power parameter exceeding a design criterion, performing a modification of the IC layout diagram, the modification comprising at least one of altering a placement of the cell in the IC layout diagram or modifying a power delivery path to the cell, wherein the determining the power parameter is performed before a routing operation in the IC layout diagram, which the prior arts made of record failed to teach or suggest as claimed. Furthermore, under the 2019 Patent Eligibility Guideline, the claims are directed to patent eligible subject matter because (1) under Step 1, the claims are directed to a process; (2) under Step 2A, Prong One, the claims are not directed to mathematical concepts comprising mathematical relationships, mathematical formulas or equations, and mathematical calculations since no expressed equation or formula is recited in the claims; nor are the claims directed to a mental process since one of ordinary skilled in the art at the time of the filing of the invention, would NOT reasonably be able to perform the method mentally since the calculations would involve large amount of data associated with the electronic design, as normally found in the art of computer-aided design and analysis of circuits; nor are the claims directed to certain methods of organizing human activity.
As per claims 9-15, the independent claim 9, from which the claims depend, recites the system comprising a combination of inventive operations of in response to the determined power density (of a tile) exceeding a design criterion, perform a modification of the IC layout diagram to obtain a modified IC layout diagram, and perform routing to the plurality of cells in the modified IC layout diagram, as claimed, which the prior arts made of record failed to teach or suggest as claimed. Furthermore, under the 2019 Patent Eligibility Guideline, the claims are directed to patent eligible subject matter because (1) under Step 1, the claims are directed to a machine; (2) under Step 2A, Prong One, the claims are not directed to mathematical concepts comprising mathematical relationships, mathematical formulas or equations, and mathematical calculations since no expressed equation or formula is recited in the claims; nor are the claims directed to a mental process since one of ordinary skilled in the art at the time of the filing of the invention, would NOT reasonably be able to perform the method mentally since the calculations would involve large amount of data associated with the electronic design, as normally found in the art of computer-aided design and analysis of circuits; nor are the claims directed to certain methods of organizing human activity.
As per claims 16-20, the independent claim 16, from which the claims depend, recites a computer program product, comprising a non-transitory computer-readable storage medium comprising a combination of inventive operations/instructions comprising in response to the determined voltage drop exceeding a design criterion, perform a modification of the IC layout diagram, in which the modification of the IC layout comprising adding a further interconnection to connect the cell to the true power rail, as claimed, which the prior arts made of record failed to teach or suggest as claimed. In particular, Yang et al. (US Patent Application Publication No. 20120110530 A1) disclose in paragraph [0017] that the determination of voltage drop (i.e., IR drop) in the cell(s) of the IC layout diagram, receiving power supply from true power rail (i.e., power supply VDD), when exceeded the predetermined threshold value, the layout is modified in order to reduce the voltage drop, but failed to teach that this modification is done by adding an interconnection to connect the cell to the true power rail; but failed to teach that is modification to the IC layout comprises adding a further interconnection to connect the cell to the true power rail, as claimed. Furthermore, under the 2019 Patent Eligibility Guideline, the claims are directed to patent eligible subject matter because (1) under Step 1, the claims are directed to an article of manufacture; (2) under Step 2A, Prong One, the claims are not directed to mathematical concepts comprising mathematical relationships, mathematical formulas or equations, and mathematical calculations since no expressed equation or formula is recited in the claims; nor are the claims directed to a mental process since one of ordinary skilled in the art at the time of the filing of the invention, would NOT reasonably be able to perform the method mentally since the calculations would involve large amount of data associated with the electronic design, as normally found in the art of computer-aided design and analysis of circuits; nor are the claims directed to certain methods of organizing human activity.
Conclusion
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/PHALLAKA KIK/Primary Examiner, Art Unit 2851 March 28, 2026
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